1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82572EI_COPPER 0x107D 90 #define E1000_DEV_ID_82572EI_FIBER 0x107E 91 #define E1000_DEV_ID_82572EI_SERDES 0x107F 92 #define E1000_DEV_ID_82572EI 0x10B9 93 #define E1000_DEV_ID_82573E 0x108B 94 #define E1000_DEV_ID_82573E_IAMT 0x108C 95 #define E1000_DEV_ID_82573L 0x109A 96 #define E1000_DEV_ID_82574L 0x10D3 97 #define E1000_DEV_ID_82574LA 0x10F6 98 #define E1000_DEV_ID_82583V 0x150C 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 107 #define E1000_DEV_ID_ICH8_IFE 0x104C 108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115 #define E1000_DEV_ID_ICH9_BM 0x10E5 116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 117 #define E1000_DEV_ID_ICH9_IFE 0x10C0 118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 125 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 126 127 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 128 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 129 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 130 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 131 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 132 #define E1000_DEV_ID_PCH2_LV_V 0x1503 133 #define E1000_DEV_ID_82576 0x10C9 134 #define E1000_DEV_ID_82576_FIBER 0x10E6 135 #define E1000_DEV_ID_82576_SERDES 0x10E7 136 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 137 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 138 #define E1000_DEV_ID_82576_NS 0x150A 139 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 140 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 141 #define E1000_DEV_ID_82576_VF 0x10CA 142 #define E1000_DEV_ID_I350_VF 0x1520 143 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 144 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 145 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 146 #define E1000_DEV_ID_82580_COPPER 0x150E 147 #define E1000_DEV_ID_82580_FIBER 0x150F 148 #define E1000_DEV_ID_82580_SERDES 0x1510 149 #define E1000_DEV_ID_82580_SGMII 0x1511 150 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 151 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 152 #define E1000_DEV_ID_I350_COPPER 0x1521 153 #define E1000_DEV_ID_I350_FIBER 0x1522 154 #define E1000_DEV_ID_I350_SERDES 0x1523 155 #define E1000_DEV_ID_I350_SGMII 0x1524 156 #define E1000_DEV_ID_I350_DA4 0x1546 157 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 158 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 159 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 160 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 161 #define E1000_REVISION_0 0 162 #define E1000_REVISION_1 1 163 #define E1000_REVISION_2 2 164 #define E1000_REVISION_3 3 165 #define E1000_REVISION_4 4 166 167 #define E1000_FUNC_0 0 168 #define E1000_FUNC_1 1 169 #define E1000_FUNC_2 2 170 #define E1000_FUNC_3 3 171 172 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 173 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 174 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 175 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 176 177 enum e1000_mac_type { 178 e1000_undefined = 0, 179 e1000_82542, 180 e1000_82543, 181 e1000_82544, 182 e1000_82540, 183 e1000_82545, 184 e1000_82545_rev_3, 185 e1000_82546, 186 e1000_82546_rev_3, 187 e1000_82541, 188 e1000_82541_rev_2, 189 e1000_82547, 190 e1000_82547_rev_2, 191 e1000_82571, 192 e1000_82572, 193 e1000_82573, 194 e1000_82574, 195 e1000_82583, 196 e1000_80003es2lan, 197 e1000_ich8lan, 198 e1000_ich9lan, 199 e1000_ich10lan, 200 e1000_pchlan, 201 e1000_pch2lan, 202 e1000_82575, 203 e1000_82576, 204 e1000_82580, 205 e1000_i350, 206 e1000_vfadapt, 207 e1000_vfadapt_i350, 208 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 209 }; 210 211 enum e1000_media_type { 212 e1000_media_type_unknown = 0, 213 e1000_media_type_copper = 1, 214 e1000_media_type_fiber = 2, 215 e1000_media_type_internal_serdes = 3, 216 e1000_num_media_types 217 }; 218 219 enum e1000_nvm_type { 220 e1000_nvm_unknown = 0, 221 e1000_nvm_none, 222 e1000_nvm_eeprom_spi, 223 e1000_nvm_eeprom_microwire, 224 e1000_nvm_flash_hw, 225 e1000_nvm_flash_sw 226 }; 227 228 enum e1000_nvm_override { 229 e1000_nvm_override_none = 0, 230 e1000_nvm_override_spi_small, 231 e1000_nvm_override_spi_large, 232 e1000_nvm_override_microwire_small, 233 e1000_nvm_override_microwire_large 234 }; 235 236 enum e1000_phy_type { 237 e1000_phy_unknown = 0, 238 e1000_phy_none, 239 e1000_phy_m88, 240 e1000_phy_igp, 241 e1000_phy_igp_2, 242 e1000_phy_gg82563, 243 e1000_phy_igp_3, 244 e1000_phy_ife, 245 e1000_phy_bm, 246 e1000_phy_82578, 247 e1000_phy_82577, 248 e1000_phy_82579, 249 e1000_phy_82580, 250 e1000_phy_vf, 251 }; 252 253 enum e1000_bus_type { 254 e1000_bus_type_unknown = 0, 255 e1000_bus_type_pci, 256 e1000_bus_type_pcix, 257 e1000_bus_type_pci_express, 258 e1000_bus_type_reserved 259 }; 260 261 enum e1000_bus_speed { 262 e1000_bus_speed_unknown = 0, 263 e1000_bus_speed_33, 264 e1000_bus_speed_66, 265 e1000_bus_speed_100, 266 e1000_bus_speed_120, 267 e1000_bus_speed_133, 268 e1000_bus_speed_2500, 269 e1000_bus_speed_5000, 270 e1000_bus_speed_reserved 271 }; 272 273 enum e1000_bus_width { 274 e1000_bus_width_unknown = 0, 275 e1000_bus_width_pcie_x1, 276 e1000_bus_width_pcie_x2, 277 e1000_bus_width_pcie_x4 = 4, 278 e1000_bus_width_pcie_x8 = 8, 279 e1000_bus_width_32, 280 e1000_bus_width_64, 281 e1000_bus_width_reserved 282 }; 283 284 enum e1000_1000t_rx_status { 285 e1000_1000t_rx_status_not_ok = 0, 286 e1000_1000t_rx_status_ok, 287 e1000_1000t_rx_status_undefined = 0xFF 288 }; 289 290 enum e1000_rev_polarity { 291 e1000_rev_polarity_normal = 0, 292 e1000_rev_polarity_reversed, 293 e1000_rev_polarity_undefined = 0xFF 294 }; 295 296 enum e1000_fc_mode { 297 e1000_fc_none = 0, 298 e1000_fc_rx_pause, 299 e1000_fc_tx_pause, 300 e1000_fc_full, 301 e1000_fc_default = 0xFF 302 }; 303 304 enum e1000_ffe_config { 305 e1000_ffe_config_enabled = 0, 306 e1000_ffe_config_active, 307 e1000_ffe_config_blocked 308 }; 309 310 enum e1000_dsp_config { 311 e1000_dsp_config_disabled = 0, 312 e1000_dsp_config_enabled, 313 e1000_dsp_config_activated, 314 e1000_dsp_config_undefined = 0xFF 315 }; 316 317 enum e1000_ms_type { 318 e1000_ms_hw_default = 0, 319 e1000_ms_force_master, 320 e1000_ms_force_slave, 321 e1000_ms_auto 322 }; 323 324 enum e1000_smart_speed { 325 e1000_smart_speed_default = 0, 326 e1000_smart_speed_on, 327 e1000_smart_speed_off 328 }; 329 330 enum e1000_serdes_link_state { 331 e1000_serdes_link_down = 0, 332 e1000_serdes_link_autoneg_progress, 333 e1000_serdes_link_autoneg_complete, 334 e1000_serdes_link_forced_up 335 }; 336 337 #define __le16 u16 338 #define __le32 u32 339 #define __le64 u64 340 /* Receive Descriptor */ 341 struct e1000_rx_desc { 342 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 343 __le16 length; /* Length of data DMAed into data buffer */ 344 __le16 csum; /* Packet checksum */ 345 u8 status; /* Descriptor status */ 346 u8 errors; /* Descriptor Errors */ 347 __le16 special; 348 }; 349 350 /* Receive Descriptor - Extended */ 351 union e1000_rx_desc_extended { 352 struct { 353 __le64 buffer_addr; 354 __le64 reserved; 355 } read; 356 struct { 357 struct { 358 __le32 mrq; /* Multiple Rx Queues */ 359 union { 360 __le32 rss; /* RSS Hash */ 361 struct { 362 __le16 ip_id; /* IP id */ 363 __le16 csum; /* Packet Checksum */ 364 } csum_ip; 365 } hi_dword; 366 } lower; 367 struct { 368 __le32 status_error; /* ext status/error */ 369 __le16 length; 370 __le16 vlan; /* VLAN tag */ 371 } upper; 372 } wb; /* writeback */ 373 }; 374 375 #define MAX_PS_BUFFERS 4 376 /* Receive Descriptor - Packet Split */ 377 union e1000_rx_desc_packet_split { 378 struct { 379 /* one buffer for protocol header(s), three data buffers */ 380 __le64 buffer_addr[MAX_PS_BUFFERS]; 381 } read; 382 struct { 383 struct { 384 __le32 mrq; /* Multiple Rx Queues */ 385 union { 386 __le32 rss; /* RSS Hash */ 387 struct { 388 __le16 ip_id; /* IP id */ 389 __le16 csum; /* Packet Checksum */ 390 } csum_ip; 391 } hi_dword; 392 } lower; 393 struct { 394 __le32 status_error; /* ext status/error */ 395 __le16 length0; /* length of buffer 0 */ 396 __le16 vlan; /* VLAN tag */ 397 } middle; 398 struct { 399 __le16 header_status; 400 __le16 length[3]; /* length of buffers 1-3 */ 401 } upper; 402 __le64 reserved; 403 } wb; /* writeback */ 404 }; 405 406 /* Transmit Descriptor */ 407 struct e1000_tx_desc { 408 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 409 union { 410 __le32 data; 411 struct { 412 __le16 length; /* Data buffer length */ 413 u8 cso; /* Checksum offset */ 414 u8 cmd; /* Descriptor control */ 415 } flags; 416 } lower; 417 union { 418 __le32 data; 419 struct { 420 u8 status; /* Descriptor status */ 421 u8 css; /* Checksum start */ 422 __le16 special; 423 } fields; 424 } upper; 425 }; 426 427 /* Offload Context Descriptor */ 428 struct e1000_context_desc { 429 union { 430 __le32 ip_config; 431 struct { 432 u8 ipcss; /* IP checksum start */ 433 u8 ipcso; /* IP checksum offset */ 434 __le16 ipcse; /* IP checksum end */ 435 } ip_fields; 436 } lower_setup; 437 union { 438 __le32 tcp_config; 439 struct { 440 u8 tucss; /* TCP checksum start */ 441 u8 tucso; /* TCP checksum offset */ 442 __le16 tucse; /* TCP checksum end */ 443 } tcp_fields; 444 } upper_setup; 445 __le32 cmd_and_length; 446 union { 447 __le32 data; 448 struct { 449 u8 status; /* Descriptor status */ 450 u8 hdr_len; /* Header length */ 451 __le16 mss; /* Maximum segment size */ 452 } fields; 453 } tcp_seg_setup; 454 }; 455 456 /* Offload data descriptor */ 457 struct e1000_data_desc { 458 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 459 union { 460 __le32 data; 461 struct { 462 __le16 length; /* Data buffer length */ 463 u8 typ_len_ext; 464 u8 cmd; 465 } flags; 466 } lower; 467 union { 468 __le32 data; 469 struct { 470 u8 status; /* Descriptor status */ 471 u8 popts; /* Packet Options */ 472 __le16 special; 473 } fields; 474 } upper; 475 }; 476 477 /* Statistics counters collected by the MAC */ 478 struct e1000_hw_stats { 479 u64 crcerrs; 480 u64 algnerrc; 481 u64 symerrs; 482 u64 rxerrc; 483 u64 mpc; 484 u64 scc; 485 u64 ecol; 486 u64 mcc; 487 u64 latecol; 488 u64 colc; 489 u64 dc; 490 u64 tncrs; 491 u64 sec; 492 u64 cexterr; 493 u64 rlec; 494 u64 xonrxc; 495 u64 xontxc; 496 u64 xoffrxc; 497 u64 xofftxc; 498 u64 fcruc; 499 u64 prc64; 500 u64 prc127; 501 u64 prc255; 502 u64 prc511; 503 u64 prc1023; 504 u64 prc1522; 505 u64 gprc; 506 u64 bprc; 507 u64 mprc; 508 u64 gptc; 509 u64 gorc; 510 u64 gotc; 511 u64 rnbc; 512 u64 ruc; 513 u64 rfc; 514 u64 roc; 515 u64 rjc; 516 u64 mgprc; 517 u64 mgpdc; 518 u64 mgptc; 519 u64 tor; 520 u64 tot; 521 u64 tpr; 522 u64 tpt; 523 u64 ptc64; 524 u64 ptc127; 525 u64 ptc255; 526 u64 ptc511; 527 u64 ptc1023; 528 u64 ptc1522; 529 u64 mptc; 530 u64 bptc; 531 u64 tsctc; 532 u64 tsctfc; 533 u64 iac; 534 u64 icrxptc; 535 u64 icrxatc; 536 u64 ictxptc; 537 u64 ictxatc; 538 u64 ictxqec; 539 u64 ictxqmtc; 540 u64 icrxdmtc; 541 u64 icrxoc; 542 u64 cbtmpc; 543 u64 htdpmc; 544 u64 cbrdpc; 545 u64 cbrmpc; 546 u64 rpthc; 547 u64 hgptc; 548 u64 htcbdpc; 549 u64 hgorc; 550 u64 hgotc; 551 u64 lenerrs; 552 u64 scvpc; 553 u64 hrmpc; 554 u64 doosync; 555 u64 o2bgptc; 556 u64 o2bspc; 557 u64 b2ospc; 558 u64 b2ogprc; 559 }; 560 561 struct e1000_vf_stats { 562 u64 base_gprc; 563 u64 base_gptc; 564 u64 base_gorc; 565 u64 base_gotc; 566 u64 base_mprc; 567 u64 base_gotlbc; 568 u64 base_gptlbc; 569 u64 base_gorlbc; 570 u64 base_gprlbc; 571 572 u32 last_gprc; 573 u32 last_gptc; 574 u32 last_gorc; 575 u32 last_gotc; 576 u32 last_mprc; 577 u32 last_gotlbc; 578 u32 last_gptlbc; 579 u32 last_gorlbc; 580 u32 last_gprlbc; 581 582 u64 gprc; 583 u64 gptc; 584 u64 gorc; 585 u64 gotc; 586 u64 mprc; 587 u64 gotlbc; 588 u64 gptlbc; 589 u64 gorlbc; 590 u64 gprlbc; 591 }; 592 593 struct e1000_phy_stats { 594 u32 idle_errors; 595 u32 receive_errors; 596 }; 597 598 struct e1000_host_mng_dhcp_cookie { 599 u32 signature; 600 u8 status; 601 u8 reserved0; 602 u16 vlan_id; 603 u32 reserved1; 604 u16 reserved2; 605 u8 reserved3; 606 u8 checksum; 607 }; 608 609 /* Host Interface "Rev 1" */ 610 struct e1000_host_command_header { 611 u8 command_id; 612 u8 command_length; 613 u8 command_options; 614 u8 checksum; 615 }; 616 617 #define E1000_HI_MAX_DATA_LENGTH 252 618 struct e1000_host_command_info { 619 struct e1000_host_command_header command_header; 620 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 621 }; 622 623 /* Host Interface "Rev 2" */ 624 struct e1000_host_mng_command_header { 625 u8 command_id; 626 u8 checksum; 627 u16 reserved1; 628 u16 reserved2; 629 u16 command_length; 630 }; 631 632 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 633 struct e1000_host_mng_command_info { 634 struct e1000_host_mng_command_header command_header; 635 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 636 }; 637 638 #include "e1000_mac.h" 639 #include "e1000_phy.h" 640 #include "e1000_nvm.h" 641 #include "e1000_manage.h" 642 #include "e1000_mbx.h" 643 644 struct e1000_mac_operations { 645 /* Function pointers for the MAC. */ 646 s32 (*init_params)(struct e1000_hw *); 647 s32 (*id_led_init)(struct e1000_hw *); 648 s32 (*blink_led)(struct e1000_hw *); 649 s32 (*check_for_link)(struct e1000_hw *); 650 bool (*check_mng_mode)(struct e1000_hw *hw); 651 s32 (*cleanup_led)(struct e1000_hw *); 652 void (*clear_hw_cntrs)(struct e1000_hw *); 653 void (*clear_vfta)(struct e1000_hw *); 654 s32 (*get_bus_info)(struct e1000_hw *); 655 void (*set_lan_id)(struct e1000_hw *); 656 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 657 s32 (*led_on)(struct e1000_hw *); 658 s32 (*led_off)(struct e1000_hw *); 659 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 660 s32 (*reset_hw)(struct e1000_hw *); 661 s32 (*init_hw)(struct e1000_hw *); 662 void (*shutdown_serdes)(struct e1000_hw *); 663 void (*power_up_serdes)(struct e1000_hw *); 664 s32 (*setup_link)(struct e1000_hw *); 665 s32 (*setup_physical_interface)(struct e1000_hw *); 666 s32 (*setup_led)(struct e1000_hw *); 667 void (*write_vfta)(struct e1000_hw *, u32, u32); 668 void (*config_collision_dist)(struct e1000_hw *); 669 void (*rar_set)(struct e1000_hw *, u8*, u32); 670 s32 (*read_mac_addr)(struct e1000_hw *); 671 s32 (*validate_mdi_setting)(struct e1000_hw *); 672 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); 673 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 674 struct e1000_host_mng_command_header*); 675 s32 (*mng_enable_host_if)(struct e1000_hw *); 676 s32 (*wait_autoneg)(struct e1000_hw *); 677 }; 678 679 /* 680 * When to use various PHY register access functions: 681 * 682 * Func Caller 683 * Function Does Does When to use 684 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 685 * X_reg L,P,A n/a for simple PHY reg accesses 686 * X_reg_locked P,A L for multiple accesses of different regs 687 * on different pages 688 * X_reg_page A L,P for multiple accesses of different regs 689 * on the same page 690 * 691 * Where X=[read|write], L=locking, P=sets page, A=register access 692 * 693 */ 694 struct e1000_phy_operations { 695 s32 (*init_params)(struct e1000_hw *); 696 s32 (*acquire)(struct e1000_hw *); 697 s32 (*cfg_on_link_up)(struct e1000_hw *); 698 s32 (*check_polarity)(struct e1000_hw *); 699 s32 (*check_reset_block)(struct e1000_hw *); 700 s32 (*commit)(struct e1000_hw *); 701 s32 (*force_speed_duplex)(struct e1000_hw *); 702 s32 (*get_cfg_done)(struct e1000_hw *hw); 703 s32 (*get_cable_length)(struct e1000_hw *); 704 s32 (*get_info)(struct e1000_hw *); 705 s32 (*set_page)(struct e1000_hw *, u16); 706 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 707 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 708 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 709 void (*release)(struct e1000_hw *); 710 s32 (*reset)(struct e1000_hw *); 711 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 712 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 713 s32 (*write_reg)(struct e1000_hw *, u32, u16); 714 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 715 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 716 void (*power_up)(struct e1000_hw *); 717 void (*power_down)(struct e1000_hw *); 718 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 719 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 720 }; 721 722 struct e1000_nvm_operations { 723 s32 (*init_params)(struct e1000_hw *); 724 s32 (*acquire)(struct e1000_hw *); 725 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 726 void (*release)(struct e1000_hw *); 727 void (*reload)(struct e1000_hw *); 728 s32 (*update)(struct e1000_hw *); 729 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 730 s32 (*validate)(struct e1000_hw *); 731 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 732 }; 733 734 struct e1000_mac_info { 735 struct e1000_mac_operations ops; 736 u8 addr[ETH_ADDR_LEN]; 737 u8 perm_addr[ETH_ADDR_LEN]; 738 739 enum e1000_mac_type type; 740 741 u32 collision_delta; 742 u32 ledctl_default; 743 u32 ledctl_mode1; 744 u32 ledctl_mode2; 745 u32 mc_filter_type; 746 u32 tx_packet_delta; 747 u32 txcw; 748 749 u16 current_ifs_val; 750 u16 ifs_max_val; 751 u16 ifs_min_val; 752 u16 ifs_ratio; 753 u16 ifs_step_size; 754 u16 mta_reg_count; 755 u16 uta_reg_count; 756 757 /* Maximum size of the MTA register table in all supported adapters */ 758 #define MAX_MTA_REG 128 759 u32 mta_shadow[MAX_MTA_REG]; 760 u16 rar_entry_count; 761 762 u8 forced_speed_duplex; 763 764 bool adaptive_ifs; 765 bool has_fwsm; 766 bool arc_subsystem_valid; 767 bool asf_firmware_present; 768 bool autoneg; 769 bool autoneg_failed; 770 bool get_link_status; 771 bool in_ifs_mode; 772 bool report_tx_early; 773 enum e1000_serdes_link_state serdes_link_state; 774 bool serdes_has_link; 775 bool tx_pkt_filtering; 776 }; 777 778 struct e1000_phy_info { 779 struct e1000_phy_operations ops; 780 enum e1000_phy_type type; 781 782 enum e1000_1000t_rx_status local_rx; 783 enum e1000_1000t_rx_status remote_rx; 784 enum e1000_ms_type ms_type; 785 enum e1000_ms_type original_ms_type; 786 enum e1000_rev_polarity cable_polarity; 787 enum e1000_smart_speed smart_speed; 788 789 u32 addr; 790 u32 id; 791 u32 reset_delay_us; /* in usec */ 792 u32 revision; 793 794 enum e1000_media_type media_type; 795 796 u16 autoneg_advertised; 797 u16 autoneg_mask; 798 u16 cable_length; 799 u16 max_cable_length; 800 u16 min_cable_length; 801 802 u8 mdix; 803 804 bool disable_polarity_correction; 805 bool is_mdix; 806 bool polarity_correction; 807 bool speed_downgraded; 808 bool autoneg_wait_to_complete; 809 }; 810 811 struct e1000_nvm_info { 812 struct e1000_nvm_operations ops; 813 enum e1000_nvm_type type; 814 enum e1000_nvm_override override; 815 816 u32 flash_bank_size; 817 u32 flash_base_addr; 818 819 u16 word_size; 820 u16 delay_usec; 821 u16 address_bits; 822 u16 opcode_bits; 823 u16 page_size; 824 }; 825 826 struct e1000_bus_info { 827 enum e1000_bus_type type; 828 enum e1000_bus_speed speed; 829 enum e1000_bus_width width; 830 831 u16 func; 832 u16 pci_cmd_word; 833 }; 834 835 struct e1000_fc_info { 836 u32 high_water; /* Flow control high-water mark */ 837 u32 low_water; /* Flow control low-water mark */ 838 u16 pause_time; /* Flow control pause timer */ 839 u16 refresh_time; /* Flow control refresh timer */ 840 bool send_xon; /* Flow control send XON */ 841 bool strict_ieee; /* Strict IEEE mode */ 842 enum e1000_fc_mode current_mode; /* FC mode in effect */ 843 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 844 }; 845 846 struct e1000_mbx_operations { 847 s32 (*init_params)(struct e1000_hw *hw); 848 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 849 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 850 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 851 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 852 s32 (*check_for_msg)(struct e1000_hw *, u16); 853 s32 (*check_for_ack)(struct e1000_hw *, u16); 854 s32 (*check_for_rst)(struct e1000_hw *, u16); 855 }; 856 857 struct e1000_mbx_stats { 858 u32 msgs_tx; 859 u32 msgs_rx; 860 861 u32 acks; 862 u32 reqs; 863 u32 rsts; 864 }; 865 866 struct e1000_mbx_info { 867 struct e1000_mbx_operations ops; 868 struct e1000_mbx_stats stats; 869 u32 timeout; 870 u32 usec_delay; 871 u16 size; 872 }; 873 874 struct e1000_dev_spec_82541 { 875 enum e1000_dsp_config dsp_config; 876 enum e1000_ffe_config ffe_config; 877 u16 spd_default; 878 bool phy_init_script; 879 }; 880 881 struct e1000_dev_spec_82542 { 882 bool dma_fairness; 883 }; 884 885 struct e1000_dev_spec_82543 { 886 u32 tbi_compatibility; 887 bool dma_fairness; 888 bool init_phy_disabled; 889 }; 890 891 struct e1000_dev_spec_82571 { 892 bool laa_is_present; 893 u32 smb_counter; 894 E1000_MUTEX swflag_mutex; 895 }; 896 897 struct e1000_dev_spec_80003es2lan { 898 bool mdic_wa_enable; 899 }; 900 901 struct e1000_shadow_ram { 902 u16 value; 903 bool modified; 904 }; 905 906 #define E1000_SHADOW_RAM_WORDS 2048 907 908 struct e1000_dev_spec_ich8lan { 909 bool kmrn_lock_loss_workaround_enabled; 910 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 911 E1000_MUTEX nvm_mutex; 912 E1000_MUTEX swflag_mutex; 913 bool nvm_k1_enabled; 914 int eee_disable; 915 }; 916 917 struct e1000_dev_spec_82575 { 918 bool sgmii_active; 919 bool global_device_reset; 920 int eee_disable; 921 bool module_plugged; 922 u32 mtu; 923 }; 924 925 struct e1000_dev_spec_vf { 926 u32 vf_number; 927 u32 v2p_mailbox; 928 }; 929 930 struct e1000_hw { 931 void *back; 932 933 u8 *hw_addr; 934 u8 *flash_address; 935 unsigned long io_base; 936 937 struct e1000_mac_info mac; 938 struct e1000_fc_info fc; 939 struct e1000_phy_info phy; 940 struct e1000_nvm_info nvm; 941 struct e1000_bus_info bus; 942 struct e1000_mbx_info mbx; 943 struct e1000_host_mng_dhcp_cookie mng_cookie; 944 945 union { 946 struct e1000_dev_spec_82541 _82541; 947 struct e1000_dev_spec_82542 _82542; 948 struct e1000_dev_spec_82543 _82543; 949 struct e1000_dev_spec_82571 _82571; 950 struct e1000_dev_spec_80003es2lan _80003es2lan; 951 struct e1000_dev_spec_ich8lan ich8lan; 952 struct e1000_dev_spec_82575 _82575; 953 struct e1000_dev_spec_vf vf; 954 } dev_spec; 955 956 u16 device_id; 957 u16 subsystem_vendor_id; 958 u16 subsystem_device_id; 959 u16 vendor_id; 960 961 u8 revision_id; 962 }; 963 964 #include "e1000_82541.h" 965 #include "e1000_82543.h" 966 #include "e1000_82571.h" 967 #include "e1000_80003es2lan.h" 968 #include "e1000_ich8lan.h" 969 #include "e1000_82575.h" 970 971 /* These functions must be implemented by drivers */ 972 void e1000_pci_clear_mwi(struct e1000_hw *hw); 973 void e1000_pci_set_mwi(struct e1000_hw *hw); 974 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 975 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 976 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 977 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 978 979 #endif 980