1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #ifndef _E1000_HW_H_ 37 #define _E1000_HW_H_ 38 39 #include "e1000_osdep.h" 40 #include "e1000_regs.h" 41 #include "e1000_defines.h" 42 43 struct e1000_hw; 44 45 #define E1000_DEV_ID_82542 0x1000 46 #define E1000_DEV_ID_82543GC_FIBER 0x1001 47 #define E1000_DEV_ID_82543GC_COPPER 0x1004 48 #define E1000_DEV_ID_82544EI_COPPER 0x1008 49 #define E1000_DEV_ID_82544EI_FIBER 0x1009 50 #define E1000_DEV_ID_82544GC_COPPER 0x100C 51 #define E1000_DEV_ID_82544GC_LOM 0x100D 52 #define E1000_DEV_ID_82540EM 0x100E 53 #define E1000_DEV_ID_82540EM_LOM 0x1015 54 #define E1000_DEV_ID_82540EP_LOM 0x1016 55 #define E1000_DEV_ID_82540EP 0x1017 56 #define E1000_DEV_ID_82540EP_LP 0x101E 57 #define E1000_DEV_ID_82545EM_COPPER 0x100F 58 #define E1000_DEV_ID_82545EM_FIBER 0x1011 59 #define E1000_DEV_ID_82545GM_COPPER 0x1026 60 #define E1000_DEV_ID_82545GM_FIBER 0x1027 61 #define E1000_DEV_ID_82545GM_SERDES 0x1028 62 #define E1000_DEV_ID_82546EB_COPPER 0x1010 63 #define E1000_DEV_ID_82546EB_FIBER 0x1012 64 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 65 #define E1000_DEV_ID_82546GB_COPPER 0x1079 66 #define E1000_DEV_ID_82546GB_FIBER 0x107A 67 #define E1000_DEV_ID_82546GB_SERDES 0x107B 68 #define E1000_DEV_ID_82546GB_PCIE 0x108A 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 70 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 71 #define E1000_DEV_ID_82541EI 0x1013 72 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 73 #define E1000_DEV_ID_82541ER_LOM 0x1014 74 #define E1000_DEV_ID_82541ER 0x1078 75 #define E1000_DEV_ID_82541GI 0x1076 76 #define E1000_DEV_ID_82541GI_LF 0x107C 77 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 78 #define E1000_DEV_ID_82547EI 0x1019 79 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 80 #define E1000_DEV_ID_82547GI 0x1075 81 #define E1000_DEV_ID_82571EB_COPPER 0x105E 82 #define E1000_DEV_ID_82571EB_FIBER 0x105F 83 #define E1000_DEV_ID_82571EB_SERDES 0x1060 84 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 85 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 86 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 87 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 88 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 90 #define E1000_DEV_ID_82572EI_COPPER 0x107D 91 #define E1000_DEV_ID_82572EI_FIBER 0x107E 92 #define E1000_DEV_ID_82572EI_SERDES 0x107F 93 #define E1000_DEV_ID_82572EI 0x10B9 94 #define E1000_DEV_ID_82573E 0x108B 95 #define E1000_DEV_ID_82573E_IAMT 0x108C 96 #define E1000_DEV_ID_82573L 0x109A 97 #define E1000_DEV_ID_82574L 0x10D3 98 #define E1000_DEV_ID_82574LA 0x10F6 99 #define E1000_DEV_ID_82583V 0x150C 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 104 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 105 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 106 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 107 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 108 #define E1000_DEV_ID_ICH8_IFE 0x104C 109 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 110 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 111 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 112 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 113 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 114 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 115 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 116 #define E1000_DEV_ID_ICH9_BM 0x10E5 117 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 118 #define E1000_DEV_ID_ICH9_IFE 0x10C0 119 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 120 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 121 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 122 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 123 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 124 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 128 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 129 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 130 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 131 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 132 #define E1000_DEV_ID_PCH2_LV_V 0x1503 133 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 134 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 136 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 137 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 138 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 139 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 140 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 141 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 142 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 143 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 144 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 145 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 146 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 147 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 148 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 149 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 150 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 151 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 152 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 153 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 154 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 155 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 156 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 157 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 158 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 159 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 160 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 161 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 162 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 163 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 164 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 165 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 166 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 167 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 168 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 169 #define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 170 #define E1000_DEV_ID_PCH_ADL_I219_LM16 0x1A1E 171 #define E1000_DEV_ID_PCH_ADL_I219_V16 0x1A1F 172 #define E1000_DEV_ID_PCH_ADL_I219_LM17 0x1A1C 173 #define E1000_DEV_ID_PCH_ADL_I219_V17 0x1A1D 174 #define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A 175 #define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B 176 #define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C 177 #define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D 178 #define E1000_DEV_ID_PCH_LNL_I219_LM20 0x550E 179 #define E1000_DEV_ID_PCH_LNL_I219_V20 0x550F 180 #define E1000_DEV_ID_PCH_LNL_I219_LM21 0x5510 181 #define E1000_DEV_ID_PCH_LNL_I219_V21 0x5511 182 #define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7 183 #define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8 184 #define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5 185 #define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6 186 #define E1000_DEV_ID_82576 0x10C9 187 #define E1000_DEV_ID_82576_FIBER 0x10E6 188 #define E1000_DEV_ID_82576_SERDES 0x10E7 189 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 190 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 191 #define E1000_DEV_ID_82576_NS 0x150A 192 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 193 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 194 #define E1000_DEV_ID_82576_VF 0x10CA 195 #define E1000_DEV_ID_82576_VF_HV 0x152D 196 #define E1000_DEV_ID_I350_VF 0x1520 197 #define E1000_DEV_ID_I350_VF_HV 0x152F 198 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 199 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 200 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 201 #define E1000_DEV_ID_82580_COPPER 0x150E 202 #define E1000_DEV_ID_82580_FIBER 0x150F 203 #define E1000_DEV_ID_82580_SERDES 0x1510 204 #define E1000_DEV_ID_82580_SGMII 0x1511 205 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 206 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 207 #define E1000_DEV_ID_I350_COPPER 0x1521 208 #define E1000_DEV_ID_I350_FIBER 0x1522 209 #define E1000_DEV_ID_I350_SERDES 0x1523 210 #define E1000_DEV_ID_I350_SGMII 0x1524 211 #define E1000_DEV_ID_I350_DA4 0x1546 212 #define E1000_DEV_ID_I210_COPPER 0x1533 213 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 214 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 215 #define E1000_DEV_ID_I210_FIBER 0x1536 216 #define E1000_DEV_ID_I210_SERDES 0x1537 217 #define E1000_DEV_ID_I210_SGMII 0x1538 218 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 219 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 220 #define E1000_DEV_ID_I210_SGMII_FLASHLESS 0x15F6 221 #define E1000_DEV_ID_I211_COPPER 0x1539 222 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 223 #define E1000_DEV_ID_I354_SGMII 0x1F41 224 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 225 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 226 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 227 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 228 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 229 230 #define E1000_REVISION_0 0 231 #define E1000_REVISION_1 1 232 #define E1000_REVISION_2 2 233 #define E1000_REVISION_3 3 234 #define E1000_REVISION_4 4 235 236 #define E1000_FUNC_0 0 237 #define E1000_FUNC_1 1 238 #define E1000_FUNC_2 2 239 #define E1000_FUNC_3 3 240 241 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 242 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 243 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 244 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 245 246 enum e1000_mac_type { 247 e1000_undefined = 0, 248 e1000_82542, 249 e1000_82543, 250 e1000_82544, 251 e1000_82540, 252 e1000_82545, 253 e1000_82545_rev_3, 254 e1000_82546, 255 e1000_82546_rev_3, 256 e1000_82541, 257 e1000_82541_rev_2, 258 e1000_82547, 259 e1000_82547_rev_2, 260 e1000_82571, 261 e1000_82572, 262 e1000_82573, 263 e1000_82574, 264 e1000_82583, 265 e1000_80003es2lan, 266 e1000_ich8lan, 267 e1000_ich9lan, 268 e1000_ich10lan, 269 e1000_pchlan, 270 e1000_pch2lan, 271 e1000_pch_lpt, 272 e1000_pch_spt, 273 e1000_pch_cnp, 274 e1000_pch_tgp, 275 e1000_pch_adp, 276 e1000_pch_mtp, 277 e1000_82575, 278 e1000_82576, 279 e1000_82580, 280 e1000_i350, 281 e1000_i354, 282 e1000_i210, 283 e1000_i211, 284 e1000_vfadapt, 285 e1000_vfadapt_i350, 286 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 287 }; 288 289 enum e1000_media_type { 290 e1000_media_type_unknown = 0, 291 e1000_media_type_copper = 1, 292 e1000_media_type_fiber = 2, 293 e1000_media_type_internal_serdes = 3, 294 e1000_num_media_types 295 }; 296 297 enum e1000_nvm_type { 298 e1000_nvm_unknown = 0, 299 e1000_nvm_none, 300 e1000_nvm_eeprom_spi, 301 e1000_nvm_eeprom_microwire, 302 e1000_nvm_flash_hw, 303 e1000_nvm_invm, 304 e1000_nvm_flash_sw 305 }; 306 307 enum e1000_nvm_override { 308 e1000_nvm_override_none = 0, 309 e1000_nvm_override_spi_small, 310 e1000_nvm_override_spi_large, 311 e1000_nvm_override_microwire_small, 312 e1000_nvm_override_microwire_large 313 }; 314 315 enum e1000_phy_type { 316 e1000_phy_unknown = 0, 317 e1000_phy_none, 318 e1000_phy_m88, 319 e1000_phy_igp, 320 e1000_phy_igp_2, 321 e1000_phy_gg82563, 322 e1000_phy_igp_3, 323 e1000_phy_ife, 324 e1000_phy_bm, 325 e1000_phy_82578, 326 e1000_phy_82577, 327 e1000_phy_82579, 328 e1000_phy_i217, 329 e1000_phy_82580, 330 e1000_phy_vf, 331 e1000_phy_i210, 332 }; 333 334 enum e1000_bus_type { 335 e1000_bus_type_unknown = 0, 336 e1000_bus_type_pci, 337 e1000_bus_type_pcix, 338 e1000_bus_type_pci_express, 339 e1000_bus_type_reserved 340 }; 341 342 enum e1000_bus_speed { 343 e1000_bus_speed_unknown = 0, 344 e1000_bus_speed_33, 345 e1000_bus_speed_66, 346 e1000_bus_speed_100, 347 e1000_bus_speed_120, 348 e1000_bus_speed_133, 349 e1000_bus_speed_2500, 350 e1000_bus_speed_5000, 351 e1000_bus_speed_reserved 352 }; 353 354 enum e1000_bus_width { 355 e1000_bus_width_unknown = 0, 356 e1000_bus_width_pcie_x1, 357 e1000_bus_width_pcie_x2, 358 e1000_bus_width_pcie_x4 = 4, 359 e1000_bus_width_pcie_x8 = 8, 360 e1000_bus_width_32, 361 e1000_bus_width_64, 362 e1000_bus_width_reserved 363 }; 364 365 enum e1000_1000t_rx_status { 366 e1000_1000t_rx_status_not_ok = 0, 367 e1000_1000t_rx_status_ok, 368 e1000_1000t_rx_status_undefined = 0xFF 369 }; 370 371 enum e1000_rev_polarity { 372 e1000_rev_polarity_normal = 0, 373 e1000_rev_polarity_reversed, 374 e1000_rev_polarity_undefined = 0xFF 375 }; 376 377 enum e1000_fc_mode { 378 e1000_fc_none = 0, 379 e1000_fc_rx_pause, 380 e1000_fc_tx_pause, 381 e1000_fc_full, 382 e1000_fc_default = 0xFF 383 }; 384 385 enum e1000_ffe_config { 386 e1000_ffe_config_enabled = 0, 387 e1000_ffe_config_active, 388 e1000_ffe_config_blocked 389 }; 390 391 enum e1000_dsp_config { 392 e1000_dsp_config_disabled = 0, 393 e1000_dsp_config_enabled, 394 e1000_dsp_config_activated, 395 e1000_dsp_config_undefined = 0xFF 396 }; 397 398 enum e1000_ms_type { 399 e1000_ms_hw_default = 0, 400 e1000_ms_force_master, 401 e1000_ms_force_slave, 402 e1000_ms_auto 403 }; 404 405 enum e1000_smart_speed { 406 e1000_smart_speed_default = 0, 407 e1000_smart_speed_on, 408 e1000_smart_speed_off 409 }; 410 411 enum e1000_serdes_link_state { 412 e1000_serdes_link_down = 0, 413 e1000_serdes_link_autoneg_progress, 414 e1000_serdes_link_autoneg_complete, 415 e1000_serdes_link_forced_up 416 }; 417 418 #define __le16 u16 419 #define __le32 u32 420 #define __le64 u64 421 /* Receive Descriptor */ 422 struct e1000_rx_desc { 423 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 424 __le16 length; /* Length of data DMAed into data buffer */ 425 __le16 csum; /* Packet checksum */ 426 u8 status; /* Descriptor status */ 427 u8 errors; /* Descriptor Errors */ 428 __le16 special; 429 }; 430 431 /* Receive Descriptor - Extended */ 432 union e1000_rx_desc_extended { 433 struct { 434 __le64 buffer_addr; 435 __le64 reserved; 436 } read; 437 struct { 438 struct { 439 __le32 mrq; /* Multiple Rx Queues */ 440 union { 441 __le32 rss; /* RSS Hash */ 442 struct { 443 __le16 ip_id; /* IP id */ 444 __le16 csum; /* Packet Checksum */ 445 } csum_ip; 446 } hi_dword; 447 } lower; 448 struct { 449 __le32 status_error; /* ext status/error */ 450 __le16 length; 451 __le16 vlan; /* VLAN tag */ 452 } upper; 453 } wb; /* writeback */ 454 }; 455 456 #define MAX_PS_BUFFERS 4 457 458 /* Number of packet split data buffers (not including the header buffer) */ 459 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 460 461 /* Receive Descriptor - Packet Split */ 462 union e1000_rx_desc_packet_split { 463 struct { 464 /* one buffer for protocol header(s), three data buffers */ 465 __le64 buffer_addr[MAX_PS_BUFFERS]; 466 } read; 467 struct { 468 struct { 469 __le32 mrq; /* Multiple Rx Queues */ 470 union { 471 __le32 rss; /* RSS Hash */ 472 struct { 473 __le16 ip_id; /* IP id */ 474 __le16 csum; /* Packet Checksum */ 475 } csum_ip; 476 } hi_dword; 477 } lower; 478 struct { 479 __le32 status_error; /* ext status/error */ 480 __le16 length0; /* length of buffer 0 */ 481 __le16 vlan; /* VLAN tag */ 482 } middle; 483 struct { 484 __le16 header_status; 485 /* length of buffers 1-3 */ 486 __le16 length[PS_PAGE_BUFFERS]; 487 } upper; 488 __le64 reserved; 489 } wb; /* writeback */ 490 }; 491 492 /* Transmit Descriptor */ 493 struct e1000_tx_desc { 494 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 495 union { 496 __le32 data; 497 struct { 498 __le16 length; /* Data buffer length */ 499 u8 cso; /* Checksum offset */ 500 u8 cmd; /* Descriptor control */ 501 } flags; 502 } lower; 503 union { 504 __le32 data; 505 struct { 506 u8 status; /* Descriptor status */ 507 u8 css; /* Checksum start */ 508 __le16 special; 509 } fields; 510 } upper; 511 }; 512 513 /* Offload Context Descriptor */ 514 struct e1000_context_desc { 515 union { 516 __le32 ip_config; 517 struct { 518 u8 ipcss; /* IP checksum start */ 519 u8 ipcso; /* IP checksum offset */ 520 __le16 ipcse; /* IP checksum end */ 521 } ip_fields; 522 } lower_setup; 523 union { 524 __le32 tcp_config; 525 struct { 526 u8 tucss; /* TCP checksum start */ 527 u8 tucso; /* TCP checksum offset */ 528 __le16 tucse; /* TCP checksum end */ 529 } tcp_fields; 530 } upper_setup; 531 __le32 cmd_and_length; 532 union { 533 __le32 data; 534 struct { 535 u8 status; /* Descriptor status */ 536 u8 hdr_len; /* Header length */ 537 __le16 mss; /* Maximum segment size */ 538 } fields; 539 } tcp_seg_setup; 540 }; 541 542 /* Offload data descriptor */ 543 struct e1000_data_desc { 544 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 545 union { 546 __le32 data; 547 struct { 548 __le16 length; /* Data buffer length */ 549 u8 typ_len_ext; 550 u8 cmd; 551 } flags; 552 } lower; 553 union { 554 __le32 data; 555 struct { 556 u8 status; /* Descriptor status */ 557 u8 popts; /* Packet Options */ 558 __le16 special; 559 } fields; 560 } upper; 561 }; 562 563 /* Statistics counters collected by the MAC */ 564 struct e1000_hw_stats { 565 u64 crcerrs; 566 u64 algnerrc; 567 u64 symerrs; 568 u64 rxerrc; 569 u64 mpc; 570 u64 scc; 571 u64 ecol; 572 u64 mcc; 573 u64 latecol; 574 u64 colc; 575 u64 dc; 576 u64 tncrs; 577 u64 sec; 578 u64 cexterr; 579 u64 rlec; 580 u64 xonrxc; 581 u64 xontxc; 582 u64 xoffrxc; 583 u64 xofftxc; 584 u64 fcruc; 585 u64 prc64; 586 u64 prc127; 587 u64 prc255; 588 u64 prc511; 589 u64 prc1023; 590 u64 prc1522; 591 u64 gprc; 592 u64 bprc; 593 u64 mprc; 594 u64 gptc; 595 u64 gorc; 596 u64 gotc; 597 u64 rnbc; 598 u64 ruc; 599 u64 rfc; 600 u64 roc; 601 u64 rjc; 602 u64 mgprc; 603 u64 mgpdc; 604 u64 mgptc; 605 u64 tor; 606 u64 tot; 607 u64 tpr; 608 u64 tpt; 609 u64 ptc64; 610 u64 ptc127; 611 u64 ptc255; 612 u64 ptc511; 613 u64 ptc1023; 614 u64 ptc1522; 615 u64 mptc; 616 u64 bptc; 617 u64 tsctc; 618 u64 tsctfc; 619 u64 iac; 620 u64 icrxptc; 621 u64 icrxatc; 622 u64 ictxptc; 623 u64 ictxatc; 624 u64 ictxqec; 625 u64 ictxqmtc; 626 u64 icrxdmtc; 627 u64 icrxoc; 628 u64 cbtmpc; 629 u64 htdpmc; 630 u64 cbrdpc; 631 u64 cbrmpc; 632 u64 rpthc; 633 u64 hgptc; 634 u64 htcbdpc; 635 u64 hgorc; 636 u64 hgotc; 637 u64 lenerrs; 638 u64 scvpc; 639 u64 hrmpc; 640 u64 doosync; 641 u64 o2bgptc; 642 u64 o2bspc; 643 u64 b2ospc; 644 u64 b2ogprc; 645 }; 646 647 struct e1000_vf_stats { 648 u64 base_gprc; 649 u64 base_gptc; 650 u64 base_gorc; 651 u64 base_gotc; 652 u64 base_mprc; 653 u64 base_gotlbc; 654 u64 base_gptlbc; 655 u64 base_gorlbc; 656 u64 base_gprlbc; 657 658 u32 last_gprc; 659 u32 last_gptc; 660 u32 last_gorc; 661 u32 last_gotc; 662 u32 last_mprc; 663 u32 last_gotlbc; 664 u32 last_gptlbc; 665 u32 last_gorlbc; 666 u32 last_gprlbc; 667 668 u64 gprc; 669 u64 gptc; 670 u64 gorc; 671 u64 gotc; 672 u64 mprc; 673 u64 gotlbc; 674 u64 gptlbc; 675 u64 gorlbc; 676 u64 gprlbc; 677 }; 678 679 struct e1000_phy_stats { 680 u32 idle_errors; 681 u32 receive_errors; 682 }; 683 684 struct e1000_host_mng_dhcp_cookie { 685 u32 signature; 686 u8 status; 687 u8 reserved0; 688 u16 vlan_id; 689 u32 reserved1; 690 u16 reserved2; 691 u8 reserved3; 692 u8 checksum; 693 }; 694 695 /* Host Interface "Rev 1" */ 696 struct e1000_host_command_header { 697 u8 command_id; 698 u8 command_length; 699 u8 command_options; 700 u8 checksum; 701 }; 702 703 #define E1000_HI_MAX_DATA_LENGTH 252 704 struct e1000_host_command_info { 705 struct e1000_host_command_header command_header; 706 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 707 }; 708 709 /* Host Interface "Rev 2" */ 710 struct e1000_host_mng_command_header { 711 u8 command_id; 712 u8 checksum; 713 u16 reserved1; 714 u16 reserved2; 715 u16 command_length; 716 }; 717 718 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 719 struct e1000_host_mng_command_info { 720 struct e1000_host_mng_command_header command_header; 721 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 722 }; 723 724 #include "e1000_mac.h" 725 #include "e1000_phy.h" 726 #include "e1000_nvm.h" 727 #include "e1000_manage.h" 728 #include "e1000_mbx.h" 729 730 /* Function pointers for the MAC. */ 731 struct e1000_mac_operations { 732 s32 (*init_params)(struct e1000_hw *); 733 s32 (*id_led_init)(struct e1000_hw *); 734 s32 (*blink_led)(struct e1000_hw *); 735 bool (*check_mng_mode)(struct e1000_hw *); 736 s32 (*check_for_link)(struct e1000_hw *); 737 s32 (*cleanup_led)(struct e1000_hw *); 738 void (*clear_hw_cntrs)(struct e1000_hw *); 739 void (*clear_vfta)(struct e1000_hw *); 740 s32 (*get_bus_info)(struct e1000_hw *); 741 void (*set_lan_id)(struct e1000_hw *); 742 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 743 s32 (*led_on)(struct e1000_hw *); 744 s32 (*led_off)(struct e1000_hw *); 745 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 746 s32 (*reset_hw)(struct e1000_hw *); 747 s32 (*init_hw)(struct e1000_hw *); 748 void (*shutdown_serdes)(struct e1000_hw *); 749 void (*power_up_serdes)(struct e1000_hw *); 750 s32 (*setup_link)(struct e1000_hw *); 751 s32 (*setup_physical_interface)(struct e1000_hw *); 752 s32 (*setup_led)(struct e1000_hw *); 753 void (*write_vfta)(struct e1000_hw *, u32, u32); 754 void (*config_collision_dist)(struct e1000_hw *); 755 int (*rar_set)(struct e1000_hw *, u8*, u32); 756 s32 (*read_mac_addr)(struct e1000_hw *); 757 s32 (*validate_mdi_setting)(struct e1000_hw *); 758 s32 (*set_obff_timer)(struct e1000_hw *, u32); 759 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 760 void (*release_swfw_sync)(struct e1000_hw *, u16); 761 }; 762 763 /* When to use various PHY register access functions: 764 * 765 * Func Caller 766 * Function Does Does When to use 767 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 768 * X_reg L,P,A n/a for simple PHY reg accesses 769 * X_reg_locked P,A L for multiple accesses of different regs 770 * on different pages 771 * X_reg_page A L,P for multiple accesses of different regs 772 * on the same page 773 * 774 * Where X=[read|write], L=locking, P=sets page, A=register access 775 * 776 */ 777 struct e1000_phy_operations { 778 s32 (*init_params)(struct e1000_hw *); 779 s32 (*acquire)(struct e1000_hw *); 780 s32 (*cfg_on_link_up)(struct e1000_hw *); 781 s32 (*check_polarity)(struct e1000_hw *); 782 s32 (*check_reset_block)(struct e1000_hw *); 783 s32 (*commit)(struct e1000_hw *); 784 s32 (*force_speed_duplex)(struct e1000_hw *); 785 s32 (*get_cfg_done)(struct e1000_hw *hw); 786 s32 (*get_cable_length)(struct e1000_hw *); 787 s32 (*get_info)(struct e1000_hw *); 788 s32 (*set_page)(struct e1000_hw *, u16); 789 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 790 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 791 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 792 void (*release)(struct e1000_hw *); 793 s32 (*reset)(struct e1000_hw *); 794 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 795 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 796 s32 (*write_reg)(struct e1000_hw *, u32, u16); 797 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 798 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 799 void (*power_up)(struct e1000_hw *); 800 void (*power_down)(struct e1000_hw *); 801 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 802 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 803 }; 804 805 /* Function pointers for the NVM. */ 806 struct e1000_nvm_operations { 807 s32 (*init_params)(struct e1000_hw *); 808 s32 (*acquire)(struct e1000_hw *); 809 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 810 void (*release)(struct e1000_hw *); 811 void (*reload)(struct e1000_hw *); 812 s32 (*update)(struct e1000_hw *); 813 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 814 s32 (*validate)(struct e1000_hw *); 815 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 816 }; 817 818 struct e1000_mac_info { 819 struct e1000_mac_operations ops; 820 u8 addr[ETHER_ADDR_LEN]; 821 u8 perm_addr[ETHER_ADDR_LEN]; 822 823 enum e1000_mac_type type; 824 825 u32 collision_delta; 826 u32 ledctl_default; 827 u32 ledctl_mode1; 828 u32 ledctl_mode2; 829 u32 mc_filter_type; 830 u32 tx_packet_delta; 831 u32 txcw; 832 833 u16 current_ifs_val; 834 u16 ifs_max_val; 835 u16 ifs_min_val; 836 u16 ifs_ratio; 837 u16 ifs_step_size; 838 u16 mta_reg_count; 839 u16 uta_reg_count; 840 841 /* Maximum size of the MTA register table in all supported adapters */ 842 #define MAX_MTA_REG 128 843 u32 mta_shadow[MAX_MTA_REG]; 844 u16 rar_entry_count; 845 846 u8 forced_speed_duplex; 847 848 bool adaptive_ifs; 849 bool has_fwsm; 850 bool arc_subsystem_valid; 851 bool asf_firmware_present; 852 bool autoneg; 853 bool autoneg_failed; 854 bool get_link_status; 855 bool in_ifs_mode; 856 bool report_tx_early; 857 enum e1000_serdes_link_state serdes_link_state; 858 bool serdes_has_link; 859 bool tx_pkt_filtering; 860 u32 max_frame_size; 861 }; 862 863 struct e1000_phy_info { 864 struct e1000_phy_operations ops; 865 enum e1000_phy_type type; 866 867 enum e1000_1000t_rx_status local_rx; 868 enum e1000_1000t_rx_status remote_rx; 869 enum e1000_ms_type ms_type; 870 enum e1000_ms_type original_ms_type; 871 enum e1000_rev_polarity cable_polarity; 872 enum e1000_smart_speed smart_speed; 873 874 u32 addr; 875 u32 id; 876 u32 reset_delay_us; /* in usec */ 877 u32 revision; 878 879 enum e1000_media_type media_type; 880 881 u16 autoneg_advertised; 882 u16 autoneg_mask; 883 u16 cable_length; 884 u16 max_cable_length; 885 u16 min_cable_length; 886 887 u8 mdix; 888 889 bool disable_polarity_correction; 890 bool is_mdix; 891 bool polarity_correction; 892 bool speed_downgraded; 893 bool autoneg_wait_to_complete; 894 }; 895 896 struct e1000_nvm_info { 897 struct e1000_nvm_operations ops; 898 enum e1000_nvm_type type; 899 enum e1000_nvm_override override; 900 901 u32 flash_bank_size; 902 u32 flash_base_addr; 903 904 u16 word_size; 905 u16 delay_usec; 906 u16 address_bits; 907 u16 opcode_bits; 908 u16 page_size; 909 }; 910 911 struct e1000_bus_info { 912 enum e1000_bus_type type; 913 enum e1000_bus_speed speed; 914 enum e1000_bus_width width; 915 916 u16 func; 917 u16 pci_cmd_word; 918 }; 919 920 struct e1000_fc_info { 921 u32 high_water; /* Flow control high-water mark */ 922 u32 low_water; /* Flow control low-water mark */ 923 u16 pause_time; /* Flow control pause timer */ 924 u16 refresh_time; /* Flow control refresh timer */ 925 bool send_xon; /* Flow control send XON */ 926 bool strict_ieee; /* Strict IEEE mode */ 927 enum e1000_fc_mode current_mode; /* FC mode in effect */ 928 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 929 }; 930 931 struct e1000_mbx_operations { 932 s32 (*init_params)(struct e1000_hw *hw); 933 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 934 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 935 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 936 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 937 s32 (*check_for_msg)(struct e1000_hw *, u16); 938 s32 (*check_for_ack)(struct e1000_hw *, u16); 939 s32 (*check_for_rst)(struct e1000_hw *, u16); 940 }; 941 942 struct e1000_mbx_stats { 943 u32 msgs_tx; 944 u32 msgs_rx; 945 946 u32 acks; 947 u32 reqs; 948 u32 rsts; 949 }; 950 951 struct e1000_mbx_info { 952 struct e1000_mbx_operations ops; 953 struct e1000_mbx_stats stats; 954 u32 timeout; 955 u32 usec_delay; 956 u16 size; 957 }; 958 959 struct e1000_dev_spec_82541 { 960 enum e1000_dsp_config dsp_config; 961 enum e1000_ffe_config ffe_config; 962 u16 spd_default; 963 bool phy_init_script; 964 }; 965 966 struct e1000_dev_spec_82542 { 967 bool dma_fairness; 968 }; 969 970 struct e1000_dev_spec_82543 { 971 u32 tbi_compatibility; 972 bool dma_fairness; 973 bool init_phy_disabled; 974 }; 975 976 struct e1000_dev_spec_82571 { 977 bool laa_is_present; 978 u32 smb_counter; 979 }; 980 981 struct e1000_dev_spec_80003es2lan { 982 bool mdic_wa_enable; 983 }; 984 985 struct e1000_shadow_ram { 986 u16 value; 987 bool modified; 988 }; 989 990 #define E1000_SHADOW_RAM_WORDS 2048 991 992 /* I218 PHY Ultra Low Power (ULP) states */ 993 enum e1000_ulp_state { 994 e1000_ulp_state_unknown, 995 e1000_ulp_state_off, 996 e1000_ulp_state_on, 997 }; 998 999 struct e1000_dev_spec_ich8lan { 1000 bool kmrn_lock_loss_workaround_enabled; 1001 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 1002 bool nvm_k1_enabled; 1003 bool disable_k1_off; 1004 bool eee_disable; 1005 u16 eee_lp_ability; 1006 enum e1000_ulp_state ulp_state; 1007 bool ulp_capability_disabled; 1008 bool during_suspend_flow; 1009 bool smbus_disable; 1010 }; 1011 1012 struct e1000_dev_spec_82575 { 1013 bool sgmii_active; 1014 bool global_device_reset; 1015 bool eee_disable; 1016 bool module_plugged; 1017 bool clear_semaphore_once; 1018 u32 mtu; 1019 struct sfp_e1000_flags eth_flags; 1020 u8 media_port; 1021 bool media_changed; 1022 }; 1023 1024 struct e1000_dev_spec_vf { 1025 u32 vf_number; 1026 u32 v2p_mailbox; 1027 }; 1028 1029 struct e1000_hw { 1030 void *back; 1031 1032 u8 *hw_addr; 1033 u8 *flash_address; 1034 unsigned long io_base; 1035 1036 struct e1000_mac_info mac; 1037 struct e1000_fc_info fc; 1038 struct e1000_phy_info phy; 1039 struct e1000_nvm_info nvm; 1040 struct e1000_bus_info bus; 1041 struct e1000_mbx_info mbx; 1042 struct e1000_host_mng_dhcp_cookie mng_cookie; 1043 1044 union { 1045 struct e1000_dev_spec_82541 _82541; 1046 struct e1000_dev_spec_82542 _82542; 1047 struct e1000_dev_spec_82543 _82543; 1048 struct e1000_dev_spec_82571 _82571; 1049 struct e1000_dev_spec_80003es2lan _80003es2lan; 1050 struct e1000_dev_spec_ich8lan ich8lan; 1051 struct e1000_dev_spec_82575 _82575; 1052 struct e1000_dev_spec_vf vf; 1053 } dev_spec; 1054 1055 u16 device_id; 1056 u16 subsystem_vendor_id; 1057 u16 subsystem_device_id; 1058 u16 vendor_id; 1059 1060 u8 revision_id; 1061 }; 1062 1063 #include "e1000_82541.h" 1064 #include "e1000_82543.h" 1065 #include "e1000_82571.h" 1066 #include "e1000_80003es2lan.h" 1067 #include "e1000_ich8lan.h" 1068 #include "e1000_82575.h" 1069 #include "e1000_i210.h" 1070 #include "e1000_base.h" 1071 1072 /* These functions must be implemented by drivers */ 1073 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1074 void e1000_pci_set_mwi(struct e1000_hw *hw); 1075 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1076 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1077 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1078 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1079 1080 #endif 1081