1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82572EI_COPPER 0x107D 90 #define E1000_DEV_ID_82572EI_FIBER 0x107E 91 #define E1000_DEV_ID_82572EI_SERDES 0x107F 92 #define E1000_DEV_ID_82572EI 0x10B9 93 #define E1000_DEV_ID_82573E 0x108B 94 #define E1000_DEV_ID_82573E_IAMT 0x108C 95 #define E1000_DEV_ID_82573L 0x109A 96 #define E1000_DEV_ID_82574L 0x10D3 97 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 98 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 101 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 102 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 103 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 104 #define E1000_DEV_ID_ICH8_IFE 0x104C 105 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 106 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 107 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 108 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 109 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 110 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 111 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 112 #define E1000_DEV_ID_ICH9_BM 0x10E5 113 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 114 #define E1000_DEV_ID_ICH9_IFE 0x10C0 115 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 116 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 117 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 118 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 119 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 120 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 121 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 122 #define E1000_DEV_ID_82576 0x10C9 123 #define E1000_DEV_ID_82576_FIBER 0x10E6 124 #define E1000_DEV_ID_82576_SERDES 0x10E7 125 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 126 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 127 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 128 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 129 130 #define E1000_REVISION_0 0 131 #define E1000_REVISION_1 1 132 #define E1000_REVISION_2 2 133 #define E1000_REVISION_3 3 134 #define E1000_REVISION_4 4 135 136 #define E1000_FUNC_0 0 137 #define E1000_FUNC_1 1 138 139 enum e1000_mac_type { 140 e1000_undefined = 0, 141 e1000_82542, 142 e1000_82543, 143 e1000_82544, 144 e1000_82540, 145 e1000_82545, 146 e1000_82545_rev_3, 147 e1000_82546, 148 e1000_82546_rev_3, 149 e1000_82541, 150 e1000_82541_rev_2, 151 e1000_82547, 152 e1000_82547_rev_2, 153 e1000_82571, 154 e1000_82572, 155 e1000_82573, 156 e1000_82574, 157 e1000_80003es2lan, 158 e1000_ich8lan, 159 e1000_ich9lan, 160 e1000_ich10lan, 161 e1000_82575, 162 e1000_82576, 163 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 164 }; 165 166 enum e1000_media_type { 167 e1000_media_type_unknown = 0, 168 e1000_media_type_copper = 1, 169 e1000_media_type_fiber = 2, 170 e1000_media_type_internal_serdes = 3, 171 e1000_num_media_types 172 }; 173 174 enum e1000_nvm_type { 175 e1000_nvm_unknown = 0, 176 e1000_nvm_none, 177 e1000_nvm_eeprom_spi, 178 e1000_nvm_eeprom_microwire, 179 e1000_nvm_flash_hw, 180 e1000_nvm_flash_sw 181 }; 182 183 enum e1000_nvm_override { 184 e1000_nvm_override_none = 0, 185 e1000_nvm_override_spi_small, 186 e1000_nvm_override_spi_large, 187 e1000_nvm_override_microwire_small, 188 e1000_nvm_override_microwire_large 189 }; 190 191 enum e1000_phy_type { 192 e1000_phy_unknown = 0, 193 e1000_phy_none, 194 e1000_phy_m88, 195 e1000_phy_igp, 196 e1000_phy_igp_2, 197 e1000_phy_gg82563, 198 e1000_phy_igp_3, 199 e1000_phy_ife, 200 e1000_phy_bm, 201 e1000_phy_vf, 202 }; 203 204 enum e1000_bus_type { 205 e1000_bus_type_unknown = 0, 206 e1000_bus_type_pci, 207 e1000_bus_type_pcix, 208 e1000_bus_type_pci_express, 209 e1000_bus_type_reserved 210 }; 211 212 enum e1000_bus_speed { 213 e1000_bus_speed_unknown = 0, 214 e1000_bus_speed_33, 215 e1000_bus_speed_66, 216 e1000_bus_speed_100, 217 e1000_bus_speed_120, 218 e1000_bus_speed_133, 219 e1000_bus_speed_2500, 220 e1000_bus_speed_5000, 221 e1000_bus_speed_reserved 222 }; 223 224 enum e1000_bus_width { 225 e1000_bus_width_unknown = 0, 226 e1000_bus_width_pcie_x1, 227 e1000_bus_width_pcie_x2, 228 e1000_bus_width_pcie_x4 = 4, 229 e1000_bus_width_pcie_x8 = 8, 230 e1000_bus_width_32, 231 e1000_bus_width_64, 232 e1000_bus_width_reserved 233 }; 234 235 enum e1000_1000t_rx_status { 236 e1000_1000t_rx_status_not_ok = 0, 237 e1000_1000t_rx_status_ok, 238 e1000_1000t_rx_status_undefined = 0xFF 239 }; 240 241 enum e1000_rev_polarity { 242 e1000_rev_polarity_normal = 0, 243 e1000_rev_polarity_reversed, 244 e1000_rev_polarity_undefined = 0xFF 245 }; 246 247 enum e1000_fc_type { 248 e1000_fc_none = 0, 249 e1000_fc_rx_pause, 250 e1000_fc_tx_pause, 251 e1000_fc_full, 252 e1000_fc_default = 0xFF 253 }; 254 255 enum e1000_ffe_config { 256 e1000_ffe_config_enabled = 0, 257 e1000_ffe_config_active, 258 e1000_ffe_config_blocked 259 }; 260 261 enum e1000_dsp_config { 262 e1000_dsp_config_disabled = 0, 263 e1000_dsp_config_enabled, 264 e1000_dsp_config_activated, 265 e1000_dsp_config_undefined = 0xFF 266 }; 267 268 /* Receive Descriptor */ 269 struct e1000_rx_desc { 270 u64 buffer_addr; /* Address of the descriptor's data buffer */ 271 u16 length; /* Length of data DMAed into data buffer */ 272 u16 csum; /* Packet checksum */ 273 u8 status; /* Descriptor status */ 274 u8 errors; /* Descriptor Errors */ 275 u16 special; 276 }; 277 278 /* Receive Descriptor - Extended */ 279 union e1000_rx_desc_extended { 280 struct { 281 u64 buffer_addr; 282 u64 reserved; 283 } read; 284 struct { 285 struct { 286 u32 mrq; /* Multiple Rx Queues */ 287 union { 288 u32 rss; /* RSS Hash */ 289 struct { 290 u16 ip_id; /* IP id */ 291 u16 csum; /* Packet Checksum */ 292 } csum_ip; 293 } hi_dword; 294 } lower; 295 struct { 296 u32 status_error; /* ext status/error */ 297 u16 length; 298 u16 vlan; /* VLAN tag */ 299 } upper; 300 } wb; /* writeback */ 301 }; 302 303 #define MAX_PS_BUFFERS 4 304 /* Receive Descriptor - Packet Split */ 305 union e1000_rx_desc_packet_split { 306 struct { 307 /* one buffer for protocol header(s), three data buffers */ 308 u64 buffer_addr[MAX_PS_BUFFERS]; 309 } read; 310 struct { 311 struct { 312 u32 mrq; /* Multiple Rx Queues */ 313 union { 314 u32 rss; /* RSS Hash */ 315 struct { 316 u16 ip_id; /* IP id */ 317 u16 csum; /* Packet Checksum */ 318 } csum_ip; 319 } hi_dword; 320 } lower; 321 struct { 322 u32 status_error; /* ext status/error */ 323 u16 length0; /* length of buffer 0 */ 324 u16 vlan; /* VLAN tag */ 325 } middle; 326 struct { 327 u16 header_status; 328 u16 length[3]; /* length of buffers 1-3 */ 329 } upper; 330 u64 reserved; 331 } wb; /* writeback */ 332 }; 333 334 /* Transmit Descriptor */ 335 struct e1000_tx_desc { 336 u64 buffer_addr; /* Address of the descriptor's data buffer */ 337 union { 338 u32 data; 339 struct { 340 u16 length; /* Data buffer length */ 341 u8 cso; /* Checksum offset */ 342 u8 cmd; /* Descriptor control */ 343 } flags; 344 } lower; 345 union { 346 u32 data; 347 struct { 348 u8 status; /* Descriptor status */ 349 u8 css; /* Checksum start */ 350 u16 special; 351 } fields; 352 } upper; 353 }; 354 355 /* Offload Context Descriptor */ 356 struct e1000_context_desc { 357 union { 358 u32 ip_config; 359 struct { 360 u8 ipcss; /* IP checksum start */ 361 u8 ipcso; /* IP checksum offset */ 362 u16 ipcse; /* IP checksum end */ 363 } ip_fields; 364 } lower_setup; 365 union { 366 u32 tcp_config; 367 struct { 368 u8 tucss; /* TCP checksum start */ 369 u8 tucso; /* TCP checksum offset */ 370 u16 tucse; /* TCP checksum end */ 371 } tcp_fields; 372 } upper_setup; 373 u32 cmd_and_length; 374 union { 375 u32 data; 376 struct { 377 u8 status; /* Descriptor status */ 378 u8 hdr_len; /* Header length */ 379 u16 mss; /* Maximum segment size */ 380 } fields; 381 } tcp_seg_setup; 382 }; 383 384 /* Offload data descriptor */ 385 struct e1000_data_desc { 386 u64 buffer_addr; /* Address of the descriptor's buffer address */ 387 union { 388 u32 data; 389 struct { 390 u16 length; /* Data buffer length */ 391 u8 typ_len_ext; 392 u8 cmd; 393 } flags; 394 } lower; 395 union { 396 u32 data; 397 struct { 398 u8 status; /* Descriptor status */ 399 u8 popts; /* Packet Options */ 400 u16 special; 401 } fields; 402 } upper; 403 }; 404 405 /* Statistics counters collected by the MAC */ 406 struct e1000_hw_stats { 407 u64 crcerrs; 408 u64 algnerrc; 409 u64 symerrs; 410 u64 rxerrc; 411 u64 mpc; 412 u64 scc; 413 u64 ecol; 414 u64 mcc; 415 u64 latecol; 416 u64 colc; 417 u64 dc; 418 u64 tncrs; 419 u64 sec; 420 u64 cexterr; 421 u64 rlec; 422 u64 xonrxc; 423 u64 xontxc; 424 u64 xoffrxc; 425 u64 xofftxc; 426 u64 fcruc; 427 u64 prc64; 428 u64 prc127; 429 u64 prc255; 430 u64 prc511; 431 u64 prc1023; 432 u64 prc1522; 433 u64 gprc; 434 u64 bprc; 435 u64 mprc; 436 u64 gptc; 437 u64 gorc; 438 u64 gotc; 439 u64 rnbc; 440 u64 ruc; 441 u64 rfc; 442 u64 roc; 443 u64 rjc; 444 u64 mgprc; 445 u64 mgpdc; 446 u64 mgptc; 447 u64 tor; 448 u64 tot; 449 u64 tpr; 450 u64 tpt; 451 u64 ptc64; 452 u64 ptc127; 453 u64 ptc255; 454 u64 ptc511; 455 u64 ptc1023; 456 u64 ptc1522; 457 u64 mptc; 458 u64 bptc; 459 u64 tsctc; 460 u64 tsctfc; 461 u64 iac; 462 u64 icrxptc; 463 u64 icrxatc; 464 u64 ictxptc; 465 u64 ictxatc; 466 u64 ictxqec; 467 u64 ictxqmtc; 468 u64 icrxdmtc; 469 u64 icrxoc; 470 u64 cbtmpc; 471 u64 htdpmc; 472 u64 cbrdpc; 473 u64 cbrmpc; 474 u64 rpthc; 475 u64 hgptc; 476 u64 htcbdpc; 477 u64 hgorc; 478 u64 hgotc; 479 u64 lenerrs; 480 u64 scvpc; 481 u64 hrmpc; 482 }; 483 484 struct e1000_phy_stats { 485 u32 idle_errors; 486 u32 receive_errors; 487 }; 488 489 struct e1000_host_mng_dhcp_cookie { 490 u32 signature; 491 u8 status; 492 u8 reserved0; 493 u16 vlan_id; 494 u32 reserved1; 495 u16 reserved2; 496 u8 reserved3; 497 u8 checksum; 498 }; 499 500 /* Host Interface "Rev 1" */ 501 struct e1000_host_command_header { 502 u8 command_id; 503 u8 command_length; 504 u8 command_options; 505 u8 checksum; 506 }; 507 508 #define E1000_HI_MAX_DATA_LENGTH 252 509 struct e1000_host_command_info { 510 struct e1000_host_command_header command_header; 511 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 512 }; 513 514 /* Host Interface "Rev 2" */ 515 struct e1000_host_mng_command_header { 516 u8 command_id; 517 u8 checksum; 518 u16 reserved1; 519 u16 reserved2; 520 u16 command_length; 521 }; 522 523 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 524 struct e1000_host_mng_command_info { 525 struct e1000_host_mng_command_header command_header; 526 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 527 }; 528 529 #include "e1000_mac.h" 530 #include "e1000_phy.h" 531 #include "e1000_nvm.h" 532 #include "e1000_manage.h" 533 534 struct e1000_mac_operations { 535 /* Function pointers for the MAC. */ 536 s32 (*init_params)(struct e1000_hw *); 537 s32 (*blink_led)(struct e1000_hw *); 538 s32 (*check_for_link)(struct e1000_hw *); 539 bool (*check_mng_mode)(struct e1000_hw *hw); 540 s32 (*cleanup_led)(struct e1000_hw *); 541 void (*clear_hw_cntrs)(struct e1000_hw *); 542 void (*clear_vfta)(struct e1000_hw *); 543 s32 (*get_bus_info)(struct e1000_hw *); 544 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 545 s32 (*led_on)(struct e1000_hw *); 546 s32 (*led_off)(struct e1000_hw *); 547 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, 548 u32); 549 void (*remove_device)(struct e1000_hw *); 550 s32 (*reset_hw)(struct e1000_hw *); 551 s32 (*init_hw)(struct e1000_hw *); 552 void (*shutdown_serdes)(struct e1000_hw *); 553 s32 (*setup_link)(struct e1000_hw *); 554 s32 (*setup_physical_interface)(struct e1000_hw *); 555 s32 (*setup_led)(struct e1000_hw *); 556 void (*write_vfta)(struct e1000_hw *, u32, u32); 557 void (*mta_set)(struct e1000_hw *, u32); 558 void (*config_collision_dist)(struct e1000_hw*); 559 void (*rar_set)(struct e1000_hw*, u8*, u32); 560 s32 (*read_mac_addr)(struct e1000_hw*); 561 s32 (*validate_mdi_setting)(struct e1000_hw*); 562 s32 (*mng_host_if_write)(struct e1000_hw*, u8*, u16, u16, u8*); 563 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 564 struct e1000_host_mng_command_header*); 565 s32 (*mng_enable_host_if)(struct e1000_hw*); 566 s32 (*wait_autoneg)(struct e1000_hw*); 567 }; 568 569 struct e1000_phy_operations { 570 s32 (*init_params)(struct e1000_hw *); 571 s32 (*acquire)(struct e1000_hw *); 572 s32 (*check_polarity)(struct e1000_hw *); 573 s32 (*check_reset_block)(struct e1000_hw *); 574 s32 (*commit)(struct e1000_hw *); 575 s32 (*force_speed_duplex)(struct e1000_hw *); 576 s32 (*get_cfg_done)(struct e1000_hw *hw); 577 s32 (*get_cable_length)(struct e1000_hw *); 578 s32 (*get_info)(struct e1000_hw *); 579 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 580 void (*release)(struct e1000_hw *); 581 s32 (*reset)(struct e1000_hw *); 582 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 583 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 584 s32 (*write_reg)(struct e1000_hw *, u32, u16); 585 void (*power_up)(struct e1000_hw *); 586 void (*power_down)(struct e1000_hw *); 587 }; 588 589 struct e1000_nvm_operations { 590 s32 (*init_params)(struct e1000_hw *); 591 s32 (*acquire)(struct e1000_hw *); 592 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 593 void (*release)(struct e1000_hw *); 594 void (*reload)(struct e1000_hw *); 595 s32 (*update)(struct e1000_hw *); 596 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 597 s32 (*validate)(struct e1000_hw *); 598 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 599 }; 600 601 struct e1000_mac_info { 602 struct e1000_mac_operations ops; 603 u8 addr[6]; 604 u8 perm_addr[6]; 605 606 enum e1000_mac_type type; 607 608 u32 collision_delta; 609 u32 ledctl_default; 610 u32 ledctl_mode1; 611 u32 ledctl_mode2; 612 u32 mc_filter_type; 613 u32 tx_packet_delta; 614 u32 txcw; 615 616 u16 current_ifs_val; 617 u16 ifs_max_val; 618 u16 ifs_min_val; 619 u16 ifs_ratio; 620 u16 ifs_step_size; 621 u16 mta_reg_count; 622 u16 rar_entry_count; 623 624 u8 forced_speed_duplex; 625 626 bool adaptive_ifs; 627 bool arc_subsystem_valid; 628 bool asf_firmware_present; 629 bool autoneg; 630 bool autoneg_failed; 631 bool disable_av; 632 bool disable_hw_init_bits; 633 bool get_link_status; 634 bool ifs_params_forced; 635 bool in_ifs_mode; 636 bool report_tx_early; 637 bool serdes_has_link; 638 bool tx_pkt_filtering; 639 }; 640 641 struct e1000_phy_info { 642 struct e1000_phy_operations ops; 643 enum e1000_phy_type type; 644 645 enum e1000_1000t_rx_status local_rx; 646 enum e1000_1000t_rx_status remote_rx; 647 enum e1000_ms_type ms_type; 648 enum e1000_ms_type original_ms_type; 649 enum e1000_rev_polarity cable_polarity; 650 enum e1000_smart_speed smart_speed; 651 652 u32 addr; 653 u32 id; 654 u32 reset_delay_us; /* in usec */ 655 u32 revision; 656 657 enum e1000_media_type media_type; 658 659 u16 autoneg_advertised; 660 u16 autoneg_mask; 661 u16 cable_length; 662 u16 max_cable_length; 663 u16 min_cable_length; 664 665 u8 mdix; 666 667 bool disable_polarity_correction; 668 bool is_mdix; 669 bool polarity_correction; 670 bool reset_disable; 671 bool speed_downgraded; 672 bool autoneg_wait_to_complete; 673 }; 674 675 struct e1000_nvm_info { 676 struct e1000_nvm_operations ops; 677 enum e1000_nvm_type type; 678 enum e1000_nvm_override override; 679 680 u32 flash_bank_size; 681 u32 flash_base_addr; 682 u32 semaphore_delay; 683 684 u16 word_size; 685 u16 delay_usec; 686 u16 address_bits; 687 u16 opcode_bits; 688 u16 page_size; 689 }; 690 691 struct e1000_bus_info { 692 enum e1000_bus_type type; 693 enum e1000_bus_speed speed; 694 enum e1000_bus_width width; 695 696 u32 snoop; 697 698 u16 func; 699 u16 pci_cmd_word; 700 }; 701 702 struct e1000_fc_info { 703 u32 high_water; /* Flow control high-water mark */ 704 u32 low_water; /* Flow control low-water mark */ 705 u16 pause_time; /* Flow control pause timer */ 706 bool send_xon; /* Flow control send XON */ 707 bool strict_ieee; /* Strict IEEE mode */ 708 enum e1000_fc_type type; /* Type of flow control */ 709 enum e1000_fc_type original_type; 710 }; 711 712 struct e1000_hw { 713 void *back; 714 void *dev_spec; 715 716 u8 *hw_addr; 717 u8 *flash_address; 718 unsigned long io_base; 719 720 struct e1000_mac_info mac; 721 struct e1000_fc_info fc; 722 struct e1000_phy_info phy; 723 struct e1000_nvm_info nvm; 724 struct e1000_bus_info bus; 725 struct e1000_host_mng_dhcp_cookie mng_cookie; 726 727 u32 dev_spec_size; 728 729 u16 device_id; 730 u16 subsystem_vendor_id; 731 u16 subsystem_device_id; 732 u16 vendor_id; 733 734 u8 revision_id; 735 }; 736 737 #include "e1000_82541.h" 738 #include "e1000_82543.h" 739 #include "e1000_82571.h" 740 #include "e1000_80003es2lan.h" 741 #include "e1000_ich8lan.h" 742 #include "e1000_82575.h" 743 744 /* These functions must be implemented by drivers */ 745 void e1000_pci_clear_mwi(struct e1000_hw *hw); 746 void e1000_pci_set_mwi(struct e1000_hw *hw); 747 s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size); 748 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 749 void e1000_free_dev_spec_struct(struct e1000_hw *hw); 750 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 751 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 752 753 #endif 754