1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82572EI_COPPER 0x107D 90 #define E1000_DEV_ID_82572EI_FIBER 0x107E 91 #define E1000_DEV_ID_82572EI_SERDES 0x107F 92 #define E1000_DEV_ID_82572EI 0x10B9 93 #define E1000_DEV_ID_82573E 0x108B 94 #define E1000_DEV_ID_82573E_IAMT 0x108C 95 #define E1000_DEV_ID_82573L 0x109A 96 #define E1000_DEV_ID_82574L 0x10D3 97 #define E1000_DEV_ID_82574LA 0x10F6 98 #define E1000_DEV_ID_82583V 0x150C 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 107 #define E1000_DEV_ID_ICH8_IFE 0x104C 108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115 #define E1000_DEV_ID_ICH9_BM 0x10E5 116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 117 #define E1000_DEV_ID_ICH9_IFE 0x10C0 118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123 #define E1000_DEV_ID_ICH10_HANKSVILLE 0xF0FE 124 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127 128 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 129 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 130 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 131 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 132 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 133 #define E1000_DEV_ID_PCH2_LV_V 0x1503 134 #define E1000_DEV_ID_82576 0x10C9 135 #define E1000_DEV_ID_82576_FIBER 0x10E6 136 #define E1000_DEV_ID_82576_SERDES 0x10E7 137 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 138 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 139 #define E1000_DEV_ID_82576_NS 0x150A 140 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 141 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 142 #define E1000_DEV_ID_82576_VF 0x10CA 143 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 144 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 145 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 146 #define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2 147 #define E1000_DEV_ID_82580_COPPER 0x150E 148 #define E1000_DEV_ID_82580_FIBER 0x150F 149 #define E1000_DEV_ID_82580_SERDES 0x1510 150 #define E1000_DEV_ID_82580_SGMII 0x1511 151 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 152 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 153 #define E1000_REVISION_0 0 154 #define E1000_REVISION_1 1 155 #define E1000_REVISION_2 2 156 #define E1000_REVISION_3 3 157 #define E1000_REVISION_4 4 158 159 #define E1000_FUNC_0 0 160 #define E1000_FUNC_1 1 161 #define E1000_FUNC_2 2 162 #define E1000_FUNC_3 3 163 164 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 165 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 166 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 167 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 168 169 enum e1000_mac_type { 170 e1000_undefined = 0, 171 e1000_82542, 172 e1000_82543, 173 e1000_82544, 174 e1000_82540, 175 e1000_82545, 176 e1000_82545_rev_3, 177 e1000_82546, 178 e1000_82546_rev_3, 179 e1000_82541, 180 e1000_82541_rev_2, 181 e1000_82547, 182 e1000_82547_rev_2, 183 e1000_82571, 184 e1000_82572, 185 e1000_82573, 186 e1000_82574, 187 e1000_82583, 188 e1000_80003es2lan, 189 e1000_ich8lan, 190 e1000_ich9lan, 191 e1000_ich10lan, 192 e1000_pchlan, 193 e1000_pch2lan, 194 e1000_82575, 195 e1000_82576, 196 e1000_82580, 197 e1000_vfadapt, 198 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 199 }; 200 201 enum e1000_media_type { 202 e1000_media_type_unknown = 0, 203 e1000_media_type_copper = 1, 204 e1000_media_type_fiber = 2, 205 e1000_media_type_internal_serdes = 3, 206 e1000_num_media_types 207 }; 208 209 enum e1000_nvm_type { 210 e1000_nvm_unknown = 0, 211 e1000_nvm_none, 212 e1000_nvm_eeprom_spi, 213 e1000_nvm_eeprom_microwire, 214 e1000_nvm_flash_hw, 215 e1000_nvm_flash_sw 216 }; 217 218 enum e1000_nvm_override { 219 e1000_nvm_override_none = 0, 220 e1000_nvm_override_spi_small, 221 e1000_nvm_override_spi_large, 222 e1000_nvm_override_microwire_small, 223 e1000_nvm_override_microwire_large 224 }; 225 226 enum e1000_phy_type { 227 e1000_phy_unknown = 0, 228 e1000_phy_none, 229 e1000_phy_m88, 230 e1000_phy_igp, 231 e1000_phy_igp_2, 232 e1000_phy_gg82563, 233 e1000_phy_igp_3, 234 e1000_phy_ife, 235 e1000_phy_bm, 236 e1000_phy_82578, 237 e1000_phy_82577, 238 e1000_phy_82579, 239 e1000_phy_82580, 240 e1000_phy_vf, 241 }; 242 243 enum e1000_bus_type { 244 e1000_bus_type_unknown = 0, 245 e1000_bus_type_pci, 246 e1000_bus_type_pcix, 247 e1000_bus_type_pci_express, 248 e1000_bus_type_reserved 249 }; 250 251 enum e1000_bus_speed { 252 e1000_bus_speed_unknown = 0, 253 e1000_bus_speed_33, 254 e1000_bus_speed_66, 255 e1000_bus_speed_100, 256 e1000_bus_speed_120, 257 e1000_bus_speed_133, 258 e1000_bus_speed_2500, 259 e1000_bus_speed_5000, 260 e1000_bus_speed_reserved 261 }; 262 263 enum e1000_bus_width { 264 e1000_bus_width_unknown = 0, 265 e1000_bus_width_pcie_x1, 266 e1000_bus_width_pcie_x2, 267 e1000_bus_width_pcie_x4 = 4, 268 e1000_bus_width_pcie_x8 = 8, 269 e1000_bus_width_32, 270 e1000_bus_width_64, 271 e1000_bus_width_reserved 272 }; 273 274 enum e1000_1000t_rx_status { 275 e1000_1000t_rx_status_not_ok = 0, 276 e1000_1000t_rx_status_ok, 277 e1000_1000t_rx_status_undefined = 0xFF 278 }; 279 280 enum e1000_rev_polarity { 281 e1000_rev_polarity_normal = 0, 282 e1000_rev_polarity_reversed, 283 e1000_rev_polarity_undefined = 0xFF 284 }; 285 286 enum e1000_fc_mode { 287 e1000_fc_none = 0, 288 e1000_fc_rx_pause, 289 e1000_fc_tx_pause, 290 e1000_fc_full, 291 e1000_fc_default = 0xFF 292 }; 293 294 enum e1000_ffe_config { 295 e1000_ffe_config_enabled = 0, 296 e1000_ffe_config_active, 297 e1000_ffe_config_blocked 298 }; 299 300 enum e1000_dsp_config { 301 e1000_dsp_config_disabled = 0, 302 e1000_dsp_config_enabled, 303 e1000_dsp_config_activated, 304 e1000_dsp_config_undefined = 0xFF 305 }; 306 307 enum e1000_ms_type { 308 e1000_ms_hw_default = 0, 309 e1000_ms_force_master, 310 e1000_ms_force_slave, 311 e1000_ms_auto 312 }; 313 314 enum e1000_smart_speed { 315 e1000_smart_speed_default = 0, 316 e1000_smart_speed_on, 317 e1000_smart_speed_off 318 }; 319 320 enum e1000_serdes_link_state { 321 e1000_serdes_link_down = 0, 322 e1000_serdes_link_autoneg_progress, 323 e1000_serdes_link_autoneg_complete, 324 e1000_serdes_link_forced_up 325 }; 326 327 #define __le16 u16 328 #define __le32 u32 329 #define __le64 u64 330 /* Receive Descriptor */ 331 struct e1000_rx_desc { 332 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 333 __le16 length; /* Length of data DMAed into data buffer */ 334 __le16 csum; /* Packet checksum */ 335 u8 status; /* Descriptor status */ 336 u8 errors; /* Descriptor Errors */ 337 __le16 special; 338 }; 339 340 /* Receive Descriptor - Extended */ 341 union e1000_rx_desc_extended { 342 struct { 343 __le64 buffer_addr; 344 __le64 reserved; 345 } read; 346 struct { 347 struct { 348 __le32 mrq; /* Multiple Rx Queues */ 349 union { 350 __le32 rss; /* RSS Hash */ 351 struct { 352 __le16 ip_id; /* IP id */ 353 __le16 csum; /* Packet Checksum */ 354 } csum_ip; 355 } hi_dword; 356 } lower; 357 struct { 358 __le32 status_error; /* ext status/error */ 359 __le16 length; 360 __le16 vlan; /* VLAN tag */ 361 } upper; 362 } wb; /* writeback */ 363 }; 364 365 #define MAX_PS_BUFFERS 4 366 /* Receive Descriptor - Packet Split */ 367 union e1000_rx_desc_packet_split { 368 struct { 369 /* one buffer for protocol header(s), three data buffers */ 370 __le64 buffer_addr[MAX_PS_BUFFERS]; 371 } read; 372 struct { 373 struct { 374 __le32 mrq; /* Multiple Rx Queues */ 375 union { 376 __le32 rss; /* RSS Hash */ 377 struct { 378 __le16 ip_id; /* IP id */ 379 __le16 csum; /* Packet Checksum */ 380 } csum_ip; 381 } hi_dword; 382 } lower; 383 struct { 384 __le32 status_error; /* ext status/error */ 385 __le16 length0; /* length of buffer 0 */ 386 __le16 vlan; /* VLAN tag */ 387 } middle; 388 struct { 389 __le16 header_status; 390 __le16 length[3]; /* length of buffers 1-3 */ 391 } upper; 392 __le64 reserved; 393 } wb; /* writeback */ 394 }; 395 396 /* Transmit Descriptor */ 397 struct e1000_tx_desc { 398 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 399 union { 400 __le32 data; 401 struct { 402 __le16 length; /* Data buffer length */ 403 u8 cso; /* Checksum offset */ 404 u8 cmd; /* Descriptor control */ 405 } flags; 406 } lower; 407 union { 408 __le32 data; 409 struct { 410 u8 status; /* Descriptor status */ 411 u8 css; /* Checksum start */ 412 __le16 special; 413 } fields; 414 } upper; 415 }; 416 417 /* Offload Context Descriptor */ 418 struct e1000_context_desc { 419 union { 420 __le32 ip_config; 421 struct { 422 u8 ipcss; /* IP checksum start */ 423 u8 ipcso; /* IP checksum offset */ 424 __le16 ipcse; /* IP checksum end */ 425 } ip_fields; 426 } lower_setup; 427 union { 428 __le32 tcp_config; 429 struct { 430 u8 tucss; /* TCP checksum start */ 431 u8 tucso; /* TCP checksum offset */ 432 __le16 tucse; /* TCP checksum end */ 433 } tcp_fields; 434 } upper_setup; 435 __le32 cmd_and_length; 436 union { 437 __le32 data; 438 struct { 439 u8 status; /* Descriptor status */ 440 u8 hdr_len; /* Header length */ 441 __le16 mss; /* Maximum segment size */ 442 } fields; 443 } tcp_seg_setup; 444 }; 445 446 /* Offload data descriptor */ 447 struct e1000_data_desc { 448 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 449 union { 450 __le32 data; 451 struct { 452 __le16 length; /* Data buffer length */ 453 u8 typ_len_ext; 454 u8 cmd; 455 } flags; 456 } lower; 457 union { 458 __le32 data; 459 struct { 460 u8 status; /* Descriptor status */ 461 u8 popts; /* Packet Options */ 462 __le16 special; 463 } fields; 464 } upper; 465 }; 466 467 /* Statistics counters collected by the MAC */ 468 struct e1000_hw_stats { 469 u64 crcerrs; 470 u64 algnerrc; 471 u64 symerrs; 472 u64 rxerrc; 473 u64 mpc; 474 u64 scc; 475 u64 ecol; 476 u64 mcc; 477 u64 latecol; 478 u64 colc; 479 u64 dc; 480 u64 tncrs; 481 u64 sec; 482 u64 cexterr; 483 u64 rlec; 484 u64 xonrxc; 485 u64 xontxc; 486 u64 xoffrxc; 487 u64 xofftxc; 488 u64 fcruc; 489 u64 prc64; 490 u64 prc127; 491 u64 prc255; 492 u64 prc511; 493 u64 prc1023; 494 u64 prc1522; 495 u64 gprc; 496 u64 bprc; 497 u64 mprc; 498 u64 gptc; 499 u64 gorc; 500 u64 gotc; 501 u64 rnbc; 502 u64 ruc; 503 u64 rfc; 504 u64 roc; 505 u64 rjc; 506 u64 mgprc; 507 u64 mgpdc; 508 u64 mgptc; 509 u64 tor; 510 u64 tot; 511 u64 tpr; 512 u64 tpt; 513 u64 ptc64; 514 u64 ptc127; 515 u64 ptc255; 516 u64 ptc511; 517 u64 ptc1023; 518 u64 ptc1522; 519 u64 mptc; 520 u64 bptc; 521 u64 tsctc; 522 u64 tsctfc; 523 u64 iac; 524 u64 icrxptc; 525 u64 icrxatc; 526 u64 ictxptc; 527 u64 ictxatc; 528 u64 ictxqec; 529 u64 ictxqmtc; 530 u64 icrxdmtc; 531 u64 icrxoc; 532 u64 cbtmpc; 533 u64 htdpmc; 534 u64 cbrdpc; 535 u64 cbrmpc; 536 u64 rpthc; 537 u64 hgptc; 538 u64 htcbdpc; 539 u64 hgorc; 540 u64 hgotc; 541 u64 lenerrs; 542 u64 scvpc; 543 u64 hrmpc; 544 u64 doosync; 545 }; 546 547 struct e1000_vf_stats { 548 u64 base_gprc; 549 u64 base_gptc; 550 u64 base_gorc; 551 u64 base_gotc; 552 u64 base_mprc; 553 u64 base_gotlbc; 554 u64 base_gptlbc; 555 u64 base_gorlbc; 556 u64 base_gprlbc; 557 558 u32 last_gprc; 559 u32 last_gptc; 560 u32 last_gorc; 561 u32 last_gotc; 562 u32 last_mprc; 563 u32 last_gotlbc; 564 u32 last_gptlbc; 565 u32 last_gorlbc; 566 u32 last_gprlbc; 567 568 u64 gprc; 569 u64 gptc; 570 u64 gorc; 571 u64 gotc; 572 u64 mprc; 573 u64 gotlbc; 574 u64 gptlbc; 575 u64 gorlbc; 576 u64 gprlbc; 577 }; 578 579 struct e1000_phy_stats { 580 u32 idle_errors; 581 u32 receive_errors; 582 }; 583 584 struct e1000_host_mng_dhcp_cookie { 585 u32 signature; 586 u8 status; 587 u8 reserved0; 588 u16 vlan_id; 589 u32 reserved1; 590 u16 reserved2; 591 u8 reserved3; 592 u8 checksum; 593 }; 594 595 /* Host Interface "Rev 1" */ 596 struct e1000_host_command_header { 597 u8 command_id; 598 u8 command_length; 599 u8 command_options; 600 u8 checksum; 601 }; 602 603 #define E1000_HI_MAX_DATA_LENGTH 252 604 struct e1000_host_command_info { 605 struct e1000_host_command_header command_header; 606 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 607 }; 608 609 /* Host Interface "Rev 2" */ 610 struct e1000_host_mng_command_header { 611 u8 command_id; 612 u8 checksum; 613 u16 reserved1; 614 u16 reserved2; 615 u16 command_length; 616 }; 617 618 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 619 struct e1000_host_mng_command_info { 620 struct e1000_host_mng_command_header command_header; 621 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 622 }; 623 624 #include "e1000_mac.h" 625 #include "e1000_phy.h" 626 #include "e1000_nvm.h" 627 #include "e1000_manage.h" 628 #include "e1000_mbx.h" 629 630 struct e1000_mac_operations { 631 /* Function pointers for the MAC. */ 632 s32 (*init_params)(struct e1000_hw *); 633 s32 (*id_led_init)(struct e1000_hw *); 634 s32 (*blink_led)(struct e1000_hw *); 635 s32 (*check_for_link)(struct e1000_hw *); 636 bool (*check_mng_mode)(struct e1000_hw *hw); 637 s32 (*cleanup_led)(struct e1000_hw *); 638 void (*clear_hw_cntrs)(struct e1000_hw *); 639 void (*clear_vfta)(struct e1000_hw *); 640 s32 (*get_bus_info)(struct e1000_hw *); 641 void (*set_lan_id)(struct e1000_hw *); 642 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 643 s32 (*led_on)(struct e1000_hw *); 644 s32 (*led_off)(struct e1000_hw *); 645 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 646 s32 (*reset_hw)(struct e1000_hw *); 647 s32 (*init_hw)(struct e1000_hw *); 648 void (*shutdown_serdes)(struct e1000_hw *); 649 void (*power_up_serdes)(struct e1000_hw *); 650 s32 (*setup_link)(struct e1000_hw *); 651 s32 (*setup_physical_interface)(struct e1000_hw *); 652 s32 (*setup_led)(struct e1000_hw *); 653 void (*write_vfta)(struct e1000_hw *, u32, u32); 654 void (*config_collision_dist)(struct e1000_hw *); 655 void (*rar_set)(struct e1000_hw *, u8*, u32); 656 s32 (*read_mac_addr)(struct e1000_hw *); 657 s32 (*validate_mdi_setting)(struct e1000_hw *); 658 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); 659 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 660 struct e1000_host_mng_command_header*); 661 s32 (*mng_enable_host_if)(struct e1000_hw *); 662 s32 (*wait_autoneg)(struct e1000_hw *); 663 }; 664 665 struct e1000_phy_operations { 666 s32 (*init_params)(struct e1000_hw *); 667 s32 (*acquire)(struct e1000_hw *); 668 s32 (*cfg_on_link_up)(struct e1000_hw *); 669 s32 (*check_polarity)(struct e1000_hw *); 670 s32 (*check_reset_block)(struct e1000_hw *); 671 s32 (*commit)(struct e1000_hw *); 672 s32 (*force_speed_duplex)(struct e1000_hw *); 673 s32 (*get_cfg_done)(struct e1000_hw *hw); 674 s32 (*get_cable_length)(struct e1000_hw *); 675 s32 (*get_info)(struct e1000_hw *); 676 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 677 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 678 void (*release)(struct e1000_hw *); 679 s32 (*reset)(struct e1000_hw *); 680 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 681 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 682 s32 (*write_reg)(struct e1000_hw *, u32, u16); 683 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 684 void (*power_up)(struct e1000_hw *); 685 void (*power_down)(struct e1000_hw *); 686 }; 687 688 struct e1000_nvm_operations { 689 s32 (*init_params)(struct e1000_hw *); 690 s32 (*acquire)(struct e1000_hw *); 691 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 692 void (*release)(struct e1000_hw *); 693 void (*reload)(struct e1000_hw *); 694 s32 (*update)(struct e1000_hw *); 695 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 696 s32 (*validate)(struct e1000_hw *); 697 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 698 }; 699 700 struct e1000_mac_info { 701 struct e1000_mac_operations ops; 702 u8 addr[6]; 703 u8 perm_addr[6]; 704 705 enum e1000_mac_type type; 706 707 u32 collision_delta; 708 u32 ledctl_default; 709 u32 ledctl_mode1; 710 u32 ledctl_mode2; 711 u32 mc_filter_type; 712 u32 tx_packet_delta; 713 u32 txcw; 714 715 u16 current_ifs_val; 716 u16 ifs_max_val; 717 u16 ifs_min_val; 718 u16 ifs_ratio; 719 u16 ifs_step_size; 720 u16 mta_reg_count; 721 u16 uta_reg_count; 722 723 /* Maximum size of the MTA register table in all supported adapters */ 724 #define MAX_MTA_REG 128 725 u32 mta_shadow[MAX_MTA_REG]; 726 u16 rar_entry_count; 727 728 u8 forced_speed_duplex; 729 730 bool adaptive_ifs; 731 bool has_fwsm; 732 bool arc_subsystem_valid; 733 bool asf_firmware_present; 734 bool autoneg; 735 bool autoneg_failed; 736 bool get_link_status; 737 bool in_ifs_mode; 738 bool report_tx_early; 739 enum e1000_serdes_link_state serdes_link_state; 740 bool serdes_has_link; 741 bool tx_pkt_filtering; 742 }; 743 744 struct e1000_phy_info { 745 struct e1000_phy_operations ops; 746 enum e1000_phy_type type; 747 748 enum e1000_1000t_rx_status local_rx; 749 enum e1000_1000t_rx_status remote_rx; 750 enum e1000_ms_type ms_type; 751 enum e1000_ms_type original_ms_type; 752 enum e1000_rev_polarity cable_polarity; 753 enum e1000_smart_speed smart_speed; 754 755 u32 addr; 756 u32 id; 757 u32 reset_delay_us; /* in usec */ 758 u32 revision; 759 760 enum e1000_media_type media_type; 761 762 u16 autoneg_advertised; 763 u16 autoneg_mask; 764 u16 cable_length; 765 u16 max_cable_length; 766 u16 min_cable_length; 767 768 u8 mdix; 769 770 bool disable_polarity_correction; 771 bool is_mdix; 772 bool polarity_correction; 773 bool reset_disable; 774 bool speed_downgraded; 775 bool autoneg_wait_to_complete; 776 }; 777 778 struct e1000_nvm_info { 779 struct e1000_nvm_operations ops; 780 enum e1000_nvm_type type; 781 enum e1000_nvm_override override; 782 783 u32 flash_bank_size; 784 u32 flash_base_addr; 785 786 u16 word_size; 787 u16 delay_usec; 788 u16 address_bits; 789 u16 opcode_bits; 790 u16 page_size; 791 }; 792 793 struct e1000_bus_info { 794 enum e1000_bus_type type; 795 enum e1000_bus_speed speed; 796 enum e1000_bus_width width; 797 798 u16 func; 799 u16 pci_cmd_word; 800 }; 801 802 struct e1000_fc_info { 803 u32 high_water; /* Flow control high-water mark */ 804 u32 low_water; /* Flow control low-water mark */ 805 u16 pause_time; /* Flow control pause timer */ 806 u16 refresh_time; /* Flow control refresh timer */ 807 bool send_xon; /* Flow control send XON */ 808 bool strict_ieee; /* Strict IEEE mode */ 809 enum e1000_fc_mode current_mode; /* FC mode in effect */ 810 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 811 }; 812 813 struct e1000_mbx_operations { 814 s32 (*init_params)(struct e1000_hw *hw); 815 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 816 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 817 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 818 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 819 s32 (*check_for_msg)(struct e1000_hw *, u16); 820 s32 (*check_for_ack)(struct e1000_hw *, u16); 821 s32 (*check_for_rst)(struct e1000_hw *, u16); 822 }; 823 824 struct e1000_mbx_stats { 825 u32 msgs_tx; 826 u32 msgs_rx; 827 828 u32 acks; 829 u32 reqs; 830 u32 rsts; 831 }; 832 833 struct e1000_mbx_info { 834 struct e1000_mbx_operations ops; 835 struct e1000_mbx_stats stats; 836 u32 timeout; 837 u32 usec_delay; 838 u16 size; 839 }; 840 841 struct e1000_dev_spec_82541 { 842 enum e1000_dsp_config dsp_config; 843 enum e1000_ffe_config ffe_config; 844 u16 spd_default; 845 bool phy_init_script; 846 }; 847 848 struct e1000_dev_spec_82542 { 849 bool dma_fairness; 850 }; 851 852 struct e1000_dev_spec_82543 { 853 u32 tbi_compatibility; 854 bool dma_fairness; 855 bool init_phy_disabled; 856 }; 857 858 struct e1000_dev_spec_82571 { 859 bool laa_is_present; 860 u32 smb_counter; 861 E1000_MUTEX swflag_mutex; 862 }; 863 864 struct e1000_dev_spec_80003es2lan { 865 bool mdic_wa_enable; 866 }; 867 868 struct e1000_shadow_ram { 869 u16 value; 870 bool modified; 871 }; 872 873 #define E1000_SHADOW_RAM_WORDS 2048 874 875 struct e1000_dev_spec_ich8lan { 876 bool kmrn_lock_loss_workaround_enabled; 877 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 878 E1000_MUTEX nvm_mutex; 879 E1000_MUTEX swflag_mutex; 880 bool nvm_k1_enabled; 881 bool eee_disable; 882 }; 883 884 struct e1000_dev_spec_82575 { 885 bool sgmii_active; 886 bool global_device_reset; 887 }; 888 889 struct e1000_dev_spec_vf { 890 u32 vf_number; 891 u32 v2p_mailbox; 892 }; 893 894 struct e1000_hw { 895 void *back; 896 897 u8 *hw_addr; 898 u8 *flash_address; 899 unsigned long io_base; 900 901 struct e1000_mac_info mac; 902 struct e1000_fc_info fc; 903 struct e1000_phy_info phy; 904 struct e1000_nvm_info nvm; 905 struct e1000_bus_info bus; 906 struct e1000_mbx_info mbx; 907 struct e1000_host_mng_dhcp_cookie mng_cookie; 908 909 union { 910 struct e1000_dev_spec_82541 _82541; 911 struct e1000_dev_spec_82542 _82542; 912 struct e1000_dev_spec_82543 _82543; 913 struct e1000_dev_spec_82571 _82571; 914 struct e1000_dev_spec_80003es2lan _80003es2lan; 915 struct e1000_dev_spec_ich8lan ich8lan; 916 struct e1000_dev_spec_82575 _82575; 917 struct e1000_dev_spec_vf vf; 918 } dev_spec; 919 920 u16 device_id; 921 u16 subsystem_vendor_id; 922 u16 subsystem_device_id; 923 u16 vendor_id; 924 925 u8 revision_id; 926 }; 927 928 #include "e1000_82541.h" 929 #include "e1000_82543.h" 930 #include "e1000_82571.h" 931 #include "e1000_80003es2lan.h" 932 #include "e1000_ich8lan.h" 933 #include "e1000_82575.h" 934 935 /* These functions must be implemented by drivers */ 936 void e1000_pci_clear_mwi(struct e1000_hw *hw); 937 void e1000_pci_set_mwi(struct e1000_hw *hw); 938 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 939 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 940 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 941 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 942 943 #endif 944