1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82572EI_COPPER 0x107D 90 #define E1000_DEV_ID_82572EI_FIBER 0x107E 91 #define E1000_DEV_ID_82572EI_SERDES 0x107F 92 #define E1000_DEV_ID_82572EI 0x10B9 93 #define E1000_DEV_ID_82573E 0x108B 94 #define E1000_DEV_ID_82573E_IAMT 0x108C 95 #define E1000_DEV_ID_82573L 0x109A 96 #define E1000_DEV_ID_82574L 0x10D3 97 #define E1000_DEV_ID_82574LA 0x10F6 98 #define E1000_DEV_ID_82583V 0x150C 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 107 #define E1000_DEV_ID_ICH8_IFE 0x104C 108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115 #define E1000_DEV_ID_ICH9_BM 0x10E5 116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 117 #define E1000_DEV_ID_ICH9_IFE 0x10C0 118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 125 126 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 127 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 128 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 129 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 130 #define E1000_DEV_ID_82576 0x10C9 131 #define E1000_DEV_ID_82576_FIBER 0x10E6 132 #define E1000_DEV_ID_82576_SERDES 0x10E7 133 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 134 #define E1000_DEV_ID_82576_NS 0x150A 135 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 136 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 137 #define E1000_DEV_ID_82576_VF 0x10CA 138 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 139 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 140 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 141 #define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2 142 #define E1000_DEV_ID_82580_COPPER 0x150E 143 #define E1000_DEV_ID_82580_FIBER 0x150F 144 #define E1000_DEV_ID_82580_SERDES 0x1510 145 #define E1000_DEV_ID_82580_SGMII 0x1511 146 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 147 #define E1000_REVISION_0 0 148 #define E1000_REVISION_1 1 149 #define E1000_REVISION_2 2 150 #define E1000_REVISION_3 3 151 #define E1000_REVISION_4 4 152 153 #define E1000_FUNC_0 0 154 #define E1000_FUNC_1 1 155 #define E1000_FUNC_2 2 156 #define E1000_FUNC_3 3 157 158 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 159 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 160 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 161 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 162 163 enum e1000_mac_type { 164 e1000_undefined = 0, 165 e1000_82542, 166 e1000_82543, 167 e1000_82544, 168 e1000_82540, 169 e1000_82545, 170 e1000_82545_rev_3, 171 e1000_82546, 172 e1000_82546_rev_3, 173 e1000_82541, 174 e1000_82541_rev_2, 175 e1000_82547, 176 e1000_82547_rev_2, 177 e1000_82571, 178 e1000_82572, 179 e1000_82573, 180 e1000_82574, 181 e1000_82583, 182 e1000_80003es2lan, 183 e1000_ich8lan, 184 e1000_ich9lan, 185 e1000_ich10lan, 186 e1000_pchlan, 187 e1000_82575, 188 e1000_82576, 189 e1000_82580, 190 e1000_vfadapt, 191 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 192 }; 193 194 enum e1000_media_type { 195 e1000_media_type_unknown = 0, 196 e1000_media_type_copper = 1, 197 e1000_media_type_fiber = 2, 198 e1000_media_type_internal_serdes = 3, 199 e1000_num_media_types 200 }; 201 202 enum e1000_nvm_type { 203 e1000_nvm_unknown = 0, 204 e1000_nvm_none, 205 e1000_nvm_eeprom_spi, 206 e1000_nvm_eeprom_microwire, 207 e1000_nvm_flash_hw, 208 e1000_nvm_flash_sw 209 }; 210 211 enum e1000_nvm_override { 212 e1000_nvm_override_none = 0, 213 e1000_nvm_override_spi_small, 214 e1000_nvm_override_spi_large, 215 e1000_nvm_override_microwire_small, 216 e1000_nvm_override_microwire_large 217 }; 218 219 enum e1000_phy_type { 220 e1000_phy_unknown = 0, 221 e1000_phy_none, 222 e1000_phy_m88, 223 e1000_phy_igp, 224 e1000_phy_igp_2, 225 e1000_phy_gg82563, 226 e1000_phy_igp_3, 227 e1000_phy_ife, 228 e1000_phy_bm, 229 e1000_phy_82578, 230 e1000_phy_82577, 231 e1000_phy_82580, 232 e1000_phy_vf, 233 }; 234 235 enum e1000_bus_type { 236 e1000_bus_type_unknown = 0, 237 e1000_bus_type_pci, 238 e1000_bus_type_pcix, 239 e1000_bus_type_pci_express, 240 e1000_bus_type_reserved 241 }; 242 243 enum e1000_bus_speed { 244 e1000_bus_speed_unknown = 0, 245 e1000_bus_speed_33, 246 e1000_bus_speed_66, 247 e1000_bus_speed_100, 248 e1000_bus_speed_120, 249 e1000_bus_speed_133, 250 e1000_bus_speed_2500, 251 e1000_bus_speed_5000, 252 e1000_bus_speed_reserved 253 }; 254 255 enum e1000_bus_width { 256 e1000_bus_width_unknown = 0, 257 e1000_bus_width_pcie_x1, 258 e1000_bus_width_pcie_x2, 259 e1000_bus_width_pcie_x4 = 4, 260 e1000_bus_width_pcie_x8 = 8, 261 e1000_bus_width_32, 262 e1000_bus_width_64, 263 e1000_bus_width_reserved 264 }; 265 266 enum e1000_1000t_rx_status { 267 e1000_1000t_rx_status_not_ok = 0, 268 e1000_1000t_rx_status_ok, 269 e1000_1000t_rx_status_undefined = 0xFF 270 }; 271 272 enum e1000_rev_polarity { 273 e1000_rev_polarity_normal = 0, 274 e1000_rev_polarity_reversed, 275 e1000_rev_polarity_undefined = 0xFF 276 }; 277 278 enum e1000_fc_mode { 279 e1000_fc_none = 0, 280 e1000_fc_rx_pause, 281 e1000_fc_tx_pause, 282 e1000_fc_full, 283 e1000_fc_default = 0xFF 284 }; 285 286 enum e1000_ffe_config { 287 e1000_ffe_config_enabled = 0, 288 e1000_ffe_config_active, 289 e1000_ffe_config_blocked 290 }; 291 292 enum e1000_dsp_config { 293 e1000_dsp_config_disabled = 0, 294 e1000_dsp_config_enabled, 295 e1000_dsp_config_activated, 296 e1000_dsp_config_undefined = 0xFF 297 }; 298 299 enum e1000_ms_type { 300 e1000_ms_hw_default = 0, 301 e1000_ms_force_master, 302 e1000_ms_force_slave, 303 e1000_ms_auto 304 }; 305 306 enum e1000_smart_speed { 307 e1000_smart_speed_default = 0, 308 e1000_smart_speed_on, 309 e1000_smart_speed_off 310 }; 311 312 enum e1000_serdes_link_state { 313 e1000_serdes_link_down = 0, 314 e1000_serdes_link_autoneg_progress, 315 e1000_serdes_link_autoneg_complete, 316 e1000_serdes_link_forced_up 317 }; 318 319 /* Receive Descriptor */ 320 struct e1000_rx_desc { 321 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 322 __le16 length; /* Length of data DMAed into data buffer */ 323 __le16 csum; /* Packet checksum */ 324 u8 status; /* Descriptor status */ 325 u8 errors; /* Descriptor Errors */ 326 __le16 special; 327 }; 328 329 /* Receive Descriptor - Extended */ 330 union e1000_rx_desc_extended { 331 struct { 332 __le64 buffer_addr; 333 __le64 reserved; 334 } read; 335 struct { 336 struct { 337 __le32 mrq; /* Multiple Rx Queues */ 338 union { 339 __le32 rss; /* RSS Hash */ 340 struct { 341 __le16 ip_id; /* IP id */ 342 __le16 csum; /* Packet Checksum */ 343 } csum_ip; 344 } hi_dword; 345 } lower; 346 struct { 347 __le32 status_error; /* ext status/error */ 348 __le16 length; 349 __le16 vlan; /* VLAN tag */ 350 } upper; 351 } wb; /* writeback */ 352 }; 353 354 #define MAX_PS_BUFFERS 4 355 /* Receive Descriptor - Packet Split */ 356 union e1000_rx_desc_packet_split { 357 struct { 358 /* one buffer for protocol header(s), three data buffers */ 359 __le64 buffer_addr[MAX_PS_BUFFERS]; 360 } read; 361 struct { 362 struct { 363 __le32 mrq; /* Multiple Rx Queues */ 364 union { 365 __le32 rss; /* RSS Hash */ 366 struct { 367 __le16 ip_id; /* IP id */ 368 __le16 csum; /* Packet Checksum */ 369 } csum_ip; 370 } hi_dword; 371 } lower; 372 struct { 373 __le32 status_error; /* ext status/error */ 374 __le16 length0; /* length of buffer 0 */ 375 __le16 vlan; /* VLAN tag */ 376 } middle; 377 struct { 378 __le16 header_status; 379 __le16 length[3]; /* length of buffers 1-3 */ 380 } upper; 381 __le64 reserved; 382 } wb; /* writeback */ 383 }; 384 385 /* Transmit Descriptor */ 386 struct e1000_tx_desc { 387 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 388 union { 389 __le32 data; 390 struct { 391 __le16 length; /* Data buffer length */ 392 u8 cso; /* Checksum offset */ 393 u8 cmd; /* Descriptor control */ 394 } flags; 395 } lower; 396 union { 397 __le32 data; 398 struct { 399 u8 status; /* Descriptor status */ 400 u8 css; /* Checksum start */ 401 __le16 special; 402 } fields; 403 } upper; 404 }; 405 406 /* Offload Context Descriptor */ 407 struct e1000_context_desc { 408 union { 409 __le32 ip_config; 410 struct { 411 u8 ipcss; /* IP checksum start */ 412 u8 ipcso; /* IP checksum offset */ 413 __le16 ipcse; /* IP checksum end */ 414 } ip_fields; 415 } lower_setup; 416 union { 417 __le32 tcp_config; 418 struct { 419 u8 tucss; /* TCP checksum start */ 420 u8 tucso; /* TCP checksum offset */ 421 __le16 tucse; /* TCP checksum end */ 422 } tcp_fields; 423 } upper_setup; 424 __le32 cmd_and_length; 425 union { 426 __le32 data; 427 struct { 428 u8 status; /* Descriptor status */ 429 u8 hdr_len; /* Header length */ 430 __le16 mss; /* Maximum segment size */ 431 } fields; 432 } tcp_seg_setup; 433 }; 434 435 /* Offload data descriptor */ 436 struct e1000_data_desc { 437 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 438 union { 439 __le32 data; 440 struct { 441 __le16 length; /* Data buffer length */ 442 u8 typ_len_ext; 443 u8 cmd; 444 } flags; 445 } lower; 446 union { 447 __le32 data; 448 struct { 449 u8 status; /* Descriptor status */ 450 u8 popts; /* Packet Options */ 451 __le16 special; 452 } fields; 453 } upper; 454 }; 455 456 /* Statistics counters collected by the MAC */ 457 struct e1000_hw_stats { 458 u64 crcerrs; 459 u64 algnerrc; 460 u64 symerrs; 461 u64 rxerrc; 462 u64 mpc; 463 u64 scc; 464 u64 ecol; 465 u64 mcc; 466 u64 latecol; 467 u64 colc; 468 u64 dc; 469 u64 tncrs; 470 u64 sec; 471 u64 cexterr; 472 u64 rlec; 473 u64 xonrxc; 474 u64 xontxc; 475 u64 xoffrxc; 476 u64 xofftxc; 477 u64 fcruc; 478 u64 prc64; 479 u64 prc127; 480 u64 prc255; 481 u64 prc511; 482 u64 prc1023; 483 u64 prc1522; 484 u64 gprc; 485 u64 bprc; 486 u64 mprc; 487 u64 gptc; 488 u64 gorc; 489 u64 gotc; 490 u64 rnbc; 491 u64 ruc; 492 u64 rfc; 493 u64 roc; 494 u64 rjc; 495 u64 mgprc; 496 u64 mgpdc; 497 u64 mgptc; 498 u64 tor; 499 u64 tot; 500 u64 tpr; 501 u64 tpt; 502 u64 ptc64; 503 u64 ptc127; 504 u64 ptc255; 505 u64 ptc511; 506 u64 ptc1023; 507 u64 ptc1522; 508 u64 mptc; 509 u64 bptc; 510 u64 tsctc; 511 u64 tsctfc; 512 u64 iac; 513 u64 icrxptc; 514 u64 icrxatc; 515 u64 ictxptc; 516 u64 ictxatc; 517 u64 ictxqec; 518 u64 ictxqmtc; 519 u64 icrxdmtc; 520 u64 icrxoc; 521 u64 cbtmpc; 522 u64 htdpmc; 523 u64 cbrdpc; 524 u64 cbrmpc; 525 u64 rpthc; 526 u64 hgptc; 527 u64 htcbdpc; 528 u64 hgorc; 529 u64 hgotc; 530 u64 lenerrs; 531 u64 scvpc; 532 u64 hrmpc; 533 u64 doosync; 534 }; 535 536 struct e1000_vf_stats { 537 u64 base_gprc; 538 u64 base_gptc; 539 u64 base_gorc; 540 u64 base_gotc; 541 u64 base_mprc; 542 u64 base_gotlbc; 543 u64 base_gptlbc; 544 u64 base_gorlbc; 545 u64 base_gprlbc; 546 547 u32 last_gprc; 548 u32 last_gptc; 549 u32 last_gorc; 550 u32 last_gotc; 551 u32 last_mprc; 552 u32 last_gotlbc; 553 u32 last_gptlbc; 554 u32 last_gorlbc; 555 u32 last_gprlbc; 556 557 u64 gprc; 558 u64 gptc; 559 u64 gorc; 560 u64 gotc; 561 u64 mprc; 562 u64 gotlbc; 563 u64 gptlbc; 564 u64 gorlbc; 565 u64 gprlbc; 566 }; 567 568 struct e1000_phy_stats { 569 u32 idle_errors; 570 u32 receive_errors; 571 }; 572 573 struct e1000_host_mng_dhcp_cookie { 574 u32 signature; 575 u8 status; 576 u8 reserved0; 577 u16 vlan_id; 578 u32 reserved1; 579 u16 reserved2; 580 u8 reserved3; 581 u8 checksum; 582 }; 583 584 /* Host Interface "Rev 1" */ 585 struct e1000_host_command_header { 586 u8 command_id; 587 u8 command_length; 588 u8 command_options; 589 u8 checksum; 590 }; 591 592 #define E1000_HI_MAX_DATA_LENGTH 252 593 struct e1000_host_command_info { 594 struct e1000_host_command_header command_header; 595 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 596 }; 597 598 /* Host Interface "Rev 2" */ 599 struct e1000_host_mng_command_header { 600 u8 command_id; 601 u8 checksum; 602 u16 reserved1; 603 u16 reserved2; 604 u16 command_length; 605 }; 606 607 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 608 struct e1000_host_mng_command_info { 609 struct e1000_host_mng_command_header command_header; 610 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 611 }; 612 613 #include "e1000_mac.h" 614 #include "e1000_phy.h" 615 #include "e1000_nvm.h" 616 #include "e1000_manage.h" 617 #include "e1000_mbx.h" 618 619 struct e1000_mac_operations { 620 /* Function pointers for the MAC. */ 621 s32 (*init_params)(struct e1000_hw *); 622 s32 (*id_led_init)(struct e1000_hw *); 623 s32 (*blink_led)(struct e1000_hw *); 624 s32 (*check_for_link)(struct e1000_hw *); 625 bool (*check_mng_mode)(struct e1000_hw *hw); 626 s32 (*cleanup_led)(struct e1000_hw *); 627 void (*clear_hw_cntrs)(struct e1000_hw *); 628 void (*clear_vfta)(struct e1000_hw *); 629 s32 (*get_bus_info)(struct e1000_hw *); 630 void (*set_lan_id)(struct e1000_hw *); 631 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 632 s32 (*led_on)(struct e1000_hw *); 633 s32 (*led_off)(struct e1000_hw *); 634 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 635 s32 (*reset_hw)(struct e1000_hw *); 636 s32 (*init_hw)(struct e1000_hw *); 637 void (*shutdown_serdes)(struct e1000_hw *); 638 void (*power_up_serdes)(struct e1000_hw *); 639 s32 (*setup_link)(struct e1000_hw *); 640 s32 (*setup_physical_interface)(struct e1000_hw *); 641 s32 (*setup_led)(struct e1000_hw *); 642 void (*write_vfta)(struct e1000_hw *, u32, u32); 643 void (*config_collision_dist)(struct e1000_hw *); 644 void (*rar_set)(struct e1000_hw *, u8*, u32); 645 s32 (*read_mac_addr)(struct e1000_hw *); 646 s32 (*validate_mdi_setting)(struct e1000_hw *); 647 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); 648 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 649 struct e1000_host_mng_command_header*); 650 s32 (*mng_enable_host_if)(struct e1000_hw *); 651 s32 (*wait_autoneg)(struct e1000_hw *); 652 }; 653 654 struct e1000_phy_operations { 655 s32 (*init_params)(struct e1000_hw *); 656 s32 (*acquire)(struct e1000_hw *); 657 s32 (*cfg_on_link_up)(struct e1000_hw *); 658 s32 (*check_polarity)(struct e1000_hw *); 659 s32 (*check_reset_block)(struct e1000_hw *); 660 s32 (*commit)(struct e1000_hw *); 661 s32 (*force_speed_duplex)(struct e1000_hw *); 662 s32 (*get_cfg_done)(struct e1000_hw *hw); 663 s32 (*get_cable_length)(struct e1000_hw *); 664 s32 (*get_info)(struct e1000_hw *); 665 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 666 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 667 void (*release)(struct e1000_hw *); 668 s32 (*reset)(struct e1000_hw *); 669 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 670 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 671 s32 (*write_reg)(struct e1000_hw *, u32, u16); 672 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 673 void (*power_up)(struct e1000_hw *); 674 void (*power_down)(struct e1000_hw *); 675 }; 676 677 struct e1000_nvm_operations { 678 s32 (*init_params)(struct e1000_hw *); 679 s32 (*acquire)(struct e1000_hw *); 680 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 681 void (*release)(struct e1000_hw *); 682 void (*reload)(struct e1000_hw *); 683 s32 (*update)(struct e1000_hw *); 684 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 685 s32 (*validate)(struct e1000_hw *); 686 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 687 }; 688 689 struct e1000_mac_info { 690 struct e1000_mac_operations ops; 691 u8 addr[6]; 692 u8 perm_addr[6]; 693 694 enum e1000_mac_type type; 695 696 u32 collision_delta; 697 u32 ledctl_default; 698 u32 ledctl_mode1; 699 u32 ledctl_mode2; 700 u32 mc_filter_type; 701 u32 tx_packet_delta; 702 u32 txcw; 703 704 u16 current_ifs_val; 705 u16 ifs_max_val; 706 u16 ifs_min_val; 707 u16 ifs_ratio; 708 u16 ifs_step_size; 709 u16 mta_reg_count; 710 u16 uta_reg_count; 711 712 /* Maximum size of the MTA register table in all supported adapters */ 713 #define MAX_MTA_REG 128 714 u32 mta_shadow[MAX_MTA_REG]; 715 u16 rar_entry_count; 716 717 u8 forced_speed_duplex; 718 719 bool adaptive_ifs; 720 bool has_fwsm; 721 bool arc_subsystem_valid; 722 bool asf_firmware_present; 723 bool autoneg; 724 bool autoneg_failed; 725 bool get_link_status; 726 bool in_ifs_mode; 727 bool report_tx_early; 728 enum e1000_serdes_link_state serdes_link_state; 729 bool serdes_has_link; 730 bool tx_pkt_filtering; 731 }; 732 733 struct e1000_phy_info { 734 struct e1000_phy_operations ops; 735 enum e1000_phy_type type; 736 737 enum e1000_1000t_rx_status local_rx; 738 enum e1000_1000t_rx_status remote_rx; 739 enum e1000_ms_type ms_type; 740 enum e1000_ms_type original_ms_type; 741 enum e1000_rev_polarity cable_polarity; 742 enum e1000_smart_speed smart_speed; 743 744 u32 addr; 745 u32 id; 746 u32 reset_delay_us; /* in usec */ 747 u32 revision; 748 749 enum e1000_media_type media_type; 750 751 u16 autoneg_advertised; 752 u16 autoneg_mask; 753 u16 cable_length; 754 u16 max_cable_length; 755 u16 min_cable_length; 756 757 u8 mdix; 758 759 bool disable_polarity_correction; 760 bool is_mdix; 761 bool polarity_correction; 762 bool reset_disable; 763 bool speed_downgraded; 764 bool autoneg_wait_to_complete; 765 }; 766 767 struct e1000_nvm_info { 768 struct e1000_nvm_operations ops; 769 enum e1000_nvm_type type; 770 enum e1000_nvm_override override; 771 772 u32 flash_bank_size; 773 u32 flash_base_addr; 774 775 u16 word_size; 776 u16 delay_usec; 777 u16 address_bits; 778 u16 opcode_bits; 779 u16 page_size; 780 }; 781 782 struct e1000_bus_info { 783 enum e1000_bus_type type; 784 enum e1000_bus_speed speed; 785 enum e1000_bus_width width; 786 787 u16 func; 788 u16 pci_cmd_word; 789 }; 790 791 struct e1000_fc_info { 792 u32 high_water; /* Flow control high-water mark */ 793 u32 low_water; /* Flow control low-water mark */ 794 u16 pause_time; /* Flow control pause timer */ 795 u16 refresh_time; /* Flow control refresh timer */ 796 bool send_xon; /* Flow control send XON */ 797 bool strict_ieee; /* Strict IEEE mode */ 798 enum e1000_fc_mode current_mode; /* FC mode in effect */ 799 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 800 }; 801 802 struct e1000_dev_spec_82541 { 803 enum e1000_dsp_config dsp_config; 804 enum e1000_ffe_config ffe_config; 805 u16 spd_default; 806 bool phy_init_script; 807 }; 808 809 struct e1000_dev_spec_82542 { 810 bool dma_fairness; 811 }; 812 813 struct e1000_dev_spec_82543 { 814 u32 tbi_compatibility; 815 bool dma_fairness; 816 bool init_phy_disabled; 817 }; 818 819 struct e1000_dev_spec_82571 { 820 bool laa_is_present; 821 u32 smb_counter; 822 }; 823 824 struct e1000_dev_spec_80003es2lan { 825 bool mdic_wa_enable; 826 }; 827 828 struct e1000_shadow_ram { 829 u16 value; 830 bool modified; 831 }; 832 833 #define E1000_SHADOW_RAM_WORDS 2048 834 835 struct e1000_dev_spec_ich8lan { 836 bool kmrn_lock_loss_workaround_enabled; 837 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 838 E1000_MUTEX nvm_mutex; 839 E1000_MUTEX swflag_mutex; 840 bool nvm_k1_enabled; 841 }; 842 843 struct e1000_mbx_operations { 844 s32 (*init_params)(struct e1000_hw *hw); 845 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 846 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 847 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 848 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 849 s32 (*check_for_msg)(struct e1000_hw *, u16); 850 s32 (*check_for_ack)(struct e1000_hw *, u16); 851 s32 (*check_for_rst)(struct e1000_hw *, u16); 852 }; 853 854 struct e1000_mbx_stats { 855 u32 msgs_tx; 856 u32 msgs_rx; 857 u32 acks; 858 u32 reqs; 859 u32 rsts; 860 }; 861 862 struct e1000_mbx_info { 863 struct e1000_mbx_operations ops; 864 struct e1000_mbx_stats stats; 865 u32 timeout; 866 u32 usec_delay; 867 u16 size; 868 }; 869 870 struct e1000_dev_spec_82575 { 871 bool sgmii_active; 872 bool global_device_reset; 873 }; 874 875 struct e1000_dev_spec_vf { 876 u32 vf_number; 877 u32 v2p_mailbox; 878 }; 879 880 881 struct e1000_hw { 882 void *back; 883 884 u8 *hw_addr; 885 u8 *flash_address; 886 unsigned long io_base; 887 888 struct e1000_mac_info mac; 889 struct e1000_fc_info fc; 890 struct e1000_phy_info phy; 891 struct e1000_nvm_info nvm; 892 struct e1000_bus_info bus; 893 struct e1000_mbx_info mbx; 894 struct e1000_host_mng_dhcp_cookie mng_cookie; 895 896 union { 897 struct e1000_dev_spec_82541 _82541; 898 struct e1000_dev_spec_82542 _82542; 899 struct e1000_dev_spec_82543 _82543; 900 struct e1000_dev_spec_82571 _82571; 901 struct e1000_dev_spec_80003es2lan _80003es2lan; 902 struct e1000_dev_spec_ich8lan ich8lan; 903 struct e1000_dev_spec_82575 _82575; 904 struct e1000_dev_spec_vf vf; 905 } dev_spec; 906 907 u16 device_id; 908 u16 subsystem_vendor_id; 909 u16 subsystem_device_id; 910 u16 vendor_id; 911 912 u8 revision_id; 913 }; 914 915 #include "e1000_82541.h" 916 #include "e1000_82543.h" 917 #include "e1000_82571.h" 918 #include "e1000_80003es2lan.h" 919 #include "e1000_ich8lan.h" 920 #include "e1000_82575.h" 921 922 /* These functions must be implemented by drivers */ 923 void e1000_pci_clear_mwi(struct e1000_hw *hw); 924 void e1000_pci_set_mwi(struct e1000_hw *hw); 925 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 926 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 927 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 928 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 929 930 #endif 931