1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2015, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #ifndef _E1000_HW_H_ 37 #define _E1000_HW_H_ 38 39 #include "e1000_osdep.h" 40 #include "e1000_regs.h" 41 #include "e1000_defines.h" 42 43 struct e1000_hw; 44 45 #define E1000_DEV_ID_82542 0x1000 46 #define E1000_DEV_ID_82543GC_FIBER 0x1001 47 #define E1000_DEV_ID_82543GC_COPPER 0x1004 48 #define E1000_DEV_ID_82544EI_COPPER 0x1008 49 #define E1000_DEV_ID_82544EI_FIBER 0x1009 50 #define E1000_DEV_ID_82544GC_COPPER 0x100C 51 #define E1000_DEV_ID_82544GC_LOM 0x100D 52 #define E1000_DEV_ID_82540EM 0x100E 53 #define E1000_DEV_ID_82540EM_LOM 0x1015 54 #define E1000_DEV_ID_82540EP_LOM 0x1016 55 #define E1000_DEV_ID_82540EP 0x1017 56 #define E1000_DEV_ID_82540EP_LP 0x101E 57 #define E1000_DEV_ID_82545EM_COPPER 0x100F 58 #define E1000_DEV_ID_82545EM_FIBER 0x1011 59 #define E1000_DEV_ID_82545GM_COPPER 0x1026 60 #define E1000_DEV_ID_82545GM_FIBER 0x1027 61 #define E1000_DEV_ID_82545GM_SERDES 0x1028 62 #define E1000_DEV_ID_82546EB_COPPER 0x1010 63 #define E1000_DEV_ID_82546EB_FIBER 0x1012 64 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 65 #define E1000_DEV_ID_82546GB_COPPER 0x1079 66 #define E1000_DEV_ID_82546GB_FIBER 0x107A 67 #define E1000_DEV_ID_82546GB_SERDES 0x107B 68 #define E1000_DEV_ID_82546GB_PCIE 0x108A 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 70 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 71 #define E1000_DEV_ID_82541EI 0x1013 72 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 73 #define E1000_DEV_ID_82541ER_LOM 0x1014 74 #define E1000_DEV_ID_82541ER 0x1078 75 #define E1000_DEV_ID_82541GI 0x1076 76 #define E1000_DEV_ID_82541GI_LF 0x107C 77 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 78 #define E1000_DEV_ID_82547EI 0x1019 79 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 80 #define E1000_DEV_ID_82547GI 0x1075 81 #define E1000_DEV_ID_82571EB_COPPER 0x105E 82 #define E1000_DEV_ID_82571EB_FIBER 0x105F 83 #define E1000_DEV_ID_82571EB_SERDES 0x1060 84 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 85 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 86 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 87 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 88 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 90 #define E1000_DEV_ID_82572EI_COPPER 0x107D 91 #define E1000_DEV_ID_82572EI_FIBER 0x107E 92 #define E1000_DEV_ID_82572EI_SERDES 0x107F 93 #define E1000_DEV_ID_82572EI 0x10B9 94 #define E1000_DEV_ID_82573E 0x108B 95 #define E1000_DEV_ID_82573E_IAMT 0x108C 96 #define E1000_DEV_ID_82573L 0x109A 97 #define E1000_DEV_ID_82574L 0x10D3 98 #define E1000_DEV_ID_82574LA 0x10F6 99 #define E1000_DEV_ID_82583V 0x150C 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 104 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 105 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 106 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 107 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 108 #define E1000_DEV_ID_ICH8_IFE 0x104C 109 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 110 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 111 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 112 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 113 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 114 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 115 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 116 #define E1000_DEV_ID_ICH9_BM 0x10E5 117 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 118 #define E1000_DEV_ID_ICH9_IFE 0x10C0 119 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 120 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 121 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 122 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 123 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 124 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 128 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 129 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 130 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 131 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 132 #define E1000_DEV_ID_PCH2_LV_V 0x1503 133 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 134 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 136 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 137 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 138 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 139 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 140 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 141 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 142 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 143 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 144 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 145 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 146 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 147 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 148 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 149 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 150 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 151 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 152 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 153 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 154 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 155 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 156 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 157 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 158 #define E1000_DEV_ID_PCH_ICP_I219_V10 0x0D4F 159 #define E1000_DEV_ID_82576 0x10C9 160 #define E1000_DEV_ID_82576_FIBER 0x10E6 161 #define E1000_DEV_ID_82576_SERDES 0x10E7 162 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 163 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 164 #define E1000_DEV_ID_82576_NS 0x150A 165 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 166 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 167 #define E1000_DEV_ID_82576_VF 0x10CA 168 #define E1000_DEV_ID_82576_VF_HV 0x152D 169 #define E1000_DEV_ID_I350_VF 0x1520 170 #define E1000_DEV_ID_I350_VF_HV 0x152F 171 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 172 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 173 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 174 #define E1000_DEV_ID_82580_COPPER 0x150E 175 #define E1000_DEV_ID_82580_FIBER 0x150F 176 #define E1000_DEV_ID_82580_SERDES 0x1510 177 #define E1000_DEV_ID_82580_SGMII 0x1511 178 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 179 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 180 #define E1000_DEV_ID_I350_COPPER 0x1521 181 #define E1000_DEV_ID_I350_FIBER 0x1522 182 #define E1000_DEV_ID_I350_SERDES 0x1523 183 #define E1000_DEV_ID_I350_SGMII 0x1524 184 #define E1000_DEV_ID_I350_DA4 0x1546 185 #define E1000_DEV_ID_I210_COPPER 0x1533 186 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 187 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 188 #define E1000_DEV_ID_I210_FIBER 0x1536 189 #define E1000_DEV_ID_I210_SERDES 0x1537 190 #define E1000_DEV_ID_I210_SGMII 0x1538 191 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 192 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 193 #define E1000_DEV_ID_I211_COPPER 0x1539 194 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 195 #define E1000_DEV_ID_I354_SGMII 0x1F41 196 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 197 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 198 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 199 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 200 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 201 202 #define E1000_REVISION_0 0 203 #define E1000_REVISION_1 1 204 #define E1000_REVISION_2 2 205 #define E1000_REVISION_3 3 206 #define E1000_REVISION_4 4 207 208 #define E1000_FUNC_0 0 209 #define E1000_FUNC_1 1 210 #define E1000_FUNC_2 2 211 #define E1000_FUNC_3 3 212 213 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 214 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 215 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 216 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 217 218 enum e1000_mac_type { 219 e1000_undefined = 0, 220 e1000_82542, 221 e1000_82543, 222 e1000_82544, 223 e1000_82540, 224 e1000_82545, 225 e1000_82545_rev_3, 226 e1000_82546, 227 e1000_82546_rev_3, 228 e1000_82541, 229 e1000_82541_rev_2, 230 e1000_82547, 231 e1000_82547_rev_2, 232 e1000_82571, 233 e1000_82572, 234 e1000_82573, 235 e1000_82574, 236 e1000_82583, 237 e1000_80003es2lan, 238 e1000_ich8lan, 239 e1000_ich9lan, 240 e1000_ich10lan, 241 e1000_pchlan, 242 e1000_pch2lan, 243 e1000_pch_lpt, 244 e1000_pch_spt, 245 e1000_pch_cnp, 246 e1000_82575, 247 e1000_82576, 248 e1000_82580, 249 e1000_i350, 250 e1000_i354, 251 e1000_i210, 252 e1000_i211, 253 e1000_vfadapt, 254 e1000_vfadapt_i350, 255 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 256 }; 257 258 enum e1000_media_type { 259 e1000_media_type_unknown = 0, 260 e1000_media_type_copper = 1, 261 e1000_media_type_fiber = 2, 262 e1000_media_type_internal_serdes = 3, 263 e1000_num_media_types 264 }; 265 266 enum e1000_nvm_type { 267 e1000_nvm_unknown = 0, 268 e1000_nvm_none, 269 e1000_nvm_eeprom_spi, 270 e1000_nvm_eeprom_microwire, 271 e1000_nvm_flash_hw, 272 e1000_nvm_invm, 273 e1000_nvm_flash_sw 274 }; 275 276 enum e1000_nvm_override { 277 e1000_nvm_override_none = 0, 278 e1000_nvm_override_spi_small, 279 e1000_nvm_override_spi_large, 280 e1000_nvm_override_microwire_small, 281 e1000_nvm_override_microwire_large 282 }; 283 284 enum e1000_phy_type { 285 e1000_phy_unknown = 0, 286 e1000_phy_none, 287 e1000_phy_m88, 288 e1000_phy_igp, 289 e1000_phy_igp_2, 290 e1000_phy_gg82563, 291 e1000_phy_igp_3, 292 e1000_phy_ife, 293 e1000_phy_bm, 294 e1000_phy_82578, 295 e1000_phy_82577, 296 e1000_phy_82579, 297 e1000_phy_i217, 298 e1000_phy_82580, 299 e1000_phy_vf, 300 e1000_phy_i210, 301 }; 302 303 enum e1000_bus_type { 304 e1000_bus_type_unknown = 0, 305 e1000_bus_type_pci, 306 e1000_bus_type_pcix, 307 e1000_bus_type_pci_express, 308 e1000_bus_type_reserved 309 }; 310 311 enum e1000_bus_speed { 312 e1000_bus_speed_unknown = 0, 313 e1000_bus_speed_33, 314 e1000_bus_speed_66, 315 e1000_bus_speed_100, 316 e1000_bus_speed_120, 317 e1000_bus_speed_133, 318 e1000_bus_speed_2500, 319 e1000_bus_speed_5000, 320 e1000_bus_speed_reserved 321 }; 322 323 enum e1000_bus_width { 324 e1000_bus_width_unknown = 0, 325 e1000_bus_width_pcie_x1, 326 e1000_bus_width_pcie_x2, 327 e1000_bus_width_pcie_x4 = 4, 328 e1000_bus_width_pcie_x8 = 8, 329 e1000_bus_width_32, 330 e1000_bus_width_64, 331 e1000_bus_width_reserved 332 }; 333 334 enum e1000_1000t_rx_status { 335 e1000_1000t_rx_status_not_ok = 0, 336 e1000_1000t_rx_status_ok, 337 e1000_1000t_rx_status_undefined = 0xFF 338 }; 339 340 enum e1000_rev_polarity { 341 e1000_rev_polarity_normal = 0, 342 e1000_rev_polarity_reversed, 343 e1000_rev_polarity_undefined = 0xFF 344 }; 345 346 enum e1000_fc_mode { 347 e1000_fc_none = 0, 348 e1000_fc_rx_pause, 349 e1000_fc_tx_pause, 350 e1000_fc_full, 351 e1000_fc_default = 0xFF 352 }; 353 354 enum e1000_ffe_config { 355 e1000_ffe_config_enabled = 0, 356 e1000_ffe_config_active, 357 e1000_ffe_config_blocked 358 }; 359 360 enum e1000_dsp_config { 361 e1000_dsp_config_disabled = 0, 362 e1000_dsp_config_enabled, 363 e1000_dsp_config_activated, 364 e1000_dsp_config_undefined = 0xFF 365 }; 366 367 enum e1000_ms_type { 368 e1000_ms_hw_default = 0, 369 e1000_ms_force_master, 370 e1000_ms_force_slave, 371 e1000_ms_auto 372 }; 373 374 enum e1000_smart_speed { 375 e1000_smart_speed_default = 0, 376 e1000_smart_speed_on, 377 e1000_smart_speed_off 378 }; 379 380 enum e1000_serdes_link_state { 381 e1000_serdes_link_down = 0, 382 e1000_serdes_link_autoneg_progress, 383 e1000_serdes_link_autoneg_complete, 384 e1000_serdes_link_forced_up 385 }; 386 387 #define __le16 u16 388 #define __le32 u32 389 #define __le64 u64 390 /* Receive Descriptor */ 391 struct e1000_rx_desc { 392 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 393 __le16 length; /* Length of data DMAed into data buffer */ 394 __le16 csum; /* Packet checksum */ 395 u8 status; /* Descriptor status */ 396 u8 errors; /* Descriptor Errors */ 397 __le16 special; 398 }; 399 400 /* Receive Descriptor - Extended */ 401 union e1000_rx_desc_extended { 402 struct { 403 __le64 buffer_addr; 404 __le64 reserved; 405 } read; 406 struct { 407 struct { 408 __le32 mrq; /* Multiple Rx Queues */ 409 union { 410 __le32 rss; /* RSS Hash */ 411 struct { 412 __le16 ip_id; /* IP id */ 413 __le16 csum; /* Packet Checksum */ 414 } csum_ip; 415 } hi_dword; 416 } lower; 417 struct { 418 __le32 status_error; /* ext status/error */ 419 __le16 length; 420 __le16 vlan; /* VLAN tag */ 421 } upper; 422 } wb; /* writeback */ 423 }; 424 425 #define MAX_PS_BUFFERS 4 426 427 /* Number of packet split data buffers (not including the header buffer) */ 428 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 429 430 /* Receive Descriptor - Packet Split */ 431 union e1000_rx_desc_packet_split { 432 struct { 433 /* one buffer for protocol header(s), three data buffers */ 434 __le64 buffer_addr[MAX_PS_BUFFERS]; 435 } read; 436 struct { 437 struct { 438 __le32 mrq; /* Multiple Rx Queues */ 439 union { 440 __le32 rss; /* RSS Hash */ 441 struct { 442 __le16 ip_id; /* IP id */ 443 __le16 csum; /* Packet Checksum */ 444 } csum_ip; 445 } hi_dword; 446 } lower; 447 struct { 448 __le32 status_error; /* ext status/error */ 449 __le16 length0; /* length of buffer 0 */ 450 __le16 vlan; /* VLAN tag */ 451 } middle; 452 struct { 453 __le16 header_status; 454 /* length of buffers 1-3 */ 455 __le16 length[PS_PAGE_BUFFERS]; 456 } upper; 457 __le64 reserved; 458 } wb; /* writeback */ 459 }; 460 461 /* Transmit Descriptor */ 462 struct e1000_tx_desc { 463 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 464 union { 465 __le32 data; 466 struct { 467 __le16 length; /* Data buffer length */ 468 u8 cso; /* Checksum offset */ 469 u8 cmd; /* Descriptor control */ 470 } flags; 471 } lower; 472 union { 473 __le32 data; 474 struct { 475 u8 status; /* Descriptor status */ 476 u8 css; /* Checksum start */ 477 __le16 special; 478 } fields; 479 } upper; 480 }; 481 482 /* Offload Context Descriptor */ 483 struct e1000_context_desc { 484 union { 485 __le32 ip_config; 486 struct { 487 u8 ipcss; /* IP checksum start */ 488 u8 ipcso; /* IP checksum offset */ 489 __le16 ipcse; /* IP checksum end */ 490 } ip_fields; 491 } lower_setup; 492 union { 493 __le32 tcp_config; 494 struct { 495 u8 tucss; /* TCP checksum start */ 496 u8 tucso; /* TCP checksum offset */ 497 __le16 tucse; /* TCP checksum end */ 498 } tcp_fields; 499 } upper_setup; 500 __le32 cmd_and_length; 501 union { 502 __le32 data; 503 struct { 504 u8 status; /* Descriptor status */ 505 u8 hdr_len; /* Header length */ 506 __le16 mss; /* Maximum segment size */ 507 } fields; 508 } tcp_seg_setup; 509 }; 510 511 /* Offload data descriptor */ 512 struct e1000_data_desc { 513 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 514 union { 515 __le32 data; 516 struct { 517 __le16 length; /* Data buffer length */ 518 u8 typ_len_ext; 519 u8 cmd; 520 } flags; 521 } lower; 522 union { 523 __le32 data; 524 struct { 525 u8 status; /* Descriptor status */ 526 u8 popts; /* Packet Options */ 527 __le16 special; 528 } fields; 529 } upper; 530 }; 531 532 /* Statistics counters collected by the MAC */ 533 struct e1000_hw_stats { 534 u64 crcerrs; 535 u64 algnerrc; 536 u64 symerrs; 537 u64 rxerrc; 538 u64 mpc; 539 u64 scc; 540 u64 ecol; 541 u64 mcc; 542 u64 latecol; 543 u64 colc; 544 u64 dc; 545 u64 tncrs; 546 u64 sec; 547 u64 cexterr; 548 u64 rlec; 549 u64 xonrxc; 550 u64 xontxc; 551 u64 xoffrxc; 552 u64 xofftxc; 553 u64 fcruc; 554 u64 prc64; 555 u64 prc127; 556 u64 prc255; 557 u64 prc511; 558 u64 prc1023; 559 u64 prc1522; 560 u64 gprc; 561 u64 bprc; 562 u64 mprc; 563 u64 gptc; 564 u64 gorc; 565 u64 gotc; 566 u64 rnbc; 567 u64 ruc; 568 u64 rfc; 569 u64 roc; 570 u64 rjc; 571 u64 mgprc; 572 u64 mgpdc; 573 u64 mgptc; 574 u64 tor; 575 u64 tot; 576 u64 tpr; 577 u64 tpt; 578 u64 ptc64; 579 u64 ptc127; 580 u64 ptc255; 581 u64 ptc511; 582 u64 ptc1023; 583 u64 ptc1522; 584 u64 mptc; 585 u64 bptc; 586 u64 tsctc; 587 u64 tsctfc; 588 u64 iac; 589 u64 icrxptc; 590 u64 icrxatc; 591 u64 ictxptc; 592 u64 ictxatc; 593 u64 ictxqec; 594 u64 ictxqmtc; 595 u64 icrxdmtc; 596 u64 icrxoc; 597 u64 cbtmpc; 598 u64 htdpmc; 599 u64 cbrdpc; 600 u64 cbrmpc; 601 u64 rpthc; 602 u64 hgptc; 603 u64 htcbdpc; 604 u64 hgorc; 605 u64 hgotc; 606 u64 lenerrs; 607 u64 scvpc; 608 u64 hrmpc; 609 u64 doosync; 610 u64 o2bgptc; 611 u64 o2bspc; 612 u64 b2ospc; 613 u64 b2ogprc; 614 }; 615 616 struct e1000_vf_stats { 617 u64 base_gprc; 618 u64 base_gptc; 619 u64 base_gorc; 620 u64 base_gotc; 621 u64 base_mprc; 622 u64 base_gotlbc; 623 u64 base_gptlbc; 624 u64 base_gorlbc; 625 u64 base_gprlbc; 626 627 u32 last_gprc; 628 u32 last_gptc; 629 u32 last_gorc; 630 u32 last_gotc; 631 u32 last_mprc; 632 u32 last_gotlbc; 633 u32 last_gptlbc; 634 u32 last_gorlbc; 635 u32 last_gprlbc; 636 637 u64 gprc; 638 u64 gptc; 639 u64 gorc; 640 u64 gotc; 641 u64 mprc; 642 u64 gotlbc; 643 u64 gptlbc; 644 u64 gorlbc; 645 u64 gprlbc; 646 }; 647 648 struct e1000_phy_stats { 649 u32 idle_errors; 650 u32 receive_errors; 651 }; 652 653 struct e1000_host_mng_dhcp_cookie { 654 u32 signature; 655 u8 status; 656 u8 reserved0; 657 u16 vlan_id; 658 u32 reserved1; 659 u16 reserved2; 660 u8 reserved3; 661 u8 checksum; 662 }; 663 664 /* Host Interface "Rev 1" */ 665 struct e1000_host_command_header { 666 u8 command_id; 667 u8 command_length; 668 u8 command_options; 669 u8 checksum; 670 }; 671 672 #define E1000_HI_MAX_DATA_LENGTH 252 673 struct e1000_host_command_info { 674 struct e1000_host_command_header command_header; 675 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 676 }; 677 678 /* Host Interface "Rev 2" */ 679 struct e1000_host_mng_command_header { 680 u8 command_id; 681 u8 checksum; 682 u16 reserved1; 683 u16 reserved2; 684 u16 command_length; 685 }; 686 687 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 688 struct e1000_host_mng_command_info { 689 struct e1000_host_mng_command_header command_header; 690 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 691 }; 692 693 #include "e1000_mac.h" 694 #include "e1000_phy.h" 695 #include "e1000_nvm.h" 696 #include "e1000_manage.h" 697 #include "e1000_mbx.h" 698 699 /* Function pointers for the MAC. */ 700 struct e1000_mac_operations { 701 s32 (*init_params)(struct e1000_hw *); 702 s32 (*id_led_init)(struct e1000_hw *); 703 s32 (*blink_led)(struct e1000_hw *); 704 bool (*check_mng_mode)(struct e1000_hw *); 705 s32 (*check_for_link)(struct e1000_hw *); 706 s32 (*cleanup_led)(struct e1000_hw *); 707 void (*clear_hw_cntrs)(struct e1000_hw *); 708 void (*clear_vfta)(struct e1000_hw *); 709 s32 (*get_bus_info)(struct e1000_hw *); 710 void (*set_lan_id)(struct e1000_hw *); 711 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 712 s32 (*led_on)(struct e1000_hw *); 713 s32 (*led_off)(struct e1000_hw *); 714 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 715 s32 (*reset_hw)(struct e1000_hw *); 716 s32 (*init_hw)(struct e1000_hw *); 717 void (*shutdown_serdes)(struct e1000_hw *); 718 void (*power_up_serdes)(struct e1000_hw *); 719 s32 (*setup_link)(struct e1000_hw *); 720 s32 (*setup_physical_interface)(struct e1000_hw *); 721 s32 (*setup_led)(struct e1000_hw *); 722 void (*write_vfta)(struct e1000_hw *, u32, u32); 723 void (*config_collision_dist)(struct e1000_hw *); 724 int (*rar_set)(struct e1000_hw *, u8*, u32); 725 s32 (*read_mac_addr)(struct e1000_hw *); 726 s32 (*validate_mdi_setting)(struct e1000_hw *); 727 s32 (*set_obff_timer)(struct e1000_hw *, u32); 728 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 729 void (*release_swfw_sync)(struct e1000_hw *, u16); 730 }; 731 732 /* When to use various PHY register access functions: 733 * 734 * Func Caller 735 * Function Does Does When to use 736 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 737 * X_reg L,P,A n/a for simple PHY reg accesses 738 * X_reg_locked P,A L for multiple accesses of different regs 739 * on different pages 740 * X_reg_page A L,P for multiple accesses of different regs 741 * on the same page 742 * 743 * Where X=[read|write], L=locking, P=sets page, A=register access 744 * 745 */ 746 struct e1000_phy_operations { 747 s32 (*init_params)(struct e1000_hw *); 748 s32 (*acquire)(struct e1000_hw *); 749 s32 (*cfg_on_link_up)(struct e1000_hw *); 750 s32 (*check_polarity)(struct e1000_hw *); 751 s32 (*check_reset_block)(struct e1000_hw *); 752 s32 (*commit)(struct e1000_hw *); 753 s32 (*force_speed_duplex)(struct e1000_hw *); 754 s32 (*get_cfg_done)(struct e1000_hw *hw); 755 s32 (*get_cable_length)(struct e1000_hw *); 756 s32 (*get_info)(struct e1000_hw *); 757 s32 (*set_page)(struct e1000_hw *, u16); 758 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 759 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 760 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 761 void (*release)(struct e1000_hw *); 762 s32 (*reset)(struct e1000_hw *); 763 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 764 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 765 s32 (*write_reg)(struct e1000_hw *, u32, u16); 766 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 767 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 768 void (*power_up)(struct e1000_hw *); 769 void (*power_down)(struct e1000_hw *); 770 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 771 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 772 }; 773 774 /* Function pointers for the NVM. */ 775 struct e1000_nvm_operations { 776 s32 (*init_params)(struct e1000_hw *); 777 s32 (*acquire)(struct e1000_hw *); 778 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 779 void (*release)(struct e1000_hw *); 780 void (*reload)(struct e1000_hw *); 781 s32 (*update)(struct e1000_hw *); 782 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 783 s32 (*validate)(struct e1000_hw *); 784 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 785 }; 786 787 struct e1000_mac_info { 788 struct e1000_mac_operations ops; 789 u8 addr[ETHER_ADDR_LEN]; 790 u8 perm_addr[ETHER_ADDR_LEN]; 791 792 enum e1000_mac_type type; 793 794 u32 collision_delta; 795 u32 ledctl_default; 796 u32 ledctl_mode1; 797 u32 ledctl_mode2; 798 u32 mc_filter_type; 799 u32 tx_packet_delta; 800 u32 txcw; 801 802 u16 current_ifs_val; 803 u16 ifs_max_val; 804 u16 ifs_min_val; 805 u16 ifs_ratio; 806 u16 ifs_step_size; 807 u16 mta_reg_count; 808 u16 uta_reg_count; 809 810 /* Maximum size of the MTA register table in all supported adapters */ 811 #define MAX_MTA_REG 128 812 u32 mta_shadow[MAX_MTA_REG]; 813 u16 rar_entry_count; 814 815 u8 forced_speed_duplex; 816 817 bool adaptive_ifs; 818 bool has_fwsm; 819 bool arc_subsystem_valid; 820 bool asf_firmware_present; 821 bool autoneg; 822 bool autoneg_failed; 823 bool get_link_status; 824 bool in_ifs_mode; 825 bool report_tx_early; 826 enum e1000_serdes_link_state serdes_link_state; 827 bool serdes_has_link; 828 bool tx_pkt_filtering; 829 u32 max_frame_size; 830 }; 831 832 struct e1000_phy_info { 833 struct e1000_phy_operations ops; 834 enum e1000_phy_type type; 835 836 enum e1000_1000t_rx_status local_rx; 837 enum e1000_1000t_rx_status remote_rx; 838 enum e1000_ms_type ms_type; 839 enum e1000_ms_type original_ms_type; 840 enum e1000_rev_polarity cable_polarity; 841 enum e1000_smart_speed smart_speed; 842 843 u32 addr; 844 u32 id; 845 u32 reset_delay_us; /* in usec */ 846 u32 revision; 847 848 enum e1000_media_type media_type; 849 850 u16 autoneg_advertised; 851 u16 autoneg_mask; 852 u16 cable_length; 853 u16 max_cable_length; 854 u16 min_cable_length; 855 856 u8 mdix; 857 858 bool disable_polarity_correction; 859 bool is_mdix; 860 bool polarity_correction; 861 bool speed_downgraded; 862 bool autoneg_wait_to_complete; 863 }; 864 865 struct e1000_nvm_info { 866 struct e1000_nvm_operations ops; 867 enum e1000_nvm_type type; 868 enum e1000_nvm_override override; 869 870 u32 flash_bank_size; 871 u32 flash_base_addr; 872 873 u16 word_size; 874 u16 delay_usec; 875 u16 address_bits; 876 u16 opcode_bits; 877 u16 page_size; 878 }; 879 880 struct e1000_bus_info { 881 enum e1000_bus_type type; 882 enum e1000_bus_speed speed; 883 enum e1000_bus_width width; 884 885 u16 func; 886 u16 pci_cmd_word; 887 }; 888 889 struct e1000_fc_info { 890 u32 high_water; /* Flow control high-water mark */ 891 u32 low_water; /* Flow control low-water mark */ 892 u16 pause_time; /* Flow control pause timer */ 893 u16 refresh_time; /* Flow control refresh timer */ 894 bool send_xon; /* Flow control send XON */ 895 bool strict_ieee; /* Strict IEEE mode */ 896 enum e1000_fc_mode current_mode; /* FC mode in effect */ 897 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 898 }; 899 900 struct e1000_mbx_operations { 901 s32 (*init_params)(struct e1000_hw *hw); 902 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 903 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 904 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 905 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 906 s32 (*check_for_msg)(struct e1000_hw *, u16); 907 s32 (*check_for_ack)(struct e1000_hw *, u16); 908 s32 (*check_for_rst)(struct e1000_hw *, u16); 909 }; 910 911 struct e1000_mbx_stats { 912 u32 msgs_tx; 913 u32 msgs_rx; 914 915 u32 acks; 916 u32 reqs; 917 u32 rsts; 918 }; 919 920 struct e1000_mbx_info { 921 struct e1000_mbx_operations ops; 922 struct e1000_mbx_stats stats; 923 u32 timeout; 924 u32 usec_delay; 925 u16 size; 926 }; 927 928 struct e1000_dev_spec_82541 { 929 enum e1000_dsp_config dsp_config; 930 enum e1000_ffe_config ffe_config; 931 u16 spd_default; 932 bool phy_init_script; 933 }; 934 935 struct e1000_dev_spec_82542 { 936 bool dma_fairness; 937 }; 938 939 struct e1000_dev_spec_82543 { 940 u32 tbi_compatibility; 941 bool dma_fairness; 942 bool init_phy_disabled; 943 }; 944 945 struct e1000_dev_spec_82571 { 946 bool laa_is_present; 947 u32 smb_counter; 948 }; 949 950 struct e1000_dev_spec_80003es2lan { 951 bool mdic_wa_enable; 952 }; 953 954 struct e1000_shadow_ram { 955 u16 value; 956 bool modified; 957 }; 958 959 #define E1000_SHADOW_RAM_WORDS 2048 960 961 /* I218 PHY Ultra Low Power (ULP) states */ 962 enum e1000_ulp_state { 963 e1000_ulp_state_unknown, 964 e1000_ulp_state_off, 965 e1000_ulp_state_on, 966 }; 967 968 struct e1000_dev_spec_ich8lan { 969 bool kmrn_lock_loss_workaround_enabled; 970 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 971 bool nvm_k1_enabled; 972 bool disable_k1_off; 973 bool eee_disable; 974 u16 eee_lp_ability; 975 enum e1000_ulp_state ulp_state; 976 bool ulp_capability_disabled; 977 bool during_suspend_flow; 978 bool during_dpg_exit; 979 }; 980 981 struct e1000_dev_spec_82575 { 982 bool sgmii_active; 983 bool global_device_reset; 984 bool eee_disable; 985 bool module_plugged; 986 bool clear_semaphore_once; 987 u32 mtu; 988 struct sfp_e1000_flags eth_flags; 989 u8 media_port; 990 bool media_changed; 991 }; 992 993 struct e1000_dev_spec_vf { 994 u32 vf_number; 995 u32 v2p_mailbox; 996 }; 997 998 struct e1000_hw { 999 void *back; 1000 1001 u8 *hw_addr; 1002 u8 *flash_address; 1003 unsigned long io_base; 1004 1005 struct e1000_mac_info mac; 1006 struct e1000_fc_info fc; 1007 struct e1000_phy_info phy; 1008 struct e1000_nvm_info nvm; 1009 struct e1000_bus_info bus; 1010 struct e1000_mbx_info mbx; 1011 struct e1000_host_mng_dhcp_cookie mng_cookie; 1012 1013 union { 1014 struct e1000_dev_spec_82541 _82541; 1015 struct e1000_dev_spec_82542 _82542; 1016 struct e1000_dev_spec_82543 _82543; 1017 struct e1000_dev_spec_82571 _82571; 1018 struct e1000_dev_spec_80003es2lan _80003es2lan; 1019 struct e1000_dev_spec_ich8lan ich8lan; 1020 struct e1000_dev_spec_82575 _82575; 1021 struct e1000_dev_spec_vf vf; 1022 } dev_spec; 1023 1024 u16 device_id; 1025 u16 subsystem_vendor_id; 1026 u16 subsystem_device_id; 1027 u16 vendor_id; 1028 1029 u8 revision_id; 1030 }; 1031 1032 #include "e1000_82541.h" 1033 #include "e1000_82543.h" 1034 #include "e1000_82571.h" 1035 #include "e1000_80003es2lan.h" 1036 #include "e1000_ich8lan.h" 1037 #include "e1000_82575.h" 1038 #include "e1000_i210.h" 1039 1040 /* These functions must be implemented by drivers */ 1041 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1042 void e1000_pci_set_mwi(struct e1000_hw *hw); 1043 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1044 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1045 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1046 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1047 1048 #endif 1049