xref: /freebsd/sys/dev/e1000/e1000_hw.h (revision 396c556d77189a5c474d35cec6f44a762e310b7d)
1 /******************************************************************************
2   SPDX-License-Identifier: BSD-3-Clause
3 
4   Copyright (c) 2001-2015, Intel Corporation
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6 
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11       this list of conditions and the following disclaimer.
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13    2. Redistributions in binary form must reproduce the above copyright
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33 ******************************************************************************/
34 /*$FreeBSD$*/
35 
36 #ifndef _E1000_HW_H_
37 #define _E1000_HW_H_
38 
39 #include "e1000_osdep.h"
40 #include "e1000_regs.h"
41 #include "e1000_defines.h"
42 
43 struct e1000_hw;
44 
45 #define E1000_DEV_ID_82542			0x1000
46 #define E1000_DEV_ID_82543GC_FIBER		0x1001
47 #define E1000_DEV_ID_82543GC_COPPER		0x1004
48 #define E1000_DEV_ID_82544EI_COPPER		0x1008
49 #define E1000_DEV_ID_82544EI_FIBER		0x1009
50 #define E1000_DEV_ID_82544GC_COPPER		0x100C
51 #define E1000_DEV_ID_82544GC_LOM		0x100D
52 #define E1000_DEV_ID_82540EM			0x100E
53 #define E1000_DEV_ID_82540EM_LOM		0x1015
54 #define E1000_DEV_ID_82540EP_LOM		0x1016
55 #define E1000_DEV_ID_82540EP			0x1017
56 #define E1000_DEV_ID_82540EP_LP			0x101E
57 #define E1000_DEV_ID_82545EM_COPPER		0x100F
58 #define E1000_DEV_ID_82545EM_FIBER		0x1011
59 #define E1000_DEV_ID_82545GM_COPPER		0x1026
60 #define E1000_DEV_ID_82545GM_FIBER		0x1027
61 #define E1000_DEV_ID_82545GM_SERDES		0x1028
62 #define E1000_DEV_ID_82546EB_COPPER		0x1010
63 #define E1000_DEV_ID_82546EB_FIBER		0x1012
64 #define E1000_DEV_ID_82546EB_QUAD_COPPER	0x101D
65 #define E1000_DEV_ID_82546GB_COPPER		0x1079
66 #define E1000_DEV_ID_82546GB_FIBER		0x107A
67 #define E1000_DEV_ID_82546GB_SERDES		0x107B
68 #define E1000_DEV_ID_82546GB_PCIE		0x108A
69 #define E1000_DEV_ID_82546GB_QUAD_COPPER	0x1099
70 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3	0x10B5
71 #define E1000_DEV_ID_82541EI			0x1013
72 #define E1000_DEV_ID_82541EI_MOBILE		0x1018
73 #define E1000_DEV_ID_82541ER_LOM		0x1014
74 #define E1000_DEV_ID_82541ER			0x1078
75 #define E1000_DEV_ID_82541GI			0x1076
76 #define E1000_DEV_ID_82541GI_LF			0x107C
77 #define E1000_DEV_ID_82541GI_MOBILE		0x1077
78 #define E1000_DEV_ID_82547EI			0x1019
79 #define E1000_DEV_ID_82547EI_MOBILE		0x101A
80 #define E1000_DEV_ID_82547GI			0x1075
81 #define E1000_DEV_ID_82571EB_COPPER		0x105E
82 #define E1000_DEV_ID_82571EB_FIBER		0x105F
83 #define E1000_DEV_ID_82571EB_SERDES		0x1060
84 #define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
85 #define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
86 #define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
87 #define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
88 #define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
90 #define E1000_DEV_ID_82572EI_COPPER		0x107D
91 #define E1000_DEV_ID_82572EI_FIBER		0x107E
92 #define E1000_DEV_ID_82572EI_SERDES		0x107F
93 #define E1000_DEV_ID_82572EI			0x10B9
94 #define E1000_DEV_ID_82573E			0x108B
95 #define E1000_DEV_ID_82573E_IAMT		0x108C
96 #define E1000_DEV_ID_82573L			0x109A
97 #define E1000_DEV_ID_82574L			0x10D3
98 #define E1000_DEV_ID_82574LA			0x10F6
99 #define E1000_DEV_ID_82583V			0x150C
100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
104 #define E1000_DEV_ID_ICH8_82567V_3		0x1501
105 #define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
106 #define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
107 #define E1000_DEV_ID_ICH8_IGP_C			0x104B
108 #define E1000_DEV_ID_ICH8_IFE			0x104C
109 #define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
110 #define E1000_DEV_ID_ICH8_IFE_G			0x10C5
111 #define E1000_DEV_ID_ICH8_IGP_M			0x104D
112 #define E1000_DEV_ID_ICH9_IGP_M			0x10BF
113 #define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
114 #define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
115 #define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
116 #define E1000_DEV_ID_ICH9_BM			0x10E5
117 #define E1000_DEV_ID_ICH9_IGP_C			0x294C
118 #define E1000_DEV_ID_ICH9_IFE			0x10C0
119 #define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
120 #define E1000_DEV_ID_ICH9_IFE_G			0x10C2
121 #define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
122 #define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
123 #define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
124 #define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
125 #define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
126 #define E1000_DEV_ID_ICH10_D_BM_V		0x1525
127 #define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
128 #define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
129 #define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
130 #define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
131 #define E1000_DEV_ID_PCH2_LV_LM			0x1502
132 #define E1000_DEV_ID_PCH2_LV_V			0x1503
133 #define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A
134 #define E1000_DEV_ID_PCH_LPT_I217_V		0x153B
135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A
136 #define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559
137 #define E1000_DEV_ID_PCH_I218_LM2		0x15A0
138 #define E1000_DEV_ID_PCH_I218_V2		0x15A1
139 #define E1000_DEV_ID_PCH_I218_LM3		0x15A2 /* Wildcat Point PCH */
140 #define E1000_DEV_ID_PCH_I218_V3		0x15A3 /* Wildcat Point PCH */
141 #define E1000_DEV_ID_PCH_SPT_I219_LM		0x156F /* Sunrise Point PCH */
142 #define E1000_DEV_ID_PCH_SPT_I219_V		0x1570 /* Sunrise Point PCH */
143 #define E1000_DEV_ID_PCH_SPT_I219_LM2		0x15B7 /* Sunrise Point-H PCH */
144 #define E1000_DEV_ID_PCH_SPT_I219_V2		0x15B8 /* Sunrise Point-H PCH */
145 #define E1000_DEV_ID_PCH_LBG_I219_LM3		0x15B9 /* LEWISBURG PCH */
146 #define E1000_DEV_ID_PCH_SPT_I219_LM4		0x15D7
147 #define E1000_DEV_ID_PCH_SPT_I219_V4		0x15D8
148 #define E1000_DEV_ID_PCH_SPT_I219_LM5		0x15E3
149 #define E1000_DEV_ID_PCH_SPT_I219_V5		0x15D6
150 #define E1000_DEV_ID_82576			0x10C9
151 #define E1000_DEV_ID_82576_FIBER		0x10E6
152 #define E1000_DEV_ID_82576_SERDES		0x10E7
153 #define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
154 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526
155 #define E1000_DEV_ID_82576_NS			0x150A
156 #define E1000_DEV_ID_82576_NS_SERDES		0x1518
157 #define E1000_DEV_ID_82576_SERDES_QUAD		0x150D
158 #define E1000_DEV_ID_82576_VF			0x10CA
159 #define E1000_DEV_ID_82576_VF_HV		0x152D
160 #define E1000_DEV_ID_I350_VF			0x1520
161 #define E1000_DEV_ID_I350_VF_HV			0x152F
162 #define E1000_DEV_ID_82575EB_COPPER		0x10A7
163 #define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
164 #define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
165 #define E1000_DEV_ID_82580_COPPER		0x150E
166 #define E1000_DEV_ID_82580_FIBER		0x150F
167 #define E1000_DEV_ID_82580_SERDES		0x1510
168 #define E1000_DEV_ID_82580_SGMII		0x1511
169 #define E1000_DEV_ID_82580_COPPER_DUAL		0x1516
170 #define E1000_DEV_ID_82580_QUAD_FIBER		0x1527
171 #define E1000_DEV_ID_I350_COPPER		0x1521
172 #define E1000_DEV_ID_I350_FIBER			0x1522
173 #define E1000_DEV_ID_I350_SERDES		0x1523
174 #define E1000_DEV_ID_I350_SGMII			0x1524
175 #define E1000_DEV_ID_I350_DA4			0x1546
176 #define E1000_DEV_ID_I210_COPPER		0x1533
177 #define E1000_DEV_ID_I210_COPPER_OEM1		0x1534
178 #define E1000_DEV_ID_I210_COPPER_IT		0x1535
179 #define E1000_DEV_ID_I210_FIBER			0x1536
180 #define E1000_DEV_ID_I210_SERDES		0x1537
181 #define E1000_DEV_ID_I210_SGMII			0x1538
182 #define E1000_DEV_ID_I210_COPPER_FLASHLESS	0x157B
183 #define E1000_DEV_ID_I210_SERDES_FLASHLESS	0x157C
184 #define E1000_DEV_ID_I211_COPPER		0x1539
185 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS	0x1F40
186 #define E1000_DEV_ID_I354_SGMII			0x1F41
187 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS	0x1F45
188 #define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
189 #define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
190 #define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
191 #define E1000_DEV_ID_DH89XXCC_SFP		0x0440
192 
193 #define E1000_REVISION_0	0
194 #define E1000_REVISION_1	1
195 #define E1000_REVISION_2	2
196 #define E1000_REVISION_3	3
197 #define E1000_REVISION_4	4
198 
199 #define E1000_FUNC_0		0
200 #define E1000_FUNC_1		1
201 #define E1000_FUNC_2		2
202 #define E1000_FUNC_3		3
203 
204 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
205 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3
206 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2	6
207 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3	9
208 
209 enum e1000_mac_type {
210 	e1000_undefined = 0,
211 	e1000_82542,
212 	e1000_82543,
213 	e1000_82544,
214 	e1000_82540,
215 	e1000_82545,
216 	e1000_82545_rev_3,
217 	e1000_82546,
218 	e1000_82546_rev_3,
219 	e1000_82541,
220 	e1000_82541_rev_2,
221 	e1000_82547,
222 	e1000_82547_rev_2,
223 	e1000_82571,
224 	e1000_82572,
225 	e1000_82573,
226 	e1000_82574,
227 	e1000_82583,
228 	e1000_80003es2lan,
229 	e1000_ich8lan,
230 	e1000_ich9lan,
231 	e1000_ich10lan,
232 	e1000_pchlan,
233 	e1000_pch2lan,
234 	e1000_pch_lpt,
235 	e1000_pch_spt,
236 	e1000_82575,
237 	e1000_82576,
238 	e1000_82580,
239 	e1000_i350,
240 	e1000_i354,
241 	e1000_i210,
242 	e1000_i211,
243 	e1000_vfadapt,
244 	e1000_vfadapt_i350,
245 	e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
246 };
247 
248 enum e1000_media_type {
249 	e1000_media_type_unknown = 0,
250 	e1000_media_type_copper = 1,
251 	e1000_media_type_fiber = 2,
252 	e1000_media_type_internal_serdes = 3,
253 	e1000_num_media_types
254 };
255 
256 enum e1000_nvm_type {
257 	e1000_nvm_unknown = 0,
258 	e1000_nvm_none,
259 	e1000_nvm_eeprom_spi,
260 	e1000_nvm_eeprom_microwire,
261 	e1000_nvm_flash_hw,
262 	e1000_nvm_invm,
263 	e1000_nvm_flash_sw
264 };
265 
266 enum e1000_nvm_override {
267 	e1000_nvm_override_none = 0,
268 	e1000_nvm_override_spi_small,
269 	e1000_nvm_override_spi_large,
270 	e1000_nvm_override_microwire_small,
271 	e1000_nvm_override_microwire_large
272 };
273 
274 enum e1000_phy_type {
275 	e1000_phy_unknown = 0,
276 	e1000_phy_none,
277 	e1000_phy_m88,
278 	e1000_phy_igp,
279 	e1000_phy_igp_2,
280 	e1000_phy_gg82563,
281 	e1000_phy_igp_3,
282 	e1000_phy_ife,
283 	e1000_phy_bm,
284 	e1000_phy_82578,
285 	e1000_phy_82577,
286 	e1000_phy_82579,
287 	e1000_phy_i217,
288 	e1000_phy_82580,
289 	e1000_phy_vf,
290 	e1000_phy_i210,
291 };
292 
293 enum e1000_bus_type {
294 	e1000_bus_type_unknown = 0,
295 	e1000_bus_type_pci,
296 	e1000_bus_type_pcix,
297 	e1000_bus_type_pci_express,
298 	e1000_bus_type_reserved
299 };
300 
301 enum e1000_bus_speed {
302 	e1000_bus_speed_unknown = 0,
303 	e1000_bus_speed_33,
304 	e1000_bus_speed_66,
305 	e1000_bus_speed_100,
306 	e1000_bus_speed_120,
307 	e1000_bus_speed_133,
308 	e1000_bus_speed_2500,
309 	e1000_bus_speed_5000,
310 	e1000_bus_speed_reserved
311 };
312 
313 enum e1000_bus_width {
314 	e1000_bus_width_unknown = 0,
315 	e1000_bus_width_pcie_x1,
316 	e1000_bus_width_pcie_x2,
317 	e1000_bus_width_pcie_x4 = 4,
318 	e1000_bus_width_pcie_x8 = 8,
319 	e1000_bus_width_32,
320 	e1000_bus_width_64,
321 	e1000_bus_width_reserved
322 };
323 
324 enum e1000_1000t_rx_status {
325 	e1000_1000t_rx_status_not_ok = 0,
326 	e1000_1000t_rx_status_ok,
327 	e1000_1000t_rx_status_undefined = 0xFF
328 };
329 
330 enum e1000_rev_polarity {
331 	e1000_rev_polarity_normal = 0,
332 	e1000_rev_polarity_reversed,
333 	e1000_rev_polarity_undefined = 0xFF
334 };
335 
336 enum e1000_fc_mode {
337 	e1000_fc_none = 0,
338 	e1000_fc_rx_pause,
339 	e1000_fc_tx_pause,
340 	e1000_fc_full,
341 	e1000_fc_default = 0xFF
342 };
343 
344 enum e1000_ffe_config {
345 	e1000_ffe_config_enabled = 0,
346 	e1000_ffe_config_active,
347 	e1000_ffe_config_blocked
348 };
349 
350 enum e1000_dsp_config {
351 	e1000_dsp_config_disabled = 0,
352 	e1000_dsp_config_enabled,
353 	e1000_dsp_config_activated,
354 	e1000_dsp_config_undefined = 0xFF
355 };
356 
357 enum e1000_ms_type {
358 	e1000_ms_hw_default = 0,
359 	e1000_ms_force_master,
360 	e1000_ms_force_slave,
361 	e1000_ms_auto
362 };
363 
364 enum e1000_smart_speed {
365 	e1000_smart_speed_default = 0,
366 	e1000_smart_speed_on,
367 	e1000_smart_speed_off
368 };
369 
370 enum e1000_serdes_link_state {
371 	e1000_serdes_link_down = 0,
372 	e1000_serdes_link_autoneg_progress,
373 	e1000_serdes_link_autoneg_complete,
374 	e1000_serdes_link_forced_up
375 };
376 
377 #define __le16 u16
378 #define __le32 u32
379 #define __le64 u64
380 /* Receive Descriptor */
381 struct e1000_rx_desc {
382 	__le64 buffer_addr; /* Address of the descriptor's data buffer */
383 	__le16 length;      /* Length of data DMAed into data buffer */
384 	__le16 csum; /* Packet checksum */
385 	u8  status;  /* Descriptor status */
386 	u8  errors;  /* Descriptor Errors */
387 	__le16 special;
388 };
389 
390 /* Receive Descriptor - Extended */
391 union e1000_rx_desc_extended {
392 	struct {
393 		__le64 buffer_addr;
394 		__le64 reserved;
395 	} read;
396 	struct {
397 		struct {
398 			__le32 mrq; /* Multiple Rx Queues */
399 			union {
400 				__le32 rss; /* RSS Hash */
401 				struct {
402 					__le16 ip_id;  /* IP id */
403 					__le16 csum;   /* Packet Checksum */
404 				} csum_ip;
405 			} hi_dword;
406 		} lower;
407 		struct {
408 			__le32 status_error;  /* ext status/error */
409 			__le16 length;
410 			__le16 vlan; /* VLAN tag */
411 		} upper;
412 	} wb;  /* writeback */
413 };
414 
415 #define MAX_PS_BUFFERS 4
416 
417 /* Number of packet split data buffers (not including the header buffer) */
418 #define PS_PAGE_BUFFERS	(MAX_PS_BUFFERS - 1)
419 
420 /* Receive Descriptor - Packet Split */
421 union e1000_rx_desc_packet_split {
422 	struct {
423 		/* one buffer for protocol header(s), three data buffers */
424 		__le64 buffer_addr[MAX_PS_BUFFERS];
425 	} read;
426 	struct {
427 		struct {
428 			__le32 mrq;  /* Multiple Rx Queues */
429 			union {
430 				__le32 rss; /* RSS Hash */
431 				struct {
432 					__le16 ip_id;    /* IP id */
433 					__le16 csum;     /* Packet Checksum */
434 				} csum_ip;
435 			} hi_dword;
436 		} lower;
437 		struct {
438 			__le32 status_error;  /* ext status/error */
439 			__le16 length0;  /* length of buffer 0 */
440 			__le16 vlan;  /* VLAN tag */
441 		} middle;
442 		struct {
443 			__le16 header_status;
444 			/* length of buffers 1-3 */
445 			__le16 length[PS_PAGE_BUFFERS];
446 		} upper;
447 		__le64 reserved;
448 	} wb; /* writeback */
449 };
450 
451 /* Transmit Descriptor */
452 struct e1000_tx_desc {
453 	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
454 	union {
455 		__le32 data;
456 		struct {
457 			__le16 length;  /* Data buffer length */
458 			u8 cso;  /* Checksum offset */
459 			u8 cmd;  /* Descriptor control */
460 		} flags;
461 	} lower;
462 	union {
463 		__le32 data;
464 		struct {
465 			u8 status; /* Descriptor status */
466 			u8 css;  /* Checksum start */
467 			__le16 special;
468 		} fields;
469 	} upper;
470 };
471 
472 /* Offload Context Descriptor */
473 struct e1000_context_desc {
474 	union {
475 		__le32 ip_config;
476 		struct {
477 			u8 ipcss;  /* IP checksum start */
478 			u8 ipcso;  /* IP checksum offset */
479 			__le16 ipcse;  /* IP checksum end */
480 		} ip_fields;
481 	} lower_setup;
482 	union {
483 		__le32 tcp_config;
484 		struct {
485 			u8 tucss;  /* TCP checksum start */
486 			u8 tucso;  /* TCP checksum offset */
487 			__le16 tucse;  /* TCP checksum end */
488 		} tcp_fields;
489 	} upper_setup;
490 	__le32 cmd_and_length;
491 	union {
492 		__le32 data;
493 		struct {
494 			u8 status;  /* Descriptor status */
495 			u8 hdr_len;  /* Header length */
496 			__le16 mss;  /* Maximum segment size */
497 		} fields;
498 	} tcp_seg_setup;
499 };
500 
501 /* Offload data descriptor */
502 struct e1000_data_desc {
503 	__le64 buffer_addr;  /* Address of the descriptor's buffer address */
504 	union {
505 		__le32 data;
506 		struct {
507 			__le16 length;  /* Data buffer length */
508 			u8 typ_len_ext;
509 			u8 cmd;
510 		} flags;
511 	} lower;
512 	union {
513 		__le32 data;
514 		struct {
515 			u8 status;  /* Descriptor status */
516 			u8 popts;  /* Packet Options */
517 			__le16 special;
518 		} fields;
519 	} upper;
520 };
521 
522 /* Statistics counters collected by the MAC */
523 struct e1000_hw_stats {
524 	u64 crcerrs;
525 	u64 algnerrc;
526 	u64 symerrs;
527 	u64 rxerrc;
528 	u64 mpc;
529 	u64 scc;
530 	u64 ecol;
531 	u64 mcc;
532 	u64 latecol;
533 	u64 colc;
534 	u64 dc;
535 	u64 tncrs;
536 	u64 sec;
537 	u64 cexterr;
538 	u64 rlec;
539 	u64 xonrxc;
540 	u64 xontxc;
541 	u64 xoffrxc;
542 	u64 xofftxc;
543 	u64 fcruc;
544 	u64 prc64;
545 	u64 prc127;
546 	u64 prc255;
547 	u64 prc511;
548 	u64 prc1023;
549 	u64 prc1522;
550 	u64 gprc;
551 	u64 bprc;
552 	u64 mprc;
553 	u64 gptc;
554 	u64 gorc;
555 	u64 gotc;
556 	u64 rnbc;
557 	u64 ruc;
558 	u64 rfc;
559 	u64 roc;
560 	u64 rjc;
561 	u64 mgprc;
562 	u64 mgpdc;
563 	u64 mgptc;
564 	u64 tor;
565 	u64 tot;
566 	u64 tpr;
567 	u64 tpt;
568 	u64 ptc64;
569 	u64 ptc127;
570 	u64 ptc255;
571 	u64 ptc511;
572 	u64 ptc1023;
573 	u64 ptc1522;
574 	u64 mptc;
575 	u64 bptc;
576 	u64 tsctc;
577 	u64 tsctfc;
578 	u64 iac;
579 	u64 icrxptc;
580 	u64 icrxatc;
581 	u64 ictxptc;
582 	u64 ictxatc;
583 	u64 ictxqec;
584 	u64 ictxqmtc;
585 	u64 icrxdmtc;
586 	u64 icrxoc;
587 	u64 cbtmpc;
588 	u64 htdpmc;
589 	u64 cbrdpc;
590 	u64 cbrmpc;
591 	u64 rpthc;
592 	u64 hgptc;
593 	u64 htcbdpc;
594 	u64 hgorc;
595 	u64 hgotc;
596 	u64 lenerrs;
597 	u64 scvpc;
598 	u64 hrmpc;
599 	u64 doosync;
600 	u64 o2bgptc;
601 	u64 o2bspc;
602 	u64 b2ospc;
603 	u64 b2ogprc;
604 };
605 
606 struct e1000_vf_stats {
607 	u64 base_gprc;
608 	u64 base_gptc;
609 	u64 base_gorc;
610 	u64 base_gotc;
611 	u64 base_mprc;
612 	u64 base_gotlbc;
613 	u64 base_gptlbc;
614 	u64 base_gorlbc;
615 	u64 base_gprlbc;
616 
617 	u32 last_gprc;
618 	u32 last_gptc;
619 	u32 last_gorc;
620 	u32 last_gotc;
621 	u32 last_mprc;
622 	u32 last_gotlbc;
623 	u32 last_gptlbc;
624 	u32 last_gorlbc;
625 	u32 last_gprlbc;
626 
627 	u64 gprc;
628 	u64 gptc;
629 	u64 gorc;
630 	u64 gotc;
631 	u64 mprc;
632 	u64 gotlbc;
633 	u64 gptlbc;
634 	u64 gorlbc;
635 	u64 gprlbc;
636 };
637 
638 struct e1000_phy_stats {
639 	u32 idle_errors;
640 	u32 receive_errors;
641 };
642 
643 struct e1000_host_mng_dhcp_cookie {
644 	u32 signature;
645 	u8  status;
646 	u8  reserved0;
647 	u16 vlan_id;
648 	u32 reserved1;
649 	u16 reserved2;
650 	u8  reserved3;
651 	u8  checksum;
652 };
653 
654 /* Host Interface "Rev 1" */
655 struct e1000_host_command_header {
656 	u8 command_id;
657 	u8 command_length;
658 	u8 command_options;
659 	u8 checksum;
660 };
661 
662 #define E1000_HI_MAX_DATA_LENGTH	252
663 struct e1000_host_command_info {
664 	struct e1000_host_command_header command_header;
665 	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
666 };
667 
668 /* Host Interface "Rev 2" */
669 struct e1000_host_mng_command_header {
670 	u8  command_id;
671 	u8  checksum;
672 	u16 reserved1;
673 	u16 reserved2;
674 	u16 command_length;
675 };
676 
677 #define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8
678 struct e1000_host_mng_command_info {
679 	struct e1000_host_mng_command_header command_header;
680 	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
681 };
682 
683 #include "e1000_mac.h"
684 #include "e1000_phy.h"
685 #include "e1000_nvm.h"
686 #include "e1000_manage.h"
687 #include "e1000_mbx.h"
688 
689 /* Function pointers for the MAC. */
690 struct e1000_mac_operations {
691 	s32  (*init_params)(struct e1000_hw *);
692 	s32  (*id_led_init)(struct e1000_hw *);
693 	s32  (*blink_led)(struct e1000_hw *);
694 	bool (*check_mng_mode)(struct e1000_hw *);
695 	s32  (*check_for_link)(struct e1000_hw *);
696 	s32  (*cleanup_led)(struct e1000_hw *);
697 	void (*clear_hw_cntrs)(struct e1000_hw *);
698 	void (*clear_vfta)(struct e1000_hw *);
699 	s32  (*get_bus_info)(struct e1000_hw *);
700 	void (*set_lan_id)(struct e1000_hw *);
701 	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
702 	s32  (*led_on)(struct e1000_hw *);
703 	s32  (*led_off)(struct e1000_hw *);
704 	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
705 	s32  (*reset_hw)(struct e1000_hw *);
706 	s32  (*init_hw)(struct e1000_hw *);
707 	void (*shutdown_serdes)(struct e1000_hw *);
708 	void (*power_up_serdes)(struct e1000_hw *);
709 	s32  (*setup_link)(struct e1000_hw *);
710 	s32  (*setup_physical_interface)(struct e1000_hw *);
711 	s32  (*setup_led)(struct e1000_hw *);
712 	void (*write_vfta)(struct e1000_hw *, u32, u32);
713 	void (*config_collision_dist)(struct e1000_hw *);
714 	int  (*rar_set)(struct e1000_hw *, u8*, u32);
715 	s32  (*read_mac_addr)(struct e1000_hw *);
716 	s32  (*validate_mdi_setting)(struct e1000_hw *);
717 	s32  (*set_obff_timer)(struct e1000_hw *, u32);
718 	s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
719 	void (*release_swfw_sync)(struct e1000_hw *, u16);
720 };
721 
722 /* When to use various PHY register access functions:
723  *
724  *                 Func   Caller
725  *   Function      Does   Does    When to use
726  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
727  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
728  *   X_reg_locked  P,A    L       for multiple accesses of different regs
729  *                                on different pages
730  *   X_reg_page    A      L,P     for multiple accesses of different regs
731  *                                on the same page
732  *
733  * Where X=[read|write], L=locking, P=sets page, A=register access
734  *
735  */
736 struct e1000_phy_operations {
737 	s32  (*init_params)(struct e1000_hw *);
738 	s32  (*acquire)(struct e1000_hw *);
739 	s32  (*cfg_on_link_up)(struct e1000_hw *);
740 	s32  (*check_polarity)(struct e1000_hw *);
741 	s32  (*check_reset_block)(struct e1000_hw *);
742 	s32  (*commit)(struct e1000_hw *);
743 	s32  (*force_speed_duplex)(struct e1000_hw *);
744 	s32  (*get_cfg_done)(struct e1000_hw *hw);
745 	s32  (*get_cable_length)(struct e1000_hw *);
746 	s32  (*get_info)(struct e1000_hw *);
747 	s32  (*set_page)(struct e1000_hw *, u16);
748 	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
749 	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
750 	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
751 	void (*release)(struct e1000_hw *);
752 	s32  (*reset)(struct e1000_hw *);
753 	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
754 	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
755 	s32  (*write_reg)(struct e1000_hw *, u32, u16);
756 	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
757 	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
758 	void (*power_up)(struct e1000_hw *);
759 	void (*power_down)(struct e1000_hw *);
760 	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
761 	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
762 };
763 
764 /* Function pointers for the NVM. */
765 struct e1000_nvm_operations {
766 	s32  (*init_params)(struct e1000_hw *);
767 	s32  (*acquire)(struct e1000_hw *);
768 	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
769 	void (*release)(struct e1000_hw *);
770 	void (*reload)(struct e1000_hw *);
771 	s32  (*update)(struct e1000_hw *);
772 	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
773 	s32  (*validate)(struct e1000_hw *);
774 	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
775 };
776 
777 struct e1000_mac_info {
778 	struct e1000_mac_operations ops;
779 	u8 addr[ETH_ADDR_LEN];
780 	u8 perm_addr[ETH_ADDR_LEN];
781 
782 	enum e1000_mac_type type;
783 
784 	u32 collision_delta;
785 	u32 ledctl_default;
786 	u32 ledctl_mode1;
787 	u32 ledctl_mode2;
788 	u32 mc_filter_type;
789 	u32 tx_packet_delta;
790 	u32 txcw;
791 
792 	u16 current_ifs_val;
793 	u16 ifs_max_val;
794 	u16 ifs_min_val;
795 	u16 ifs_ratio;
796 	u16 ifs_step_size;
797 	u16 mta_reg_count;
798 	u16 uta_reg_count;
799 
800 	/* Maximum size of the MTA register table in all supported adapters */
801 #define MAX_MTA_REG 128
802 	u32 mta_shadow[MAX_MTA_REG];
803 	u16 rar_entry_count;
804 
805 	u8  forced_speed_duplex;
806 
807 	bool adaptive_ifs;
808 	bool has_fwsm;
809 	bool arc_subsystem_valid;
810 	bool asf_firmware_present;
811 	bool autoneg;
812 	bool autoneg_failed;
813 	bool get_link_status;
814 	bool in_ifs_mode;
815 	bool report_tx_early;
816 	enum e1000_serdes_link_state serdes_link_state;
817 	bool serdes_has_link;
818 	bool tx_pkt_filtering;
819 	u32  max_frame_size;
820 };
821 
822 struct e1000_phy_info {
823 	struct e1000_phy_operations ops;
824 	enum e1000_phy_type type;
825 
826 	enum e1000_1000t_rx_status local_rx;
827 	enum e1000_1000t_rx_status remote_rx;
828 	enum e1000_ms_type ms_type;
829 	enum e1000_ms_type original_ms_type;
830 	enum e1000_rev_polarity cable_polarity;
831 	enum e1000_smart_speed smart_speed;
832 
833 	u32 addr;
834 	u32 id;
835 	u32 reset_delay_us; /* in usec */
836 	u32 revision;
837 
838 	enum e1000_media_type media_type;
839 
840 	u16 autoneg_advertised;
841 	u16 autoneg_mask;
842 	u16 cable_length;
843 	u16 max_cable_length;
844 	u16 min_cable_length;
845 
846 	u8 mdix;
847 
848 	bool disable_polarity_correction;
849 	bool is_mdix;
850 	bool polarity_correction;
851 	bool speed_downgraded;
852 	bool autoneg_wait_to_complete;
853 };
854 
855 struct e1000_nvm_info {
856 	struct e1000_nvm_operations ops;
857 	enum e1000_nvm_type type;
858 	enum e1000_nvm_override override;
859 
860 	u32 flash_bank_size;
861 	u32 flash_base_addr;
862 
863 	u16 word_size;
864 	u16 delay_usec;
865 	u16 address_bits;
866 	u16 opcode_bits;
867 	u16 page_size;
868 };
869 
870 struct e1000_bus_info {
871 	enum e1000_bus_type type;
872 	enum e1000_bus_speed speed;
873 	enum e1000_bus_width width;
874 
875 	u16 func;
876 	u16 pci_cmd_word;
877 };
878 
879 struct e1000_fc_info {
880 	u32 high_water;  /* Flow control high-water mark */
881 	u32 low_water;  /* Flow control low-water mark */
882 	u16 pause_time;  /* Flow control pause timer */
883 	u16 refresh_time;  /* Flow control refresh timer */
884 	bool send_xon;  /* Flow control send XON */
885 	bool strict_ieee;  /* Strict IEEE mode */
886 	enum e1000_fc_mode current_mode;  /* FC mode in effect */
887 	enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
888 };
889 
890 struct e1000_mbx_operations {
891 	s32 (*init_params)(struct e1000_hw *hw);
892 	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
893 	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
894 	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
895 	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
896 	s32 (*check_for_msg)(struct e1000_hw *, u16);
897 	s32 (*check_for_ack)(struct e1000_hw *, u16);
898 	s32 (*check_for_rst)(struct e1000_hw *, u16);
899 };
900 
901 struct e1000_mbx_stats {
902 	u32 msgs_tx;
903 	u32 msgs_rx;
904 
905 	u32 acks;
906 	u32 reqs;
907 	u32 rsts;
908 };
909 
910 struct e1000_mbx_info {
911 	struct e1000_mbx_operations ops;
912 	struct e1000_mbx_stats stats;
913 	u32 timeout;
914 	u32 usec_delay;
915 	u16 size;
916 };
917 
918 struct e1000_dev_spec_82541 {
919 	enum e1000_dsp_config dsp_config;
920 	enum e1000_ffe_config ffe_config;
921 	u16 spd_default;
922 	bool phy_init_script;
923 };
924 
925 struct e1000_dev_spec_82542 {
926 	bool dma_fairness;
927 };
928 
929 struct e1000_dev_spec_82543 {
930 	u32  tbi_compatibility;
931 	bool dma_fairness;
932 	bool init_phy_disabled;
933 };
934 
935 struct e1000_dev_spec_82571 {
936 	bool laa_is_present;
937 	u32 smb_counter;
938 	E1000_MUTEX swflag_mutex;
939 };
940 
941 struct e1000_dev_spec_80003es2lan {
942 	bool  mdic_wa_enable;
943 };
944 
945 struct e1000_shadow_ram {
946 	u16  value;
947 	bool modified;
948 };
949 
950 #define E1000_SHADOW_RAM_WORDS		2048
951 
952 /* I218 PHY Ultra Low Power (ULP) states */
953 enum e1000_ulp_state {
954 	e1000_ulp_state_unknown,
955 	e1000_ulp_state_off,
956 	e1000_ulp_state_on,
957 };
958 
959 struct e1000_dev_spec_ich8lan {
960 	bool kmrn_lock_loss_workaround_enabled;
961 	struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
962 	E1000_MUTEX nvm_mutex;
963 	E1000_MUTEX swflag_mutex;
964 	bool nvm_k1_enabled;
965 	bool disable_k1_off;
966 	bool eee_disable;
967 	u16 eee_lp_ability;
968 	enum e1000_ulp_state ulp_state;
969 	bool ulp_capability_disabled;
970 	bool during_suspend_flow;
971 	bool during_dpg_exit;
972 };
973 
974 struct e1000_dev_spec_82575 {
975 	bool sgmii_active;
976 	bool global_device_reset;
977 	bool eee_disable;
978 	bool module_plugged;
979 	bool clear_semaphore_once;
980 	u32 mtu;
981 	struct sfp_e1000_flags eth_flags;
982 	u8 media_port;
983 	bool media_changed;
984 };
985 
986 struct e1000_dev_spec_vf {
987 	u32 vf_number;
988 	u32 v2p_mailbox;
989 };
990 
991 struct e1000_hw {
992 	void *back;
993 
994 	u8 *hw_addr;
995 	u8 *flash_address;
996 	unsigned long io_base;
997 
998 	struct e1000_mac_info  mac;
999 	struct e1000_fc_info   fc;
1000 	struct e1000_phy_info  phy;
1001 	struct e1000_nvm_info  nvm;
1002 	struct e1000_bus_info  bus;
1003 	struct e1000_mbx_info mbx;
1004 	struct e1000_host_mng_dhcp_cookie mng_cookie;
1005 
1006 	union {
1007 		struct e1000_dev_spec_82541 _82541;
1008 		struct e1000_dev_spec_82542 _82542;
1009 		struct e1000_dev_spec_82543 _82543;
1010 		struct e1000_dev_spec_82571 _82571;
1011 		struct e1000_dev_spec_80003es2lan _80003es2lan;
1012 		struct e1000_dev_spec_ich8lan ich8lan;
1013 		struct e1000_dev_spec_82575 _82575;
1014 		struct e1000_dev_spec_vf vf;
1015 	} dev_spec;
1016 
1017 	u16 device_id;
1018 	u16 subsystem_vendor_id;
1019 	u16 subsystem_device_id;
1020 	u16 vendor_id;
1021 
1022 	u8  revision_id;
1023 };
1024 
1025 #include "e1000_82541.h"
1026 #include "e1000_82543.h"
1027 #include "e1000_82571.h"
1028 #include "e1000_80003es2lan.h"
1029 #include "e1000_ich8lan.h"
1030 #include "e1000_82575.h"
1031 #include "e1000_i210.h"
1032 
1033 /* These functions must be implemented by drivers */
1034 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1035 void e1000_pci_set_mwi(struct e1000_hw *hw);
1036 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1037 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1038 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1039 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1040 
1041 #endif
1042