1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82572EI_COPPER 0x107D 90 #define E1000_DEV_ID_82572EI_FIBER 0x107E 91 #define E1000_DEV_ID_82572EI_SERDES 0x107F 92 #define E1000_DEV_ID_82572EI 0x10B9 93 #define E1000_DEV_ID_82573E 0x108B 94 #define E1000_DEV_ID_82573E_IAMT 0x108C 95 #define E1000_DEV_ID_82573L 0x109A 96 #define E1000_DEV_ID_82574L 0x10D3 97 #define E1000_DEV_ID_82574LA 0x10F6 98 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 99 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 102 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 103 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 104 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 105 #define E1000_DEV_ID_ICH8_IFE 0x104C 106 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 107 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 108 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 109 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 110 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 111 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 112 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 113 #define E1000_DEV_ID_ICH9_BM 0x10E5 114 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 115 #define E1000_DEV_ID_ICH9_IFE 0x10C0 116 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 117 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 118 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 119 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 120 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 121 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 122 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 123 #define E1000_DEV_ID_82576 0x10C9 124 #define E1000_DEV_ID_82576_FIBER 0x10E6 125 #define E1000_DEV_ID_82576_SERDES 0x10E7 126 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 127 #define E1000_DEV_ID_82576_NS 0x150A 128 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 129 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 130 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 131 #define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2 132 #define E1000_REVISION_0 0 133 #define E1000_REVISION_1 1 134 #define E1000_REVISION_2 2 135 #define E1000_REVISION_3 3 136 #define E1000_REVISION_4 4 137 138 #define E1000_FUNC_0 0 139 #define E1000_FUNC_1 1 140 141 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 142 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 143 144 enum e1000_mac_type { 145 e1000_undefined = 0, 146 e1000_82542, 147 e1000_82543, 148 e1000_82544, 149 e1000_82540, 150 e1000_82545, 151 e1000_82545_rev_3, 152 e1000_82546, 153 e1000_82546_rev_3, 154 e1000_82541, 155 e1000_82541_rev_2, 156 e1000_82547, 157 e1000_82547_rev_2, 158 e1000_82571, 159 e1000_82572, 160 e1000_82573, 161 e1000_82574, 162 e1000_80003es2lan, 163 e1000_ich8lan, 164 e1000_ich9lan, 165 e1000_ich10lan, 166 e1000_82575, 167 e1000_82576, 168 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 169 }; 170 171 enum e1000_media_type { 172 e1000_media_type_unknown = 0, 173 e1000_media_type_copper = 1, 174 e1000_media_type_fiber = 2, 175 e1000_media_type_internal_serdes = 3, 176 e1000_num_media_types 177 }; 178 179 enum e1000_nvm_type { 180 e1000_nvm_unknown = 0, 181 e1000_nvm_none, 182 e1000_nvm_eeprom_spi, 183 e1000_nvm_eeprom_microwire, 184 e1000_nvm_flash_hw, 185 e1000_nvm_flash_sw 186 }; 187 188 enum e1000_nvm_override { 189 e1000_nvm_override_none = 0, 190 e1000_nvm_override_spi_small, 191 e1000_nvm_override_spi_large, 192 e1000_nvm_override_microwire_small, 193 e1000_nvm_override_microwire_large 194 }; 195 196 enum e1000_phy_type { 197 e1000_phy_unknown = 0, 198 e1000_phy_none, 199 e1000_phy_m88, 200 e1000_phy_igp, 201 e1000_phy_igp_2, 202 e1000_phy_gg82563, 203 e1000_phy_igp_3, 204 e1000_phy_ife, 205 e1000_phy_bm, 206 e1000_phy_vf, 207 }; 208 209 enum e1000_bus_type { 210 e1000_bus_type_unknown = 0, 211 e1000_bus_type_pci, 212 e1000_bus_type_pcix, 213 e1000_bus_type_pci_express, 214 e1000_bus_type_reserved 215 }; 216 217 enum e1000_bus_speed { 218 e1000_bus_speed_unknown = 0, 219 e1000_bus_speed_33, 220 e1000_bus_speed_66, 221 e1000_bus_speed_100, 222 e1000_bus_speed_120, 223 e1000_bus_speed_133, 224 e1000_bus_speed_2500, 225 e1000_bus_speed_5000, 226 e1000_bus_speed_reserved 227 }; 228 229 enum e1000_bus_width { 230 e1000_bus_width_unknown = 0, 231 e1000_bus_width_pcie_x1, 232 e1000_bus_width_pcie_x2, 233 e1000_bus_width_pcie_x4 = 4, 234 e1000_bus_width_pcie_x8 = 8, 235 e1000_bus_width_32, 236 e1000_bus_width_64, 237 e1000_bus_width_reserved 238 }; 239 240 enum e1000_1000t_rx_status { 241 e1000_1000t_rx_status_not_ok = 0, 242 e1000_1000t_rx_status_ok, 243 e1000_1000t_rx_status_undefined = 0xFF 244 }; 245 246 enum e1000_rev_polarity { 247 e1000_rev_polarity_normal = 0, 248 e1000_rev_polarity_reversed, 249 e1000_rev_polarity_undefined = 0xFF 250 }; 251 252 enum e1000_fc_mode { 253 e1000_fc_none = 0, 254 e1000_fc_rx_pause, 255 e1000_fc_tx_pause, 256 e1000_fc_full, 257 e1000_fc_default = 0xFF 258 }; 259 260 enum e1000_ffe_config { 261 e1000_ffe_config_enabled = 0, 262 e1000_ffe_config_active, 263 e1000_ffe_config_blocked 264 }; 265 266 enum e1000_dsp_config { 267 e1000_dsp_config_disabled = 0, 268 e1000_dsp_config_enabled, 269 e1000_dsp_config_activated, 270 e1000_dsp_config_undefined = 0xFF 271 }; 272 273 enum e1000_ms_type { 274 e1000_ms_hw_default = 0, 275 e1000_ms_force_master, 276 e1000_ms_force_slave, 277 e1000_ms_auto 278 }; 279 280 enum e1000_smart_speed { 281 e1000_smart_speed_default = 0, 282 e1000_smart_speed_on, 283 e1000_smart_speed_off 284 }; 285 286 enum e1000_serdes_link_state { 287 e1000_serdes_link_down = 0, 288 e1000_serdes_link_autoneg_progress, 289 e1000_serdes_link_autoneg_complete, 290 e1000_serdes_link_forced_up 291 }; 292 293 /* Receive Descriptor */ 294 struct e1000_rx_desc { 295 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 296 __le16 length; /* Length of data DMAed into data buffer */ 297 __le16 csum; /* Packet checksum */ 298 u8 status; /* Descriptor status */ 299 u8 errors; /* Descriptor Errors */ 300 __le16 special; 301 }; 302 303 /* Receive Descriptor - Extended */ 304 union e1000_rx_desc_extended { 305 struct { 306 __le64 buffer_addr; 307 __le64 reserved; 308 } read; 309 struct { 310 struct { 311 __le32 mrq; /* Multiple Rx Queues */ 312 union { 313 __le32 rss; /* RSS Hash */ 314 struct { 315 __le16 ip_id; /* IP id */ 316 __le16 csum; /* Packet Checksum */ 317 } csum_ip; 318 } hi_dword; 319 } lower; 320 struct { 321 __le32 status_error; /* ext status/error */ 322 __le16 length; 323 __le16 vlan; /* VLAN tag */ 324 } upper; 325 } wb; /* writeback */ 326 }; 327 328 #define MAX_PS_BUFFERS 4 329 /* Receive Descriptor - Packet Split */ 330 union e1000_rx_desc_packet_split { 331 struct { 332 /* one buffer for protocol header(s), three data buffers */ 333 __le64 buffer_addr[MAX_PS_BUFFERS]; 334 } read; 335 struct { 336 struct { 337 __le32 mrq; /* Multiple Rx Queues */ 338 union { 339 __le32 rss; /* RSS Hash */ 340 struct { 341 __le16 ip_id; /* IP id */ 342 __le16 csum; /* Packet Checksum */ 343 } csum_ip; 344 } hi_dword; 345 } lower; 346 struct { 347 __le32 status_error; /* ext status/error */ 348 __le16 length0; /* length of buffer 0 */ 349 __le16 vlan; /* VLAN tag */ 350 } middle; 351 struct { 352 __le16 header_status; 353 __le16 length[3]; /* length of buffers 1-3 */ 354 } upper; 355 __le64 reserved; 356 } wb; /* writeback */ 357 }; 358 359 /* Transmit Descriptor */ 360 struct e1000_tx_desc { 361 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 362 union { 363 __le32 data; 364 struct { 365 __le16 length; /* Data buffer length */ 366 u8 cso; /* Checksum offset */ 367 u8 cmd; /* Descriptor control */ 368 } flags; 369 } lower; 370 union { 371 __le32 data; 372 struct { 373 u8 status; /* Descriptor status */ 374 u8 css; /* Checksum start */ 375 __le16 special; 376 } fields; 377 } upper; 378 }; 379 380 /* Offload Context Descriptor */ 381 struct e1000_context_desc { 382 union { 383 __le32 ip_config; 384 struct { 385 u8 ipcss; /* IP checksum start */ 386 u8 ipcso; /* IP checksum offset */ 387 __le16 ipcse; /* IP checksum end */ 388 } ip_fields; 389 } lower_setup; 390 union { 391 __le32 tcp_config; 392 struct { 393 u8 tucss; /* TCP checksum start */ 394 u8 tucso; /* TCP checksum offset */ 395 __le16 tucse; /* TCP checksum end */ 396 } tcp_fields; 397 } upper_setup; 398 __le32 cmd_and_length; 399 union { 400 __le32 data; 401 struct { 402 u8 status; /* Descriptor status */ 403 u8 hdr_len; /* Header length */ 404 __le16 mss; /* Maximum segment size */ 405 } fields; 406 } tcp_seg_setup; 407 }; 408 409 /* Offload data descriptor */ 410 struct e1000_data_desc { 411 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 412 union { 413 __le32 data; 414 struct { 415 __le16 length; /* Data buffer length */ 416 u8 typ_len_ext; 417 u8 cmd; 418 } flags; 419 } lower; 420 union { 421 __le32 data; 422 struct { 423 u8 status; /* Descriptor status */ 424 u8 popts; /* Packet Options */ 425 __le16 special; 426 } fields; 427 } upper; 428 }; 429 430 /* Statistics counters collected by the MAC */ 431 struct e1000_hw_stats { 432 u64 crcerrs; 433 u64 algnerrc; 434 u64 symerrs; 435 u64 rxerrc; 436 u64 mpc; 437 u64 scc; 438 u64 ecol; 439 u64 mcc; 440 u64 latecol; 441 u64 colc; 442 u64 dc; 443 u64 tncrs; 444 u64 sec; 445 u64 cexterr; 446 u64 rlec; 447 u64 xonrxc; 448 u64 xontxc; 449 u64 xoffrxc; 450 u64 xofftxc; 451 u64 fcruc; 452 u64 prc64; 453 u64 prc127; 454 u64 prc255; 455 u64 prc511; 456 u64 prc1023; 457 u64 prc1522; 458 u64 gprc; 459 u64 bprc; 460 u64 mprc; 461 u64 gptc; 462 u64 gorc; 463 u64 gotc; 464 u64 rnbc; 465 u64 ruc; 466 u64 rfc; 467 u64 roc; 468 u64 rjc; 469 u64 mgprc; 470 u64 mgpdc; 471 u64 mgptc; 472 u64 tor; 473 u64 tot; 474 u64 tpr; 475 u64 tpt; 476 u64 ptc64; 477 u64 ptc127; 478 u64 ptc255; 479 u64 ptc511; 480 u64 ptc1023; 481 u64 ptc1522; 482 u64 mptc; 483 u64 bptc; 484 u64 tsctc; 485 u64 tsctfc; 486 u64 iac; 487 u64 icrxptc; 488 u64 icrxatc; 489 u64 ictxptc; 490 u64 ictxatc; 491 u64 ictxqec; 492 u64 ictxqmtc; 493 u64 icrxdmtc; 494 u64 icrxoc; 495 u64 cbtmpc; 496 u64 htdpmc; 497 u64 cbrdpc; 498 u64 cbrmpc; 499 u64 rpthc; 500 u64 hgptc; 501 u64 htcbdpc; 502 u64 hgorc; 503 u64 hgotc; 504 u64 lenerrs; 505 u64 scvpc; 506 u64 hrmpc; 507 u64 doosync; 508 }; 509 510 511 struct e1000_phy_stats { 512 u32 idle_errors; 513 u32 receive_errors; 514 }; 515 516 struct e1000_host_mng_dhcp_cookie { 517 u32 signature; 518 u8 status; 519 u8 reserved0; 520 u16 vlan_id; 521 u32 reserved1; 522 u16 reserved2; 523 u8 reserved3; 524 u8 checksum; 525 }; 526 527 /* Host Interface "Rev 1" */ 528 struct e1000_host_command_header { 529 u8 command_id; 530 u8 command_length; 531 u8 command_options; 532 u8 checksum; 533 }; 534 535 #define E1000_HI_MAX_DATA_LENGTH 252 536 struct e1000_host_command_info { 537 struct e1000_host_command_header command_header; 538 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 539 }; 540 541 /* Host Interface "Rev 2" */ 542 struct e1000_host_mng_command_header { 543 u8 command_id; 544 u8 checksum; 545 u16 reserved1; 546 u16 reserved2; 547 u16 command_length; 548 }; 549 550 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 551 struct e1000_host_mng_command_info { 552 struct e1000_host_mng_command_header command_header; 553 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 554 }; 555 556 #include "e1000_mac.h" 557 #include "e1000_phy.h" 558 #include "e1000_nvm.h" 559 #include "e1000_manage.h" 560 561 struct e1000_mac_operations { 562 /* Function pointers for the MAC. */ 563 s32 (*init_params)(struct e1000_hw *); 564 s32 (*id_led_init)(struct e1000_hw *); 565 s32 (*blink_led)(struct e1000_hw *); 566 s32 (*check_for_link)(struct e1000_hw *); 567 bool (*check_mng_mode)(struct e1000_hw *hw); 568 s32 (*cleanup_led)(struct e1000_hw *); 569 void (*clear_hw_cntrs)(struct e1000_hw *); 570 void (*clear_vfta)(struct e1000_hw *); 571 s32 (*get_bus_info)(struct e1000_hw *); 572 void (*set_lan_id)(struct e1000_hw *); 573 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 574 s32 (*led_on)(struct e1000_hw *); 575 s32 (*led_off)(struct e1000_hw *); 576 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 577 s32 (*reset_hw)(struct e1000_hw *); 578 s32 (*init_hw)(struct e1000_hw *); 579 void (*shutdown_serdes)(struct e1000_hw *); 580 s32 (*setup_link)(struct e1000_hw *); 581 s32 (*setup_physical_interface)(struct e1000_hw *); 582 s32 (*setup_led)(struct e1000_hw *); 583 void (*write_vfta)(struct e1000_hw *, u32, u32); 584 void (*mta_set)(struct e1000_hw *, u32); 585 void (*config_collision_dist)(struct e1000_hw *); 586 void (*rar_set)(struct e1000_hw *, u8*, u32); 587 s32 (*read_mac_addr)(struct e1000_hw *); 588 s32 (*validate_mdi_setting)(struct e1000_hw *); 589 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); 590 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 591 struct e1000_host_mng_command_header*); 592 s32 (*mng_enable_host_if)(struct e1000_hw *); 593 s32 (*wait_autoneg)(struct e1000_hw *); 594 }; 595 596 struct e1000_phy_operations { 597 s32 (*init_params)(struct e1000_hw *); 598 s32 (*acquire)(struct e1000_hw *); 599 s32 (*cfg_on_link_up)(struct e1000_hw *); 600 s32 (*check_polarity)(struct e1000_hw *); 601 s32 (*check_reset_block)(struct e1000_hw *); 602 s32 (*commit)(struct e1000_hw *); 603 s32 (*force_speed_duplex)(struct e1000_hw *); 604 s32 (*get_cfg_done)(struct e1000_hw *hw); 605 s32 (*get_cable_length)(struct e1000_hw *); 606 s32 (*get_info)(struct e1000_hw *); 607 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 608 void (*release)(struct e1000_hw *); 609 s32 (*reset)(struct e1000_hw *); 610 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 611 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 612 s32 (*write_reg)(struct e1000_hw *, u32, u16); 613 void (*power_up)(struct e1000_hw *); 614 void (*power_down)(struct e1000_hw *); 615 }; 616 617 struct e1000_nvm_operations { 618 s32 (*init_params)(struct e1000_hw *); 619 s32 (*acquire)(struct e1000_hw *); 620 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 621 void (*release)(struct e1000_hw *); 622 void (*reload)(struct e1000_hw *); 623 s32 (*update)(struct e1000_hw *); 624 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 625 s32 (*validate)(struct e1000_hw *); 626 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 627 }; 628 629 struct e1000_mac_info { 630 struct e1000_mac_operations ops; 631 u8 addr[6]; 632 u8 perm_addr[6]; 633 634 enum e1000_mac_type type; 635 636 u32 collision_delta; 637 u32 ledctl_default; 638 u32 ledctl_mode1; 639 u32 ledctl_mode2; 640 u32 mc_filter_type; 641 u32 tx_packet_delta; 642 u32 txcw; 643 644 u16 current_ifs_val; 645 u16 ifs_max_val; 646 u16 ifs_min_val; 647 u16 ifs_ratio; 648 u16 ifs_step_size; 649 u16 mta_reg_count; 650 #define MAX_MTA_REG 128 /* this must be the maximum size of the MTA register 651 * table in all supported adapters 652 */ 653 u32 mta_shadow[MAX_MTA_REG]; 654 u16 rar_entry_count; 655 656 u8 forced_speed_duplex; 657 658 bool adaptive_ifs; 659 bool arc_subsystem_valid; 660 bool asf_firmware_present; 661 bool autoneg; 662 bool autoneg_failed; 663 bool get_link_status; 664 bool in_ifs_mode; 665 bool report_tx_early; 666 enum e1000_serdes_link_state serdes_link_state; 667 bool serdes_has_link; 668 bool tx_pkt_filtering; 669 }; 670 671 struct e1000_phy_info { 672 struct e1000_phy_operations ops; 673 enum e1000_phy_type type; 674 675 enum e1000_1000t_rx_status local_rx; 676 enum e1000_1000t_rx_status remote_rx; 677 enum e1000_ms_type ms_type; 678 enum e1000_ms_type original_ms_type; 679 enum e1000_rev_polarity cable_polarity; 680 enum e1000_smart_speed smart_speed; 681 682 u32 addr; 683 u32 id; 684 u32 reset_delay_us; /* in usec */ 685 u32 revision; 686 687 enum e1000_media_type media_type; 688 689 u16 autoneg_advertised; 690 u16 autoneg_mask; 691 u16 cable_length; 692 u16 max_cable_length; 693 u16 min_cable_length; 694 695 u8 mdix; 696 697 bool disable_polarity_correction; 698 bool is_mdix; 699 bool polarity_correction; 700 bool reset_disable; 701 bool speed_downgraded; 702 bool autoneg_wait_to_complete; 703 }; 704 705 struct e1000_nvm_info { 706 struct e1000_nvm_operations ops; 707 enum e1000_nvm_type type; 708 enum e1000_nvm_override override; 709 710 u32 flash_bank_size; 711 u32 flash_base_addr; 712 713 u16 word_size; 714 u16 delay_usec; 715 u16 address_bits; 716 u16 opcode_bits; 717 u16 page_size; 718 }; 719 720 struct e1000_bus_info { 721 enum e1000_bus_type type; 722 enum e1000_bus_speed speed; 723 enum e1000_bus_width width; 724 725 u16 func; 726 u16 pci_cmd_word; 727 }; 728 729 struct e1000_fc_info { 730 u32 high_water; /* Flow control high-water mark */ 731 u32 low_water; /* Flow control low-water mark */ 732 u16 pause_time; /* Flow control pause timer */ 733 bool send_xon; /* Flow control send XON */ 734 bool strict_ieee; /* Strict IEEE mode */ 735 enum e1000_fc_mode current_mode; /* FC mode in effect */ 736 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 737 }; 738 739 struct e1000_dev_spec_82541 { 740 enum e1000_dsp_config dsp_config; 741 enum e1000_ffe_config ffe_config; 742 u16 spd_default; 743 bool phy_init_script; 744 }; 745 746 struct e1000_dev_spec_82542 { 747 bool dma_fairness; 748 }; 749 750 struct e1000_dev_spec_82543 { 751 u32 tbi_compatibility; 752 bool dma_fairness; 753 bool init_phy_disabled; 754 }; 755 756 struct e1000_dev_spec_82571 { 757 bool laa_is_present; 758 }; 759 760 struct e1000_shadow_ram { 761 u16 value; 762 bool modified; 763 }; 764 765 #define E1000_SHADOW_RAM_WORDS 2048 766 767 struct e1000_dev_spec_ich8lan { 768 bool kmrn_lock_loss_workaround_enabled; 769 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 770 }; 771 772 struct e1000_dev_spec_82575 { 773 bool sgmii_active; 774 bool global_device_reset; 775 }; 776 777 struct e1000_dev_spec_vf { 778 u32 vf_number; 779 u32 v2p_mailbox; 780 }; 781 782 783 struct e1000_hw { 784 void *back; 785 786 u8 *hw_addr; 787 u8 *flash_address; 788 unsigned long io_base; 789 790 struct e1000_mac_info mac; 791 struct e1000_fc_info fc; 792 struct e1000_phy_info phy; 793 struct e1000_nvm_info nvm; 794 struct e1000_bus_info bus; 795 struct e1000_host_mng_dhcp_cookie mng_cookie; 796 797 union { 798 struct e1000_dev_spec_82541 _82541; 799 struct e1000_dev_spec_82542 _82542; 800 struct e1000_dev_spec_82543 _82543; 801 struct e1000_dev_spec_82571 _82571; 802 struct e1000_dev_spec_ich8lan ich8lan; 803 struct e1000_dev_spec_82575 _82575; 804 struct e1000_dev_spec_vf vf; 805 } dev_spec; 806 807 u16 device_id; 808 u16 subsystem_vendor_id; 809 u16 subsystem_device_id; 810 u16 vendor_id; 811 812 u8 revision_id; 813 }; 814 815 #include "e1000_82541.h" 816 #include "e1000_82543.h" 817 #include "e1000_82571.h" 818 #include "e1000_80003es2lan.h" 819 #include "e1000_ich8lan.h" 820 #include "e1000_82575.h" 821 822 /* These functions must be implemented by drivers */ 823 void e1000_pci_clear_mwi(struct e1000_hw *hw); 824 void e1000_pci_set_mwi(struct e1000_hw *hw); 825 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 826 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 827 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 828 829 #endif 830