1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #ifndef _E1000_DEFINES_H_ 36 #define _E1000_DEFINES_H_ 37 38 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 40 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 41 42 /* Definitions for power management and wakeup registers */ 43 /* Wake Up Control */ 44 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 49 50 /* Wake Up Filter Control */ 51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 56 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 57 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 58 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 59 60 /* Wake Up Status */ 61 #define E1000_WUS_LNKC E1000_WUFC_LNKC 62 #define E1000_WUS_MAG E1000_WUFC_MAG 63 #define E1000_WUS_EX E1000_WUFC_EX 64 #define E1000_WUS_MC E1000_WUFC_MC 65 #define E1000_WUS_BC E1000_WUFC_BC 66 67 /* Extended Device Control */ 68 #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 69 #define E1000_CTRL_EXT_DPG_EN 0x00000008 /* Dynamic Power Gating */ 70 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ 71 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ 72 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ 73 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ 74 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 75 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 76 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ 77 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 78 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 79 /* Physical Func Reset Done Indication */ 80 #define E1000_CTRL_EXT_PFRSTD 0x00004000 81 #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */ 82 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 83 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 84 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ 85 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 86 /* Offset of the link mode field in Ctrl Ext register */ 87 #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22 88 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 89 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 90 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 91 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 92 #define E1000_CTRL_EXT_EIAME 0x01000000 93 #define E1000_CTRL_EXT_IRCA 0x00000001 94 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 95 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 96 #define E1000_CTRL_EXT_MEHE 0x40000000 /* Memory error handling */ 97 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 98 #define E1000_CTRL_EXT_LSECCK 0x00001000 99 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 100 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 101 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 102 #define E1000_I2CCMD_OPCODE_READ 0x08000000 103 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 104 #define E1000_I2CCMD_READY 0x20000000 105 #define E1000_I2CCMD_ERROR 0x80000000 106 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) 107 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) 108 #define E1000_MAX_SGMII_PHY_REG_ADDR 255 109 #define E1000_I2CCMD_PHY_TIMEOUT 200 110 #define E1000_IVAR_VALID 0x80 111 #define E1000_GPIE_NSICR 0x00000001 112 #define E1000_GPIE_MSIX_MODE 0x00000010 113 #define E1000_GPIE_EIAME 0x40000000 114 #define E1000_GPIE_PBA 0x80000000 115 116 /* Receive Descriptor bit definitions */ 117 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 118 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 119 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 120 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 121 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 122 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 123 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 124 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 125 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 126 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 127 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 128 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 129 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 130 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 131 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 132 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 133 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 134 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 135 136 #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 137 #define E1000_RXDEXT_STATERR_LB 0x00040000 138 #define E1000_RXDEXT_STATERR_CE 0x01000000 139 #define E1000_RXDEXT_STATERR_SE 0x02000000 140 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 141 #define E1000_RXDEXT_STATERR_CXE 0x10000000 142 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 143 #define E1000_RXDEXT_STATERR_IPE 0x40000000 144 #define E1000_RXDEXT_STATERR_RXE 0x80000000 145 146 /* mask to determine if packets should be dropped due to frame errors */ 147 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 148 E1000_RXD_ERR_CE | \ 149 E1000_RXD_ERR_SE | \ 150 E1000_RXD_ERR_SEQ | \ 151 E1000_RXD_ERR_CXE | \ 152 E1000_RXD_ERR_RXE) 153 154 /* Same mask, but for extended and packet split descriptors */ 155 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 156 E1000_RXDEXT_STATERR_CE | \ 157 E1000_RXDEXT_STATERR_SE | \ 158 E1000_RXDEXT_STATERR_SEQ | \ 159 E1000_RXDEXT_STATERR_CXE | \ 160 E1000_RXDEXT_STATERR_RXE) 161 162 #define E1000_MRQC_RSS_ENABLE_2Q 0x00000001 163 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 164 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 165 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 166 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 167 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 168 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 169 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 170 171 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 172 173 /* Management Control */ 174 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 175 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 176 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 177 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 178 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 179 /* Enable MAC address filtering */ 180 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 181 /* Enable MNG packets to host memory */ 182 #define E1000_MANC_EN_MNG2HOST 0x00200000 183 184 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 185 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 186 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 187 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 188 189 /* Receive Control */ 190 #define E1000_RCTL_RST 0x00000001 /* Software reset */ 191 #define E1000_RCTL_EN 0x00000002 /* enable */ 192 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 193 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ 194 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ 195 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 196 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 197 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 198 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 199 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 200 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 201 #define E1000_RCTL_RDMTS_HEX 0x00010000 202 #define E1000_RCTL_RDMTS1_HEX E1000_RCTL_RDMTS_HEX 203 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 204 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 205 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 206 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 207 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 208 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 209 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 210 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 211 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 212 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 213 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 214 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 215 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 216 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 217 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 218 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 219 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 220 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 221 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 222 223 /* Use byte values for the following shift parameters 224 * Usage: 225 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 226 * E1000_PSRCTL_BSIZE0_MASK) | 227 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 228 * E1000_PSRCTL_BSIZE1_MASK) | 229 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 230 * E1000_PSRCTL_BSIZE2_MASK) | 231 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 232 * E1000_PSRCTL_BSIZE3_MASK)) 233 * where value0 = [128..16256], default=256 234 * value1 = [1024..64512], default=4096 235 * value2 = [0..64512], default=4096 236 * value3 = [0..64512], default=0 237 */ 238 239 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 240 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 241 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 242 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 243 244 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 245 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 246 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 247 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 248 249 /* SWFW_SYNC Definitions */ 250 #define E1000_SWFW_EEP_SM 0x01 251 #define E1000_SWFW_PHY0_SM 0x02 252 #define E1000_SWFW_PHY1_SM 0x04 253 #define E1000_SWFW_CSR_SM 0x08 254 #define E1000_SWFW_PHY2_SM 0x20 255 #define E1000_SWFW_PHY3_SM 0x40 256 #define E1000_SWFW_SW_MNG_SM 0x400 257 258 /* Device Control */ 259 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 260 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 261 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ 262 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 263 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 264 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 265 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 266 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 267 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 268 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 269 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 270 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 271 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 272 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 273 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 274 #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ 275 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 276 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 277 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 278 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 279 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ 280 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 281 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 282 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 283 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 284 #define E1000_CTRL_DEV_RST 0x20000000 /* Device reset */ 285 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 286 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 287 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 288 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 289 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 290 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 291 292 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 293 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 294 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 295 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 296 297 #define E1000_CONNSW_ENRGSRC 0x4 298 #define E1000_CONNSW_PHYSD 0x400 299 #define E1000_CONNSW_PHY_PDN 0x800 300 #define E1000_CONNSW_SERDESD 0x200 301 #define E1000_CONNSW_AUTOSENSE_CONF 0x2 302 #define E1000_CONNSW_AUTOSENSE_EN 0x1 303 #define E1000_PCS_CFG_PCS_EN 8 304 #define E1000_PCS_LCTL_FLV_LINK_UP 1 305 #define E1000_PCS_LCTL_FSV_10 0 306 #define E1000_PCS_LCTL_FSV_100 2 307 #define E1000_PCS_LCTL_FSV_1000 4 308 #define E1000_PCS_LCTL_FDV_FULL 8 309 #define E1000_PCS_LCTL_FSD 0x10 310 #define E1000_PCS_LCTL_FORCE_LINK 0x20 311 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 312 #define E1000_PCS_LCTL_AN_ENABLE 0x10000 313 #define E1000_PCS_LCTL_AN_RESTART 0x20000 314 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 315 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 316 317 #define E1000_PCS_LSTS_LINK_OK 1 318 #define E1000_PCS_LSTS_SPEED_100 2 319 #define E1000_PCS_LSTS_SPEED_1000 4 320 #define E1000_PCS_LSTS_DUPLEX_FULL 8 321 #define E1000_PCS_LSTS_SYNK_OK 0x10 322 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 323 324 /* Device Status */ 325 #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ 326 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 327 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 328 #define E1000_STATUS_FUNC_SHIFT 2 329 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 330 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 331 #define E1000_STATUS_SPEED_MASK 0x000000C0 332 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 333 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 334 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 335 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ 336 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 337 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ 338 #define E1000_STATUS_RST_DONE 0x00200000 /* Device reset complete */ 339 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 340 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 341 #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 342 #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 343 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 344 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 345 346 /* Constants used to interpret the masked PCI-X bus speed. */ 347 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */ 348 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */ 349 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/ 350 #define E1000_STATUS_PCIM_STATE 0x40000000 /* PCIm function state */ 351 352 #define SPEED_10 10 353 #define SPEED_100 100 354 #define SPEED_1000 1000 355 #define SPEED_2500 2500 356 #define HALF_DUPLEX 1 357 #define FULL_DUPLEX 2 358 359 #define PHY_FORCE_TIME 20 360 361 #define ADVERTISE_10_HALF 0x0001 362 #define ADVERTISE_10_FULL 0x0002 363 #define ADVERTISE_100_HALF 0x0004 364 #define ADVERTISE_100_FULL 0x0008 365 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 366 #define ADVERTISE_1000_FULL 0x0020 367 368 /* 1000/H is not supported, nor spec-compliant. */ 369 #define E1000_ALL_SPEED_DUPLEX ( \ 370 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 371 ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 372 #define E1000_ALL_NOT_GIG ( \ 373 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 374 ADVERTISE_100_FULL) 375 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 376 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 377 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 378 379 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 380 381 /* LED Control */ 382 #define E1000_PHY_LED0_MODE_MASK 0x00000007 383 #define E1000_PHY_LED0_IVRT 0x00000008 384 #define E1000_PHY_LED0_MASK 0x0000001F 385 386 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 387 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 388 #define E1000_LEDCTL_LED0_IVRT 0x00000040 389 #define E1000_LEDCTL_LED0_BLINK 0x00000080 390 391 #define E1000_LEDCTL_MODE_LINK_UP 0x2 392 #define E1000_LEDCTL_MODE_LED_ON 0xE 393 #define E1000_LEDCTL_MODE_LED_OFF 0xF 394 395 /* Transmit Descriptor bit definitions */ 396 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 397 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 398 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 399 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 400 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 401 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 402 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 403 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 404 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 405 #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 406 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 407 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 408 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 409 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 410 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 411 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 412 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 413 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 414 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 415 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 416 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 417 418 /* Transmit Control */ 419 #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 420 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 421 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 422 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 423 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 424 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 425 426 /* Transmit Arbitration Count */ 427 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 428 429 /* SerDes Control */ 430 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 431 #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 432 433 /* Receive Checksum Control */ 434 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 435 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 436 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* lem(4) IPv6 checksum offload */ 437 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 438 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 439 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 440 441 /* Header split receive */ 442 #define E1000_RFCTL_NFSW_DIS 0x00000040 443 #define E1000_RFCTL_NFSR_DIS 0x00000080 444 #define E1000_RFCTL_ACK_DIS 0x00001000 445 #define E1000_RFCTL_EXTEN 0x00008000 446 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 447 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 448 #define E1000_RFCTL_LEF 0x00040000 449 450 /* Collision related configuration parameters */ 451 #define E1000_CT_SHIFT 4 452 #define E1000_COLLISION_THRESHOLD 15 453 #define E1000_COLLISION_DISTANCE 63 454 #define E1000_COLD_SHIFT 12 455 456 /* Default values for the transmit IPG register */ 457 #define DEFAULT_82542_TIPG_IPGT 10 458 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 459 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 460 461 #define E1000_TIPG_IPGT_MASK 0x000003FF 462 463 #define DEFAULT_82542_TIPG_IPGR1 2 464 #define DEFAULT_82543_TIPG_IPGR1 8 465 #define E1000_TIPG_IPGR1_SHIFT 10 466 467 #define DEFAULT_82542_TIPG_IPGR2 10 468 #define DEFAULT_82543_TIPG_IPGR2 6 469 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 470 #define E1000_TIPG_IPGR2_SHIFT 20 471 472 /* Ethertype field values */ 473 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 474 475 #define ETHERNET_FCS_SIZE 4 476 #define MAX_JUMBO_FRAME_SIZE 0x3F00 477 /* The datasheet maximum supported RX size is 9.5KB (9728 bytes) */ 478 #define MAX_RX_JUMBO_FRAME_SIZE 0x2600 479 #define E1000_TX_PTR_GAP 0x1F 480 481 /* Extended Configuration Control and Size */ 482 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 483 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 484 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 485 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 486 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 487 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 488 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 489 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 490 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 491 492 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 493 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 494 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 495 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 496 497 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 498 499 /* Low Power IDLE Control */ 500 #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ 501 502 /* PBA constants */ 503 #define E1000_PBA_8K 0x0008 /* 8KB */ 504 #define E1000_PBA_10K 0x000A /* 10KB */ 505 #define E1000_PBA_12K 0x000C /* 12KB */ 506 #define E1000_PBA_14K 0x000E /* 14KB */ 507 #define E1000_PBA_16K 0x0010 /* 16KB */ 508 #define E1000_PBA_18K 0x0012 509 #define E1000_PBA_20K 0x0014 510 #define E1000_PBA_22K 0x0016 511 #define E1000_PBA_24K 0x0018 512 #define E1000_PBA_26K 0x001A 513 #define E1000_PBA_30K 0x001E 514 #define E1000_PBA_32K 0x0020 515 #define E1000_PBA_34K 0x0022 516 #define E1000_PBA_35K 0x0023 517 #define E1000_PBA_38K 0x0026 518 #define E1000_PBA_40K 0x0028 519 #define E1000_PBA_48K 0x0030 /* 48KB */ 520 #define E1000_PBA_64K 0x0040 /* 64KB */ 521 522 #define E1000_PBA_RXA_MASK 0xFFFF 523 524 #define E1000_PBS_16K E1000_PBA_16K 525 526 /* Uncorrectable/correctable ECC Error counts and enable bits */ 527 #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 528 #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 529 #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 530 #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 531 532 /* 82575 packet-buffer and descriptor-handler ECC status. */ 533 #define E1000_ECC_82575_CORR_CNT_MASK 0x000000FF 534 #define E1000_ECC_82575_UNCORR_CNT_MASK 0x0000FF00 535 #define E1000_ECC_82575_UNCORR_CNT_SHIFT 8 536 #define E1000_ECC_82575_ENABLE 0x00010000 537 538 /* I350, I354, and I210/I211 memory error status bits. */ 539 #define E1000_PEIND_LANPORT_PARITY_FATAL 0x00000001 540 #define E1000_PEIND_MNG_PARITY_FATAL 0x00000002 541 #define E1000_PEIND_PCIE_PARITY_FATAL 0x00000004 542 #define E1000_PEIND_DMA_PARITY_FATAL 0x00000008 543 #define E1000_PEIND_FATAL_MASK 0x0000000F 544 545 /* 82580 parity and ECC detection controls. */ 546 #define E1000_DTPARC_82580_ENABLE_MASK 0x00001555 547 #define E1000_DRPARC_82580_ENABLE_MASK 0x00000055 548 #define E1000_DDPARC_82580_ENABLE_MASK 0x00000055 549 #define E1000_PCIEERRCTL_82580_ENABLE_MASK 0x00005555 550 #define E1000_PCIEECCCTL_82580_ENABLE_MASK 0x00000011 551 #define E1000_LANPERRCTL_82580_HOST_MASK 0x00007E00 552 #define E1000_LANPERRCTL_82580_RSS_ENABLE 0x00001000 553 #define E1000_PCIEECCSTS_82580_ERROR_MASK 0x00000003 554 #define E1000_LANPERRSTS_82580_ERROR_MASK 0x00007FFF 555 #define E1000_PBECCSTS_82580_ECC_ENABLE 0x00010000 556 #define E1000_PBECCSTS_82580_CORR_CNT_MASK 0x000000FF 557 558 /* 82576 uses PEIND directly rather than the later four-region layout. */ 559 #define E1000_PEIND_82576_NONFATAL_MASK 0x00000007 560 #define E1000_PEIND_82576_FATAL_MASK 0x7FFFFF00 561 #define E1000_PEIND_82576_MEMORY_HANG 0x80000000 562 #define E1000_PEINDM_82576_PARITY_ENABLE 0x80000000 563 /* 82576NS omits the IPsec key, FIFO, and packet-buffer memories. */ 564 #define E1000_PEIND_82576_IPSEC_MASK 0x40700600 565 566 /* The 82576 clear-on-read ECC status registers share this count layout. */ 567 #define E1000_ECC_82576_CORR_CNT_MASK 0x000000FF 568 #define E1000_ECC_82576_UNCORR_CNT_MASK 0x0000FF00 569 #define E1000_ECC_82576_UNCORR_CNT_SHIFT 8 570 571 #define E1000_PBECCSTS_I210_ECC_ENABLE 0x00000001 572 #define E1000_PBECCSTS_I210_CORR_ERR 0x00000004 573 574 #define E1000_PCIEERRSTS_I210_FATAL_MASK 0x00000078 575 #define E1000_PCIEERRSTS_I350_I354_FATAL_MASK 0x0000007C 576 #define E1000_PCIEECCSTS_TX_WR_DATA 0x00000010 577 #define E1000_PCIEECCSTS_RETRY_BUF 0x00000020 578 #define E1000_PCIEECCSTS_I210_CORR_MASK 0x00000030 579 #define E1000_PCIEECCSTS_I350_I354_OTHER_MASK 0x0000000F 580 #define E1000_PCIEECCSTS_I350_CORR_MASK 0x0000003F 581 /* I354 has no I350-style PCIe retry-buffer status bit. */ 582 #define E1000_PCIEECCSTS_I354_CORR_MASK 0x0000001F 583 584 #define E1000_DTPARS_CORR_MASK 0x0000005B 585 #define E1000_DTPARS_FATAL_MASK 0x00000020 586 #define E1000_DRPARS_CORR_MASK 0x0000000D 587 #define E1000_DRPARS_FATAL_MASK 0x00000002 588 #define E1000_DDECCS_CORR_MASK 0x0000000F 589 590 #define E1000_PBECCSTS_I350_I354_ENABLE_MASK 0x00030000 591 #define E1000_PBECCSTS_I350_I354_CORR_MASK 0x14000000 592 593 #define E1000_LANPERRSTS_RETX_BUF 0x00000200 594 #define E1000_LANPERRSTS_MNG_FIFO_CORR 0x00010000 595 #define E1000_LANPERRSTS_I350_I354_NO_RESET_MASK 0x00008400 596 #define E1000_LANPERRSTS_I350_I354_RESET_MASK 0x00007BFE 597 #define E1000_LANPERRSTS_I350_I354_FATAL_MASK 0x0000FFFE 598 599 #define IFS_MAX 80 600 #define IFS_MIN 40 601 #define IFS_RATIO 4 602 #define IFS_STEP 10 603 #define MIN_NUM_XMITS 1000 604 605 /* SW Semaphore Register */ 606 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 607 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 608 #define E1000_SWSM_TIMEOUT 2000 /* 100 ms at 50 us per poll */ 609 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 610 611 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 612 613 /* Interrupt Cause Read */ 614 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 615 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 616 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 617 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 618 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 619 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */ 620 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 621 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 622 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 623 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 624 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 625 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 626 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 627 #define E1000_ICR_TXD_LOW 0x00008000 628 #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 629 #define E1000_ICR_82575_RX_PBUR 0x00400000 /* Rx packet buffer error */ 630 #define E1000_ICR_82575_TX_PBUR 0x00800000 /* Tx packet buffer error */ 631 #define E1000_ICR_82575_RX_DHER 0x01000000 /* Rx descriptor error */ 632 #define E1000_ICR_82575_TX_DHER 0x02000000 /* Tx descriptor error */ 633 #define E1000_ICR_82575_MEMORY_ERROR_MASK \ 634 (E1000_ICR_82575_RX_PBUR | E1000_ICR_82575_TX_PBUR | \ 635 E1000_ICR_82575_RX_DHER | E1000_ICR_82575_TX_DHER) 636 #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 637 #define E1000_ICR_NFER 0x00800000 /* Non-Fatal Error (82576) */ 638 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 639 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 640 /* If this bit asserted, the driver should claim the interrupt */ 641 #define E1000_ICR_INT_ASSERTED 0x80000000 642 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 643 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 644 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 645 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 646 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 647 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 648 #define E1000_ICR_FER 0x00400000 /* Fatal Error */ 649 650 #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/ 651 #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */ 652 653 #define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */ 654 #define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */ 655 656 /* PBA ECC Register */ 657 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 658 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 659 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 660 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 661 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 662 663 /* Extended Interrupt Cause Read */ 664 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 665 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 666 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 667 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 668 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 669 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 670 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 671 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 672 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 673 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 674 /* TCP Timer */ 675 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ 676 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 677 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 678 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ 679 680 /* This defines the bits that are set in the Interrupt Mask 681 * Set/Read Register. Each bit is documented below: 682 * o RXT0 = Receiver Timer Interrupt (ring 0) 683 * o TXDW = Transmit Descriptor Written Back 684 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 685 * o RXSEQ = Receive Sequence Error 686 * o LSC = Link Status Change 687 */ 688 #define IMS_ENABLE_MASK ( \ 689 E1000_IMS_RXT0 | \ 690 E1000_IMS_TXDW | \ 691 E1000_IMS_RXDMT0 | \ 692 E1000_IMS_RXSEQ | \ 693 E1000_IMS_LSC) 694 695 /* Interrupt Mask Set */ 696 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */ 697 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 698 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 699 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 700 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 701 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 702 #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */ 703 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 704 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 705 #define E1000_IMS_82575_MEMORY_ERROR_MASK E1000_ICR_82575_MEMORY_ERROR_MASK 706 #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ 707 #define E1000_IMS_NFER E1000_ICR_NFER /* Non-Fatal Error (82576) */ 708 #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ 709 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 710 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 711 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 712 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 713 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 714 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 715 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 716 #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */ 717 718 #define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/ 719 #define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */ 720 /* Extended Interrupt Mask Set */ 721 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 722 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 723 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 724 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 725 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 726 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 727 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 728 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 729 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 730 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 731 732 /* Interrupt Cause Set */ 733 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 734 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 735 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 736 737 /* Extended Interrupt Cause Set */ 738 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 739 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 740 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 741 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 742 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 743 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 744 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 745 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 746 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 747 #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 748 749 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF 750 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 751 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 752 #define E1000_EITR_INTERVAL 0x00007FFC 753 754 /* Transmit Descriptor Control */ 755 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 756 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 757 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 758 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 759 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 760 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 761 /* Enable the counting of descriptors still to be processed. */ 762 #define E1000_TXDCTL_COUNT_DESC 0x00400000 763 764 /* Flow Control Constants */ 765 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 766 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 767 #define FLOW_CONTROL_TYPE 0x8808 768 769 /* 802.1q VLAN Packet Size */ 770 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 771 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 772 773 /* Receive Address 774 * Number of high/low register pairs in the RAR. The RAR (Receive Address 775 * Registers) holds the directed and multicast addresses that we monitor. 776 * Technically, we have 16 spots. However, we reserve one of these spots 777 * (RAR[15]) for our directed address used by controllers with 778 * manageability enabled, allowing us room for 15 multicast addresses. 779 */ 780 #define E1000_RAR_ENTRIES 15 781 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 782 #define E1000_RAL_MAC_ADDR_LEN 4 783 #define E1000_RAH_MAC_ADDR_LEN 2 784 #define E1000_RAH_QUEUE_MASK_82575 0x000C0000 785 #define E1000_RAH_POOL_1 0x00040000 786 787 /* Error Codes */ 788 #define E1000_SUCCESS 0 789 #define E1000_ERR_NVM 1 790 #define E1000_ERR_PHY 2 791 #define E1000_ERR_CONFIG 3 792 #define E1000_ERR_PARAM 4 793 #define E1000_ERR_MAC_INIT 5 794 #define E1000_ERR_PHY_TYPE 6 795 #define E1000_ERR_RESET 9 796 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 797 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 798 #define E1000_BLK_PHY_RESET 12 799 #define E1000_ERR_SWFW_SYNC 13 800 #define E1000_NOT_IMPLEMENTED 14 801 #define E1000_ERR_MBX 15 802 #define E1000_ERR_INVALID_ARGUMENT 16 803 #define E1000_ERR_NO_SPACE 17 804 #define E1000_ERR_NVM_PBA_SECTION 18 805 #define E1000_ERR_I2C 19 806 #define E1000_ERR_INVM_VALUE_NOT_FOUND 20 807 808 /* Loop limit on how long we wait for auto-negotiation to complete */ 809 #define FIBER_LINK_UP_LIMIT 50 810 #define COPPER_LINK_UP_LIMIT 10 811 #define PHY_AUTO_NEG_LIMIT 45 812 #define PHY_FORCE_LIMIT 20 813 /* Number of 100 microseconds we wait for PCI Express master disable */ 814 #define MASTER_DISABLE_TIMEOUT 800 815 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 816 #define PHY_CFG_TIMEOUT 100 817 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 818 #define MDIO_OWNERSHIP_TIMEOUT 10 819 /* Number of milliseconds for NVM auto read done after MAC reset. */ 820 #define AUTO_READ_DONE_TIMEOUT 10 821 822 /* Flow Control */ 823 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 824 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 825 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 826 827 /* Transmit Configuration Word */ 828 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 829 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 830 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 831 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 832 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 833 834 /* Receive Configuration Word */ 835 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 836 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 837 #define E1000_RXCW_C 0x20000000 /* Receive config */ 838 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 839 840 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 841 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 842 843 /* HH Time Sync */ 844 #define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 845 #define E1000_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */ 846 #define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 847 #define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 848 849 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 850 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 851 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 852 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 853 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 854 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 855 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 856 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 857 #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 858 859 #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 860 #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 861 862 #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 863 #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 864 865 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 866 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 867 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 868 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 869 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 870 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 871 872 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 873 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 874 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 875 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 876 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 877 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 878 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 879 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 880 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 881 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 882 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 883 884 #define E1000_TIMINCA_16NS_SHIFT 24 885 #define E1000_TIMINCA_INCPERIOD_SHIFT 24 886 #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF 887 888 /* ETQF register bit definitions */ 889 #define E1000_ETQF_1588 (1 << 30) 890 #define E1000_FTQF_VF_BP 0x00008000 891 #define E1000_FTQF_1588_TIME_STAMP 0x08000000 892 #define E1000_FTQF_MASK 0xF0000000 893 #define E1000_FTQF_MASK_PROTO_BP 0x10000000 894 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 895 #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 896 #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 897 898 #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 899 #define E1000_TSICR_TXTS 0x00000002 900 #define E1000_TSIM_TXTS 0x00000002 901 /* TUPLE Filtering Configuration */ 902 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ 903 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ 904 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ 905 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */ 906 #define E1000_TTQF_PROTOCOL_TCP 0x0 907 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 908 #define E1000_TTQF_PROTOCOL_UDP 0x1 909 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 910 #define E1000_TTQF_PROTOCOL_SCTP 0x2 911 #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ 912 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ 913 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ 914 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ 915 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 916 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 917 #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 918 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 919 920 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 921 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 922 #define E1000_MDICNFG_PHY_MASK 0x03E00000 923 #define E1000_MDICNFG_PHY_SHIFT 21 924 925 #define E1000_MEDIA_PORT_COPPER 1 926 #define E1000_MEDIA_PORT_OTHER 2 927 #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2 928 #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3 929 #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ 930 #define E1000_M88E1112_MAC_CTRL_1 0x10 931 #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ 932 #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 933 #define E1000_M88E1112_PAGE_ADDR 0x16 934 #define E1000_M88E1112_STATUS 0x01 935 936 #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */ 937 #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */ 938 #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */ 939 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 940 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ 941 942 /* I350 EEE defines */ 943 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 944 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 945 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 946 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 947 #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 948 /* EEE status */ 949 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 950 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 951 #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 952 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 953 #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 954 #define E1000_M88E1543_EEE_CTRL_1 0x0 955 #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 956 #define E1000_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */ 957 #define E1000_EEE_ADV_DEV_I354 7 958 #define E1000_EEE_ADV_ADDR_I354 60 959 #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 960 #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 961 #define E1000_PCS_STATUS_DEV_I354 3 962 #define E1000_PCS_STATUS_ADDR_I354 1 963 #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 964 #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 965 #define E1000_M88E1512_CFG_REG_1 0x0010 966 #define E1000_M88E1512_CFG_REG_2 0x0011 967 #define E1000_M88E1512_CFG_REG_3 0x0007 968 #define E1000_M88E1512_MODE 0x0014 969 #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ 970 #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ 971 #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ 972 /* PCI Express Control */ 973 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 974 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 975 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 976 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 977 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 978 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 979 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 980 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 981 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 982 #define E1000_GCR_CAP_VER2 0x00040000 983 984 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 985 E1000_GCR_RXDSCW_NO_SNOOP | \ 986 E1000_GCR_RXDSCR_NO_SNOOP | \ 987 E1000_GCR_TXD_NO_SNOOP | \ 988 E1000_GCR_TXDSCW_NO_SNOOP | \ 989 E1000_GCR_TXDSCR_NO_SNOOP) 990 991 #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 992 993 /* mPHY address control and data registers */ 994 #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */ 995 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 996 #define E1000_MPHY_DATA 0x0E10 /* Data Register */ 997 998 /* AFE CSR Offset for PCS CLK */ 999 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 1000 /* Override for near end digital loopback. */ 1001 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 1002 1003 /* PHY Control Register */ 1004 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1005 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 1006 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 1007 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 1008 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 1009 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 1010 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 1011 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1012 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 1013 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 1014 #define MII_CR_SPEED_1000 0x0040 1015 #define MII_CR_SPEED_100 0x2000 1016 #define MII_CR_SPEED_10 0x0000 1017 1018 /* PHY Status Register */ 1019 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 1020 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 1021 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 1022 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 1023 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 1024 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 1025 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 1026 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 1027 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 1028 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 1029 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 1030 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 1031 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 1032 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 1033 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 1034 1035 /* Autoneg Advertisement Register */ 1036 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 1037 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 1038 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 1039 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 1040 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 1041 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 1042 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 1043 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 1044 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 1045 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1046 1047 /* Link Partner Ability Register (Base Page) */ 1048 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 1049 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */ 1050 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */ 1051 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */ 1052 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 1053 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 1054 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 1055 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */ 1056 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */ 1057 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */ 1058 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1059 1060 /* Autoneg Expansion Register */ 1061 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 1062 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */ 1063 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */ 1064 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */ 1065 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */ 1066 1067 /* 1000BASE-T Control Register */ 1068 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 1069 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 1070 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 1071 /* 1=Repeater/switch device port 0=DTE device */ 1072 #define CR_1000T_REPEATER_DTE 0x0400 1073 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 1074 #define CR_1000T_MS_VALUE 0x0800 1075 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 1076 #define CR_1000T_MS_ENABLE 0x1000 1077 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 1078 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 1079 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 1080 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 1081 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 1082 1083 /* 1000BASE-T Status Register */ 1084 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */ 1085 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */ 1086 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 1087 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 1088 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 1089 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 1090 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */ 1091 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 1092 1093 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 1094 1095 /* PHY 1000 MII Register/Bit Definitions */ 1096 /* PHY Registers defined by IEEE */ 1097 #define PHY_CONTROL 0x00 /* Control Register */ 1098 #define PHY_STATUS 0x01 /* Status Register */ 1099 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 1100 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 1101 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 1102 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 1103 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 1104 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ 1105 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 1106 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 1107 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 1108 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 1109 1110 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 1111 1112 /* NVM Control */ 1113 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 1114 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 1115 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 1116 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 1117 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 1118 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 1119 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 1120 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 1121 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ 1122 #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ 1123 #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ 1124 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ 1125 /* NVM Addressing bits based on type 0=small, 1=large */ 1126 #define E1000_EECD_ADDR_BITS 0x00000400 1127 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ 1128 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 1129 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 1130 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 1131 #define E1000_EECD_SIZE_EX_SHIFT 11 1132 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1133 #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 1134 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1135 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 1136 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 1137 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */ 1138 #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ 1139 #define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */ 1140 #define E1000_FLUDONE_ATTEMPTS 20000 1141 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 1142 #define E1000_I210_FIFO_SEL_RX 0x00 1143 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 1144 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 1145 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 1146 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 1147 1148 #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ 1149 /* Secure FLASH mode requires removing MSb */ 1150 #define E1000_I210_FW_PTR_MASK 0x7FFF 1151 /* Firmware code revision field word offset*/ 1152 #define E1000_I210_FW_VER_OFFSET 328 1153 1154 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 1155 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1156 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 1157 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1158 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1159 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1160 #define E1000_FLASH_UPDATES 2000 1161 1162 /* NVM Word Offsets */ 1163 #define NVM_COMPAT 0x0003 1164 #define NVM_ID_LED_SETTINGS 0x0004 1165 #define NVM_VERSION 0x0005 1166 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ 1167 #define NVM_PHY_CLASS_WORD 0x0007 1168 #define E1000_I210_NVM_FW_MODULE_PTR 0x0010 1169 #define E1000_I350_NVM_FW_MODULE_PTR 0x0051 1170 #define NVM_FUTURE_INIT_WORD1 0x0019 1171 #define NVM_ETRACK_WORD 0x0042 1172 #define NVM_ETRACK_HIWORD 0x0043 1173 #define NVM_COMB_VER_OFF 0x0083 1174 #define NVM_COMB_VER_PTR 0x003d 1175 1176 /* NVM version defines */ 1177 #define NVM_MAJOR_MASK 0xF000 1178 #define NVM_MINOR_MASK 0x0FF0 1179 #define NVM_IMAGE_ID_MASK 0x000F 1180 #define NVM_COMB_VER_MASK 0x00FF 1181 #define NVM_MAJOR_SHIFT 12 1182 #define NVM_MINOR_SHIFT 4 1183 #define NVM_COMB_VER_SHFT 8 1184 #define NVM_VER_INVALID 0xFFFF 1185 #define NVM_ETRACK_SHIFT 16 1186 #define NVM_ETRACK_VALID 0x8000 1187 #define NVM_NEW_DEC_MASK 0x0F00 1188 #define NVM_HEX_CONV 16 1189 #define NVM_HEX_TENS 10 1190 1191 /* FW version defines */ 1192 /* Offset of "Loader patch ptr" in Firmware Header */ 1193 #define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET 0x01 1194 /* Patch generation hour & minutes */ 1195 #define E1000_I350_NVM_FW_VER_WORD1_OFFSET 0x04 1196 /* Patch generation month & day */ 1197 #define E1000_I350_NVM_FW_VER_WORD2_OFFSET 0x05 1198 /* Patch generation year */ 1199 #define E1000_I350_NVM_FW_VER_WORD3_OFFSET 0x06 1200 /* Patch major & minor numbers */ 1201 #define E1000_I350_NVM_FW_VER_WORD4_OFFSET 0x07 1202 1203 #define NVM_MAC_ADDR 0x0000 1204 #define NVM_SUB_DEV_ID 0x000B 1205 #define NVM_SUB_VEN_ID 0x000C 1206 #define NVM_DEV_ID 0x000D 1207 #define NVM_VEN_ID 0x000E 1208 #define NVM_INIT_CTRL_2 0x000F 1209 #define NVM_INIT_CTRL_4 0x0013 1210 #define NVM_LED_1_CFG 0x001C 1211 #define NVM_LED_0_2_CFG 0x001F 1212 1213 #define NVM_COMPAT_VALID_CSUM 0x0001 1214 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 1215 1216 #define NVM_INIT_CONTROL2_REG 0x000F 1217 #define NVM_INIT_CONTROL3_PORT_B 0x0014 1218 #define NVM_INIT_3GIO_3 0x001A 1219 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1220 #define NVM_INIT_CONTROL3_PORT_A 0x0024 1221 #define NVM_CFG 0x0012 1222 #define NVM_ALT_MAC_ADDR_PTR 0x0037 1223 #define NVM_CHECKSUM_REG 0x003F 1224 #define NVM_COMPATIBILITY_REG_3 0x0003 1225 #define NVM_COMPATIBILITY_BIT_MASK 0x8000 1226 1227 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 1228 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 1229 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 1230 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 1231 1232 #define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0) 1233 1234 /* Mask bits for fields in Word 0x24 of the NVM */ 1235 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 1236 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */ 1237 /* Offset of Link Mode bits for 82575/82576 */ 1238 #define NVM_WORD24_LNK_MODE_OFFSET 8 1239 /* Offset of Link Mode bits for 82580 up */ 1240 #define NVM_WORD24_82580_LNK_MODE_OFFSET 4 1241 1242 1243 /* Mask bits for fields in Word 0x0f of the NVM */ 1244 #define NVM_WORD0F_PAUSE_MASK 0x3000 1245 #define NVM_WORD0F_PAUSE 0x1000 1246 #define NVM_WORD0F_ASM_DIR 0x2000 1247 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1248 1249 /* Mask bits for fields in Word 0x1a of the NVM */ 1250 #define NVM_WORD1A_ASPM_MASK 0x000C 1251 1252 /* Mask bits for fields in Word 0x03 of the EEPROM */ 1253 #define NVM_COMPAT_LOM 0x0800 1254 1255 /* length of string needed to store PBA number */ 1256 #define E1000_PBANUM_LENGTH 11 1257 1258 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 1259 #define NVM_SUM 0xBABA 1260 #define NVM_CHECKSUM_UNINITIALIZED 0xFFFF 1261 1262 /* PBA (printed board assembly) number words */ 1263 #define NVM_PBA_OFFSET_0 8 1264 #define NVM_PBA_OFFSET_1 9 1265 #define NVM_PBA_PTR_GUARD 0xFAFA 1266 #define NVM_RESERVED_WORD 0xFFFF 1267 #define NVM_PHY_CLASS_A 0x8000 1268 #define NVM_SERDES_AMPLITUDE_MASK 0x000F 1269 #define NVM_SIZE_MASK 0x1C00 1270 #define NVM_SIZE_SHIFT 10 1271 #define NVM_WORD_SIZE_BASE_SHIFT 6 1272 #define NVM_SWDPIO_EXT_SHIFT 4 1273 1274 /* NVM Commands - Microwire */ 1275 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 1276 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 1277 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 1278 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 1279 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ 1280 1281 /* NVM Commands - SPI */ 1282 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1283 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 1284 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 1285 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1286 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 1287 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 1288 1289 /* SPI NVM Status Register */ 1290 #define NVM_STATUS_RDY_SPI 0x01 1291 1292 /* Word definitions for ID LED Settings */ 1293 #define ID_LED_RESERVED_0000 0x0000 1294 #define ID_LED_RESERVED_FFFF 0xFFFF 1295 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1296 (ID_LED_OFF1_OFF2 << 8) | \ 1297 (ID_LED_DEF1_DEF2 << 4) | \ 1298 (ID_LED_DEF1_DEF2)) 1299 #define ID_LED_DEF1_DEF2 0x1 1300 #define ID_LED_DEF1_ON2 0x2 1301 #define ID_LED_DEF1_OFF2 0x3 1302 #define ID_LED_ON1_DEF2 0x4 1303 #define ID_LED_ON1_ON2 0x5 1304 #define ID_LED_ON1_OFF2 0x6 1305 #define ID_LED_OFF1_DEF2 0x7 1306 #define ID_LED_OFF1_ON2 0x8 1307 #define ID_LED_OFF1_OFF2 0x9 1308 1309 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1310 #define IGP_ACTIVITY_LED_ENABLE 0x0300 1311 #define IGP_LED3_MODE 0x07000000 1312 1313 /* PCI/PCI-X/PCI-EX Config space */ 1314 #define PCIX_COMMAND_REGISTER 0xE6 1315 #define PCIX_STATUS_REGISTER_LO 0xE8 1316 #define PCIX_STATUS_REGISTER_HI 0xEA 1317 #define PCI_HEADER_TYPE_REGISTER 0x0E 1318 #define PCIE_LINK_STATUS 0x12 1319 #define PCIE_DEVICE_CONTROL2 0x28 1320 1321 #define PCIX_COMMAND_MMRBC_MASK 0x000C 1322 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1323 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1324 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1325 #define PCIX_STATUS_HI_MMRBC_4K 0x3 1326 #define PCIX_STATUS_HI_MMRBC_2K 0x2 1327 #define PCIX_STATUS_LO_FUNC_MASK 0x7 1328 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 1329 #define PCIE_LINK_WIDTH_MASK 0x3F0 1330 #define PCIE_LINK_WIDTH_SHIFT 4 1331 #define PCIE_LINK_SPEED_MASK 0x0F 1332 #define PCIE_LINK_SPEED_2500 0x01 1333 #define PCIE_LINK_SPEED_5000 0x02 1334 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 1335 1336 #define PHY_REVISION_MASK 0xFFFFFFF0 1337 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1338 #define MAX_PHY_MULTI_PAGE_REG 0xF 1339 1340 /* Bit definitions for valid PHY IDs. 1341 * I = Integrated 1342 * E = External 1343 */ 1344 #define M88E1000_E_PHY_ID 0x01410C50 1345 #define M88E1000_I_PHY_ID 0x01410C30 1346 #define M88E1011_I_PHY_ID 0x01410C20 1347 #define IGP01E1000_I_PHY_ID 0x02A80380 1348 #define M88E1111_I_PHY_ID 0x01410CC0 1349 #define M88E1543_E_PHY_ID 0x01410EA0 1350 #define M88E1512_E_PHY_ID 0x01410DD0 1351 #define M88E1112_E_PHY_ID 0x01410C90 1352 #define I347AT4_E_PHY_ID 0x01410DC0 1353 #define M88E1340M_E_PHY_ID 0x01410DF0 1354 #define GG82563_E_PHY_ID 0x01410CA0 1355 #define IGP03E1000_E_PHY_ID 0x02A80390 1356 #define IFE_E_PHY_ID 0x02A80330 1357 #define IFE_PLUS_E_PHY_ID 0x02A80320 1358 #define IFE_C_E_PHY_ID 0x02A80310 1359 #define BME1000_E_PHY_ID 0x01410CB0 1360 #define BME1000_E_PHY_ID_R2 0x01410CB1 1361 #define I82577_E_PHY_ID 0x01540050 1362 #define I82578_E_PHY_ID 0x004DD040 1363 #define I82579_E_PHY_ID 0x01540090 1364 #define I217_E_PHY_ID 0x015400A0 1365 #define I82580_I_PHY_ID 0x015403A0 1366 #define I350_I_PHY_ID 0x015403B0 1367 #define I210_I_PHY_ID 0x01410C00 1368 #define IGP04E1000_E_PHY_ID 0x02A80391 1369 #define M88_VENDOR 0x0141 1370 1371 /* M88E1000 Specific Registers */ 1372 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ 1373 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ 1374 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ 1375 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1376 1377 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 1378 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */ 1379 #define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ 1380 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 1381 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 1382 1383 /* M88E1000 PHY Specific Control Register */ 1384 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ 1385 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ 1386 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 1387 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1388 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 1389 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 1390 /* Auto crossover enabled all speeds */ 1391 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 1392 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ 1393 1394 /* M88E1000 PHY Specific Status Register */ 1395 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1396 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1397 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1398 /* 0 = <50M 1399 * 1 = 50-80M 1400 * 2 = 80-110M 1401 * 3 = 110-140M 1402 * 4 = >140M 1403 */ 1404 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 1405 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1406 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1407 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1408 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1409 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1410 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1411 1412 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1413 1414 /* Number of times we will attempt to autonegotiate before downshifting if we 1415 * are the master 1416 */ 1417 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1418 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1419 /* Number of times we will attempt to autonegotiate before downshifting if we 1420 * are the slave 1421 */ 1422 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1423 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1424 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1425 1426 /* Intel I347AT4 Registers */ 1427 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ 1428 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 1429 #define I347AT4_PAGE_SELECT 0x16 1430 1431 /* I347AT4 Extended PHY Specific Control Register */ 1432 1433 /* Number of times we will attempt to autonegotiate before downshifting if we 1434 * are the master 1435 */ 1436 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 1437 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 1438 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 1439 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 1440 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 1441 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 1442 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 1443 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 1444 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 1445 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 1446 1447 /* I347AT4 PHY Cable Diagnostics Control */ 1448 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 1449 1450 /* M88E1112 only registers */ 1451 #define M88E1112_VCT_DSP_DISTANCE 0x001A 1452 1453 /* M88EC018 Rev 2 specific DownShift settings */ 1454 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1455 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1456 1457 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 1458 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 1459 1460 /* BME1000 PHY Specific Control Register */ 1461 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 1462 1463 /* Bits... 1464 * 15-5: page 1465 * 4-0: register offset 1466 */ 1467 #define GG82563_PAGE_SHIFT 5 1468 #define GG82563_REG(page, reg) \ 1469 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1470 #define GG82563_MIN_ALT_REG 30 1471 1472 /* GG82563 Specific Registers */ 1473 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ 1474 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ 1475 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ 1476 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ 1477 1478 /* MAC Specific Control Register */ 1479 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) 1480 1481 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ 1482 1483 /* Page 193 - Port Control Registers */ 1484 /* Kumeran Mode Control */ 1485 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) 1486 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ 1487 1488 /* Page 194 - KMRN Registers */ 1489 #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ 1490 1491 /* MDI Control */ 1492 #define E1000_MDIC_REG_MASK 0x001F0000 1493 #define E1000_MDIC_REG_SHIFT 16 1494 #define E1000_MDIC_PHY_MASK 0x03E00000 1495 #define E1000_MDIC_PHY_SHIFT 21 1496 #define E1000_MDIC_OP_WRITE 0x04000000 1497 #define E1000_MDIC_OP_READ 0x08000000 1498 #define E1000_MDIC_READY 0x10000000 1499 #define E1000_MDIC_ERROR 0x40000000 1500 #define E1000_MDIC_DEST 0x80000000 1501 1502 #define E1000_VFTA_BLOCK_SIZE 8 1503 /* SerDes Control */ 1504 #define E1000_GEN_CTL_READY 0x80000000 1505 #define E1000_GEN_CTL_ADDRESS_SHIFT 8 1506 #define E1000_GEN_POLL_TIMEOUT 640 1507 1508 /* LinkSec register fields */ 1509 #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000 1510 #define E1000_LSECTXCAP_SUM_SHIFT 16 1511 #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000 1512 #define E1000_LSECRXCAP_SUM_SHIFT 16 1513 1514 #define E1000_LSECTXCTRL_EN_MASK 0x00000003 1515 #define E1000_LSECTXCTRL_DISABLE 0x0 1516 #define E1000_LSECTXCTRL_AUTH 0x1 1517 #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 1518 #define E1000_LSECTXCTRL_AISCI 0x00000020 1519 #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 1520 #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8 1521 1522 #define E1000_LSECRXCTRL_EN_MASK 0x0000000C 1523 #define E1000_LSECRXCTRL_EN_SHIFT 2 1524 #define E1000_LSECRXCTRL_DISABLE 0x0 1525 #define E1000_LSECRXCTRL_CHECK 0x1 1526 #define E1000_LSECRXCTRL_STRICT 0x2 1527 #define E1000_LSECRXCTRL_DROP 0x3 1528 #define E1000_LSECRXCTRL_PLSH 0x00000040 1529 #define E1000_LSECRXCTRL_RP 0x00000080 1530 #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 1531 1532 /* Tx Rate-Scheduler Config fields */ 1533 #define E1000_RTTBCNRC_RS_ENA 0x80000000 1534 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF 1535 #define E1000_RTTBCNRC_RF_INT_SHIFT 14 1536 #define E1000_RTTBCNRC_RF_INT_MASK \ 1537 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) 1538 1539 /* DMA Coalescing register fields */ 1540 /* DMA Coalescing Watchdog Timer */ 1541 #define E1000_DMACR_DMACWT_MASK 0x00003FFF 1542 /* DMA Coalescing Rx Threshold */ 1543 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 1544 #define E1000_DMACR_DMACTHR_SHIFT 16 1545 /* Lx when no PCIe transactions */ 1546 #define E1000_DMACR_DMAC_LX_MASK 0x30000000 1547 #define E1000_DMACR_DMAC_LX_SHIFT 28 1548 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 1549 /* DMA Coalescing VM-to-VM Loopback Watchdog Enable */ 1550 #define E1000_DMACR_DC_LPBKW_EN 0x00004000 1551 /* DMA Coalescing BMC-to-OS Watchdog Enable */ 1552 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 1553 1554 /* DMA Coalescing Transmit Threshold */ 1555 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF 1556 1557 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1558 1559 /* Rx Traffic Rate Threshold */ 1560 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF 1561 /* Rx packet rate in current window */ 1562 #define E1000_DMCRTRH_LRPRCW 0x80000000 1563 1564 /* DMA Coal Rx Traffic Current Count */ 1565 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF 1566 1567 /* Flow ctrl Rx Threshold High val */ 1568 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 1569 #define E1000_FCRTC_RTH_COAL_SHIFT 4 1570 /* Lx power decision based on DMA coal */ 1571 #define E1000_PCIEMISC_LX_DECISION 0x00000080 1572 1573 #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ 1574 #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ 1575 #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ 1576 #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 1577 #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 1578 1579 #define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */ 1580 #define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */ 1581 1582 /* Proxy Filter Control */ 1583 #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ 1584 #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ 1585 #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ 1586 #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ 1587 #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ 1588 #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ 1589 #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ 1590 #define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 1591 #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ 1592 /* Proxy Status */ 1593 #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ 1594 1595 /* Firmware Status */ 1596 #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */ 1597 /* VF Control */ 1598 #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */ 1599 1600 #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */ 1601 /* Lan ID bit field offset in status register */ 1602 #define E1000_STATUS_LAN_ID_OFFSET 2 1603 #define E1000_VFTA_ENTRIES 128 1604 #define E1000_UNUSEDARG 1605 #ifndef ERROR_REPORT 1606 #define ERROR_REPORT(fmt) do { } while (0) 1607 #endif /* ERROR_REPORT */ 1608 #endif /* _E1000_DEFINES_H_ */ 1609