1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_DEFINES_H_ 36 #define _E1000_DEFINES_H_ 37 38 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 40 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 41 42 /* Definitions for power management and wakeup registers */ 43 /* Wake Up Control */ 44 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 48 #define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */ 49 #define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */ 50 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 51 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 52 53 /* Wake Up Filter Control */ 54 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 55 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 56 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 57 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 58 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 59 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 60 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 61 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 62 #define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */ 63 #define E1000_WUFC_FLX0_PHY 0x00001000 /* Flexible Filter 0 Enable */ 64 #define E1000_WUFC_FLX1_PHY 0x00002000 /* Flexible Filter 1 Enable */ 65 #define E1000_WUFC_FLX2_PHY 0x00004000 /* Flexible Filter 2 Enable */ 66 #define E1000_WUFC_FLX3_PHY 0x00008000 /* Flexible Filter 3 Enable */ 67 #define E1000_WUFC_FLX4_PHY 0x00000200 /* Flexible Filter 4 Enable */ 68 #define E1000_WUFC_FLX5_PHY 0x00000400 /* Flexible Filter 5 Enable */ 69 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 70 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 71 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 72 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 73 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 74 #define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 75 #define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 76 #define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /*Mask for all wakeup filters*/ 77 #define E1000_WUFC_FLX_OFFSET_PHY 12 /* Offset to the Flexible Filters bits */ 78 #define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /*Mask for 4 flexible filters*/ 79 #define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /*Mask for 6 wakeup filters */ 80 #define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /*Mask for 6 flexible filters*/ 81 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 82 #define E1000_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask for all 6 wakeup filters*/ 83 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 84 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /*Mask for the 4 flexible filters */ 85 #define E1000_WUFC_FLX_FILTERS_6 0x003F0000 /* Mask for 6 flexible filters */ 86 /* 87 * For 82576 to utilize Extended filter masks in addition to 88 * existing (filter) masks 89 */ 90 #define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */ 91 92 /* Wake Up Status */ 93 #define E1000_WUS_LNKC E1000_WUFC_LNKC 94 #define E1000_WUS_MAG E1000_WUFC_MAG 95 #define E1000_WUS_EX E1000_WUFC_EX 96 #define E1000_WUS_MC E1000_WUFC_MC 97 #define E1000_WUS_BC E1000_WUFC_BC 98 #define E1000_WUS_ARP E1000_WUFC_ARP 99 #define E1000_WUS_IPV4 E1000_WUFC_IPV4 100 #define E1000_WUS_IPV6 E1000_WUFC_IPV6 101 #define E1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY 102 #define E1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY 103 #define E1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY 104 #define E1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY 105 #define E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4 106 #define E1000_WUS_FLX0 E1000_WUFC_FLX0 107 #define E1000_WUS_FLX1 E1000_WUFC_FLX1 108 #define E1000_WUS_FLX2 E1000_WUFC_FLX2 109 #define E1000_WUS_FLX3 E1000_WUFC_FLX3 110 #define E1000_WUS_FLX4 E1000_WUFC_FLX4 111 #define E1000_WUS_FLX5 E1000_WUFC_FLX5 112 #define E1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY 113 #define E1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY 114 #define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS 115 #define E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6 116 #define E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6 117 118 /* Wake Up Packet Length */ 119 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 120 121 /* Four Flexible Filters are supported */ 122 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 123 /* Six Flexible Filters are supported */ 124 #define E1000_FLEXIBLE_FILTER_COUNT_MAX_6 6 125 /* Two Extended Flexible Filters are supported (82576) */ 126 #define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 127 #define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 128 #define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 129 130 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 131 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 132 133 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 134 #define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6 135 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 136 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 137 138 /* Extended Device Control */ 139 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 140 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 141 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 142 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 143 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 144 /* Reserved (bits 4,5) in >= 82575 */ 145 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */ 146 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */ 147 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 148 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */ 149 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ 150 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ 151 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 152 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 153 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 154 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ 155 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 156 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 157 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 158 /* Physical Func Reset Done Indication */ 159 #define E1000_CTRL_EXT_PFRSTD 0x00004000 160 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 161 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 162 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 163 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 164 #define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/ 165 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 166 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 167 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 168 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 169 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 170 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 171 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 172 #define E1000_CTRL_EXT_EIAME 0x01000000 173 #define E1000_CTRL_EXT_IRCA 0x00000001 174 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 175 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 176 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 177 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 178 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 179 #define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */ 180 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 181 /* IAME enable bit (27) was removed in >= 82575 */ 182 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int acknowledge Auto-mask */ 183 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error 184 * detection enabled */ 185 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity 186 * error detection enable */ 187 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 188 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 189 #define E1000_CTRL_EXT_LSECCK 0x00001000 190 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 191 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 192 #define E1000_I2CCMD_REG_ADDR 0x00FF0000 193 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 194 #define E1000_I2CCMD_PHY_ADDR 0x07000000 195 #define E1000_I2CCMD_OPCODE_READ 0x08000000 196 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 197 #define E1000_I2CCMD_RESET 0x10000000 198 #define E1000_I2CCMD_READY 0x20000000 199 #define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 200 #define E1000_I2CCMD_ERROR 0x80000000 201 #define E1000_MAX_SGMII_PHY_REG_ADDR 255 202 #define E1000_I2CCMD_PHY_TIMEOUT 200 203 #define E1000_IVAR_VALID 0x80 204 #define E1000_GPIE_NSICR 0x00000001 205 #define E1000_GPIE_MSIX_MODE 0x00000010 206 #define E1000_GPIE_EIAME 0x40000000 207 #define E1000_GPIE_PBA 0x80000000 208 209 /* Receive Descriptor bit definitions */ 210 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 211 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 212 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 213 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 214 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 215 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 216 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 217 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 218 #define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 219 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 220 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 221 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 222 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 223 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 224 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 225 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 226 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 227 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 228 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 229 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 230 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 231 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 232 #define E1000_RXD_SPC_PRI_SHIFT 13 233 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 234 #define E1000_RXD_SPC_CFI_SHIFT 12 235 236 #define E1000_RXDEXT_STATERR_CE 0x01000000 237 #define E1000_RXDEXT_STATERR_SE 0x02000000 238 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 239 #define E1000_RXDEXT_STATERR_CXE 0x10000000 240 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 241 #define E1000_RXDEXT_STATERR_IPE 0x40000000 242 #define E1000_RXDEXT_STATERR_RXE 0x80000000 243 244 #define E1000_RXDEXT_LSECH 0x01000000 245 #define E1000_RXDEXT_LSECE_MASK 0x60000000 246 #define E1000_RXDEXT_LSECE_NO_ERROR 0x00000000 247 #define E1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000 248 #define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000 249 #define E1000_RXDEXT_LSECE_BAD_SIG 0x60000000 250 251 /* mask to determine if packets should be dropped due to frame errors */ 252 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 253 E1000_RXD_ERR_CE | \ 254 E1000_RXD_ERR_SE | \ 255 E1000_RXD_ERR_SEQ | \ 256 E1000_RXD_ERR_CXE | \ 257 E1000_RXD_ERR_RXE) 258 259 /* Same mask, but for extended and packet split descriptors */ 260 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 261 E1000_RXDEXT_STATERR_CE | \ 262 E1000_RXDEXT_STATERR_SE | \ 263 E1000_RXDEXT_STATERR_SEQ | \ 264 E1000_RXDEXT_STATERR_CXE | \ 265 E1000_RXDEXT_STATERR_RXE) 266 267 #define E1000_MRQC_ENABLE_MASK 0x00000007 268 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 269 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004 270 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 271 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 272 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 273 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 274 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 275 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 276 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 277 278 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 279 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 280 281 /* Management Control */ 282 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 283 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 284 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 285 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 286 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 287 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 288 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 289 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 290 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 291 /* Enable Neighbor Discovery Filtering */ 292 #define E1000_MANC_NEIGHBOR_EN 0x00004000 293 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 294 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 295 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 296 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 297 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 298 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 299 /* Enable MAC address filtering */ 300 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 301 /* Enable MNG packets to host memory */ 302 #define E1000_MANC_EN_MNG2HOST 0x00200000 303 /* Enable IP address filtering */ 304 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 305 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 306 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 307 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 308 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 309 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 310 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 311 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 312 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 313 314 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 315 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 316 317 /* Receive Control */ 318 #define E1000_RCTL_RST 0x00000001 /* Software reset */ 319 #define E1000_RCTL_EN 0x00000002 /* enable */ 320 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 321 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ 322 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ 323 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 324 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 325 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 326 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 327 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 328 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 329 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 330 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min thresh size */ 331 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min thresh size */ 332 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min thresh size */ 333 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 334 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 335 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 336 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 337 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 338 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 339 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 340 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 341 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 342 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 343 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 344 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 345 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 346 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 347 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 348 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 349 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 350 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 351 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 352 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 353 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 354 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 355 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 356 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 357 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 358 359 /* 360 * Use byte values for the following shift parameters 361 * Usage: 362 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 363 * E1000_PSRCTL_BSIZE0_MASK) | 364 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 365 * E1000_PSRCTL_BSIZE1_MASK) | 366 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 367 * E1000_PSRCTL_BSIZE2_MASK) | 368 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 369 * E1000_PSRCTL_BSIZE3_MASK)) 370 * where value0 = [128..16256], default=256 371 * value1 = [1024..64512], default=4096 372 * value2 = [0..64512], default=4096 373 * value3 = [0..64512], default=0 374 */ 375 376 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 377 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 378 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 379 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 380 381 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 382 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 383 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 384 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 385 386 /* SWFW_SYNC Definitions */ 387 #define E1000_SWFW_EEP_SM 0x01 388 #define E1000_SWFW_PHY0_SM 0x02 389 #define E1000_SWFW_PHY1_SM 0x04 390 #define E1000_SWFW_CSR_SM 0x08 391 #define E1000_SWFW_PHY2_SM 0x20 392 #define E1000_SWFW_PHY3_SM 0x40 393 394 /* FACTPS Definitions */ 395 #define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */ 396 /* Device Control */ 397 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 398 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 399 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 400 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ 401 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 402 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 403 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 404 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 405 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 406 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 407 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 408 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 409 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 410 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 411 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 412 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 413 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 414 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 415 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock 416 * indication in SDP[0] */ 417 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through 418 * PHYRST_N pin */ 419 #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external 420 * LINK_0 and LINK_1 pins */ 421 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 422 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 423 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 424 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 425 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 426 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 427 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 428 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 429 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 430 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 431 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 432 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 433 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 434 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 435 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 436 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */ 437 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 438 439 /* 440 * Bit definitions for the Management Data IO (MDIO) and Management Data 441 * Clock (MDC) pins in the Device Control Register. 442 */ 443 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 444 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 445 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 446 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 447 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 448 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 449 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 450 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 451 452 #define E1000_CONNSW_ENRGSRC 0x4 453 #define E1000_PCS_CFG_PCS_EN 8 454 #define E1000_PCS_LCTL_FLV_LINK_UP 1 455 #define E1000_PCS_LCTL_FSV_10 0 456 #define E1000_PCS_LCTL_FSV_100 2 457 #define E1000_PCS_LCTL_FSV_1000 4 458 #define E1000_PCS_LCTL_FDV_FULL 8 459 #define E1000_PCS_LCTL_FSD 0x10 460 #define E1000_PCS_LCTL_FORCE_LINK 0x20 461 #define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 462 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 463 #define E1000_PCS_LCTL_AN_ENABLE 0x10000 464 #define E1000_PCS_LCTL_AN_RESTART 0x20000 465 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 466 #define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 467 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 468 #define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 469 #define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 470 #define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 471 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 472 473 #define E1000_PCS_LSTS_LINK_OK 1 474 #define E1000_PCS_LSTS_SPEED_10 0 475 #define E1000_PCS_LSTS_SPEED_100 2 476 #define E1000_PCS_LSTS_SPEED_1000 4 477 #define E1000_PCS_LSTS_DUPLEX_FULL 8 478 #define E1000_PCS_LSTS_SYNK_OK 0x10 479 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 480 #define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 481 #define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 482 #define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 483 #define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 484 485 /* Device Status */ 486 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 487 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 488 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 489 #define E1000_STATUS_FUNC_SHIFT 2 490 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 491 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 492 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 493 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 494 #define E1000_STATUS_SPEED_MASK 0x000000C0 495 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 496 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 497 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 498 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 499 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 500 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 501 #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. 502 * Clear on write '0'. */ 503 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ 504 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 505 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 506 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 507 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 508 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 509 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ 510 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 511 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 512 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 513 #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution 514 * disabled */ 515 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 516 #define E1000_STATUS_FUSE_8 0x04000000 517 #define E1000_STATUS_FUSE_9 0x08000000 518 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ 519 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ 520 521 /* Constants used to interpret the masked PCI-X bus speed. */ 522 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 523 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 524 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/ 525 526 #define SPEED_10 10 527 #define SPEED_100 100 528 #define SPEED_1000 1000 529 #define HALF_DUPLEX 1 530 #define FULL_DUPLEX 2 531 532 #define PHY_FORCE_TIME 20 533 534 #define ADVERTISE_10_HALF 0x0001 535 #define ADVERTISE_10_FULL 0x0002 536 #define ADVERTISE_100_HALF 0x0004 537 #define ADVERTISE_100_FULL 0x0008 538 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 539 #define ADVERTISE_1000_FULL 0x0020 540 541 /* 1000/H is not supported, nor spec-compliant. */ 542 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 543 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 544 ADVERTISE_1000_FULL) 545 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 546 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 547 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 548 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 549 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ 550 ADVERTISE_1000_FULL) 551 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 552 553 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 554 555 /* LED Control */ 556 #define E1000_PHY_LED0_MODE_MASK 0x00000007 557 #define E1000_PHY_LED0_IVRT 0x00000008 558 #define E1000_PHY_LED0_BLINK 0x00000010 559 #define E1000_PHY_LED0_MASK 0x0000001F 560 561 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 562 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 563 #define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 564 #define E1000_LEDCTL_LED0_IVRT 0x00000040 565 #define E1000_LEDCTL_LED0_BLINK 0x00000080 566 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 567 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 568 #define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 569 #define E1000_LEDCTL_LED1_IVRT 0x00004000 570 #define E1000_LEDCTL_LED1_BLINK 0x00008000 571 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 572 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 573 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 574 #define E1000_LEDCTL_LED2_IVRT 0x00400000 575 #define E1000_LEDCTL_LED2_BLINK 0x00800000 576 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 577 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 578 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 579 #define E1000_LEDCTL_LED3_IVRT 0x40000000 580 #define E1000_LEDCTL_LED3_BLINK 0x80000000 581 582 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 583 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 584 #define E1000_LEDCTL_MODE_LINK_UP 0x2 585 #define E1000_LEDCTL_MODE_ACTIVITY 0x3 586 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 587 #define E1000_LEDCTL_MODE_LINK_10 0x5 588 #define E1000_LEDCTL_MODE_LINK_100 0x6 589 #define E1000_LEDCTL_MODE_LINK_1000 0x7 590 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 591 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 592 #define E1000_LEDCTL_MODE_COLLISION 0xA 593 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 594 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 595 #define E1000_LEDCTL_MODE_PAUSED 0xD 596 #define E1000_LEDCTL_MODE_LED_ON 0xE 597 #define E1000_LEDCTL_MODE_LED_OFF 0xF 598 599 /* Transmit Descriptor bit definitions */ 600 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 601 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 602 #define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */ 603 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 604 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 605 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 606 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 607 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 608 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 609 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 610 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 611 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 612 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 613 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 614 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 615 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 616 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 617 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 618 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 619 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 620 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 621 /* Extended desc bits for Linksec and timesync */ 622 #define E1000_TXD_CMD_LINKSEC 0x10000000 /* Apply LinkSec on packet */ 623 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 624 625 /* Transmit Control */ 626 #define E1000_TCTL_RST 0x00000001 /* software reset */ 627 #define E1000_TCTL_EN 0x00000002 /* enable tx */ 628 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 629 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 630 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 631 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 632 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 633 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 634 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 635 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 636 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 637 638 /* Transmit Arbitration Count */ 639 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 640 641 /* SerDes Control */ 642 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 643 644 /* Receive Checksum Control */ 645 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 646 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 647 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 648 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 649 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 650 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 651 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 652 653 /* Header split receive */ 654 #define E1000_RFCTL_ISCSI_DIS 0x00000001 655 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E 656 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1 657 #define E1000_RFCTL_NFSW_DIS 0x00000040 658 #define E1000_RFCTL_NFSR_DIS 0x00000080 659 #define E1000_RFCTL_NFS_VER_MASK 0x00000300 660 #define E1000_RFCTL_NFS_VER_SHIFT 8 661 #define E1000_RFCTL_IPV6_DIS 0x00000400 662 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 663 #define E1000_RFCTL_ACK_DIS 0x00001000 664 #define E1000_RFCTL_ACKD_DIS 0x00002000 665 #define E1000_RFCTL_IPFRSP_DIS 0x00004000 666 #define E1000_RFCTL_EXTEN 0x00008000 667 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 668 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 669 #define E1000_RFCTL_LEF 0x00040000 670 671 /* Collision related configuration parameters */ 672 #define E1000_COLLISION_THRESHOLD 15 673 #define E1000_CT_SHIFT 4 674 #define E1000_COLLISION_DISTANCE 63 675 #define E1000_COLD_SHIFT 12 676 677 /* Default values for the transmit IPG register */ 678 #define DEFAULT_82542_TIPG_IPGT 10 679 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 680 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 681 682 #define E1000_TIPG_IPGT_MASK 0x000003FF 683 #define E1000_TIPG_IPGR1_MASK 0x000FFC00 684 #define E1000_TIPG_IPGR2_MASK 0x3FF00000 685 686 #define DEFAULT_82542_TIPG_IPGR1 2 687 #define DEFAULT_82543_TIPG_IPGR1 8 688 #define E1000_TIPG_IPGR1_SHIFT 10 689 690 #define DEFAULT_82542_TIPG_IPGR2 10 691 #define DEFAULT_82543_TIPG_IPGR2 6 692 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 693 #define E1000_TIPG_IPGR2_SHIFT 20 694 695 /* Ethertype field values */ 696 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 697 698 #define ETHERNET_FCS_SIZE 4 699 #define MAX_JUMBO_FRAME_SIZE 0x3F00 700 701 /* Extended Configuration Control and Size */ 702 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 703 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 704 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 705 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 706 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 707 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 708 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 709 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 710 711 #define E1000_PHY_CTRL_SPD_EN 0x00000001 712 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 713 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 714 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 715 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 716 717 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 718 719 /* PBA constants */ 720 #define E1000_PBA_6K 0x0006 /* 6KB */ 721 #define E1000_PBA_8K 0x0008 /* 8KB */ 722 #define E1000_PBA_10K 0x000A /* 10KB */ 723 #define E1000_PBA_12K 0x000C /* 12KB */ 724 #define E1000_PBA_14K 0x000E /* 14KB */ 725 #define E1000_PBA_16K 0x0010 /* 16KB */ 726 #define E1000_PBA_18K 0x0012 727 #define E1000_PBA_20K 0x0014 728 #define E1000_PBA_22K 0x0016 729 #define E1000_PBA_24K 0x0018 730 #define E1000_PBA_26K 0x001A 731 #define E1000_PBA_30K 0x001E 732 #define E1000_PBA_32K 0x0020 733 #define E1000_PBA_34K 0x0022 734 #define E1000_PBA_35K 0x0023 735 #define E1000_PBA_38K 0x0026 736 #define E1000_PBA_40K 0x0028 737 #define E1000_PBA_48K 0x0030 /* 48KB */ 738 #define E1000_PBA_64K 0x0040 /* 64KB */ 739 740 #define E1000_PBS_16K E1000_PBA_16K 741 #define E1000_PBS_24K E1000_PBA_24K 742 743 #define IFS_MAX 80 744 #define IFS_MIN 40 745 #define IFS_RATIO 4 746 #define IFS_STEP 10 747 #define MIN_NUM_XMITS 1000 748 749 /* SW Semaphore Register */ 750 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 751 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 752 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 753 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 754 755 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 756 757 /* Interrupt Cause Read */ 758 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 759 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 760 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 761 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 762 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 763 #define E1000_ICR_RXO 0x00000040 /* rx overrun */ 764 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 765 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 766 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 767 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 768 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 769 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 770 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 771 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 772 #define E1000_ICR_TXD_LOW 0x00008000 773 #define E1000_ICR_SRPD 0x00010000 774 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 775 #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 776 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 777 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 778 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver 779 * should claim the interrupt */ 780 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ 781 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ 782 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ 783 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 784 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ 785 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ 786 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 787 #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW 788 * bit in the FWSM */ 789 #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates 790 * an interrupt */ 791 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 792 #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ 793 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 794 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 795 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 796 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 797 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 798 #define E1000_ICR_FER 0x00400000 /* Fatal Error */ 799 800 /* PBA ECC Register */ 801 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 802 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 803 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 804 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 805 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 806 807 /* Extended Interrupt Cause Read */ 808 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 809 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 810 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 811 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 812 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 813 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 814 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 815 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 816 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 817 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 818 /* TCP Timer */ 819 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ 820 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 821 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 822 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ 823 824 /* 825 * This defines the bits that are set in the Interrupt Mask 826 * Set/Read Register. Each bit is documented below: 827 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 828 * o RXSEQ = Receive Sequence Error 829 */ 830 #define POLL_IMS_ENABLE_MASK ( \ 831 E1000_IMS_RXDMT0 | \ 832 E1000_IMS_RXSEQ) 833 834 /* 835 * This defines the bits that are set in the Interrupt Mask 836 * Set/Read Register. Each bit is documented below: 837 * o RXT0 = Receiver Timer Interrupt (ring 0) 838 * o TXDW = Transmit Descriptor Written Back 839 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 840 * o RXSEQ = Receive Sequence Error 841 * o LSC = Link Status Change 842 */ 843 #define IMS_ENABLE_MASK ( \ 844 E1000_IMS_RXT0 | \ 845 E1000_IMS_TXDW | \ 846 E1000_IMS_RXDMT0 | \ 847 E1000_IMS_RXSEQ | \ 848 E1000_IMS_LSC) 849 850 /* Interrupt Mask Set */ 851 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */ 852 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 853 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 854 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 855 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 856 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 857 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 858 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 859 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 860 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ 861 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 862 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 863 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 864 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 865 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 866 #define E1000_IMS_SRPD E1000_ICR_SRPD 867 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 868 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 869 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 870 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 871 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO 872 * parity error */ 873 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO 874 * parity error */ 875 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer 876 * parity error */ 877 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity 878 * error */ 879 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO 880 * parity error */ 881 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO 882 * parity error */ 883 #define E1000_IMS_DSW E1000_ICR_DSW 884 #define E1000_IMS_PHYINT E1000_ICR_PHYINT 885 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 886 #define E1000_IMS_EPRST E1000_ICR_EPRST 887 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 888 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 889 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 890 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 891 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 892 #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */ 893 894 /* Extended Interrupt Mask Set */ 895 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 896 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 897 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 898 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 899 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 900 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 901 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 902 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 903 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 904 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 905 906 /* Interrupt Cause Set */ 907 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */ 908 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 909 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 910 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 911 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 912 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 913 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 914 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 915 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ 916 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 917 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 918 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 919 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 920 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 921 #define E1000_ICS_SRPD E1000_ICR_SRPD 922 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 923 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 924 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 925 #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ 926 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO 927 * parity error */ 928 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO 929 * parity error */ 930 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer 931 * parity error */ 932 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity 933 * error */ 934 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO 935 * parity error */ 936 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO 937 * parity error */ 938 #define E1000_ICS_DSW E1000_ICR_DSW 939 #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 940 #define E1000_ICS_PHYINT E1000_ICR_PHYINT 941 #define E1000_ICS_EPRST E1000_ICR_EPRST 942 943 /* Extended Interrupt Cause Set */ 944 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 945 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 946 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 947 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 948 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 949 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 950 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 951 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 952 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 953 #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 954 955 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF 956 957 /* Transmit Descriptor Control */ 958 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 959 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 960 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 961 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 962 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 963 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 964 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 965 /* Enable the counting of descriptors still to be processed. */ 966 #define E1000_TXDCTL_COUNT_DESC 0x00400000 967 968 /* Flow Control Constants */ 969 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 970 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 971 #define FLOW_CONTROL_TYPE 0x8808 972 973 /* 802.1q VLAN Packet Size */ 974 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 975 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 976 977 /* Receive Address */ 978 /* 979 * Number of high/low register pairs in the RAR. The RAR (Receive Address 980 * Registers) holds the directed and multicast addresses that we monitor. 981 * Technically, we have 16 spots. However, we reserve one of these spots 982 * (RAR[15]) for our directed address used by controllers with 983 * manageability enabled, allowing us room for 15 multicast addresses. 984 */ 985 #define E1000_RAR_ENTRIES 15 986 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 987 #define E1000_RAL_MAC_ADDR_LEN 4 988 #define E1000_RAH_MAC_ADDR_LEN 2 989 #define E1000_RAH_POOL_MASK 0x03FC0000 990 #define E1000_RAH_POOL_1 0x00040000 991 992 /* Error Codes */ 993 #define E1000_SUCCESS 0 994 #define E1000_ERR_NVM 1 995 #define E1000_ERR_PHY 2 996 #define E1000_ERR_CONFIG 3 997 #define E1000_ERR_PARAM 4 998 #define E1000_ERR_MAC_INIT 5 999 #define E1000_ERR_PHY_TYPE 6 1000 #define E1000_ERR_RESET 9 1001 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 1002 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 1003 #define E1000_BLK_PHY_RESET 12 1004 #define E1000_ERR_SWFW_SYNC 13 1005 #define E1000_NOT_IMPLEMENTED 14 1006 #define E1000_ERR_MBX 15 1007 #define E1000_ERFUSE_FAILURE 16 1008 1009 /* Loop limit on how long we wait for auto-negotiation to complete */ 1010 #define FIBER_LINK_UP_LIMIT 50 1011 #define COPPER_LINK_UP_LIMIT 10 1012 #define PHY_AUTO_NEG_LIMIT 45 1013 #define PHY_FORCE_LIMIT 20 1014 /* Number of 100 microseconds we wait for PCI Express master disable */ 1015 #define MASTER_DISABLE_TIMEOUT 800 1016 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 1017 #define PHY_CFG_TIMEOUT 100 1018 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 1019 #define MDIO_OWNERSHIP_TIMEOUT 10 1020 /* Number of milliseconds for NVM auto read done after MAC reset. */ 1021 #define AUTO_READ_DONE_TIMEOUT 10 1022 1023 /* Flow Control */ 1024 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 1025 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 1026 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1027 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1028 1029 /* Transmit Configuration Word */ 1030 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1031 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 1032 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 1033 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 1034 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 1035 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 1036 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 1037 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 1038 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 1039 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 1040 1041 /* Receive Configuration Word */ 1042 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1043 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1044 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1045 #define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1046 #define E1000_RXCW_C 0x20000000 /* Receive config */ 1047 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1048 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1049 1050 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ 1051 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ 1052 1053 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */ 1054 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */ 1055 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 1056 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 1057 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 1058 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 1059 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 1060 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */ 1061 1062 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 1063 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 1064 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 1065 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 1066 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 1067 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 1068 1069 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 1070 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 1071 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 1072 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 1073 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 1074 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 1075 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 1076 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 1077 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 1078 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 1079 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 1080 1081 #define E1000_TIMINCA_16NS_SHIFT 24 1082 /* TUPLE Filtering Configuration */ 1083 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ 1084 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ 1085 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ 1086 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */ 1087 #define E1000_TTQF_PROTOCOL_TCP 0x0 1088 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 1089 #define E1000_TTQF_PROTOCOL_UDP 0x1 1090 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 1091 #define E1000_TTQF_PROTOCOL_SCTP 0x2 1092 #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ 1093 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ 1094 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ 1095 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ 1096 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 1097 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 1098 #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 1099 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 1100 1101 /* PCI Express Control */ 1102 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 1103 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 1104 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 1105 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 1106 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 1107 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 1108 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 1109 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 1110 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 1111 #define E1000_GCR_CAP_VER2 0x00040000 1112 1113 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 1114 E1000_GCR_RXDSCW_NO_SNOOP | \ 1115 E1000_GCR_RXDSCR_NO_SNOOP | \ 1116 E1000_GCR_TXD_NO_SNOOP | \ 1117 E1000_GCR_TXDSCW_NO_SNOOP | \ 1118 E1000_GCR_TXDSCR_NO_SNOOP) 1119 1120 /* PHY Control Register */ 1121 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1122 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 1123 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 1124 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 1125 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 1126 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 1127 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 1128 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1129 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 1130 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 1131 #define MII_CR_SPEED_1000 0x0040 1132 #define MII_CR_SPEED_100 0x2000 1133 #define MII_CR_SPEED_10 0x0000 1134 1135 /* PHY Status Register */ 1136 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 1137 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 1138 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 1139 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 1140 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 1141 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 1142 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 1143 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 1144 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 1145 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 1146 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 1147 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 1148 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 1149 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 1150 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 1151 1152 /* Autoneg Advertisement Register */ 1153 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 1154 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 1155 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 1156 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 1157 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 1158 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 1159 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 1160 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 1161 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 1162 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1163 1164 /* Link Partner Ability Register (Base Page) */ 1165 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 1166 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 1167 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 1168 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 1169 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 1170 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 1171 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 1172 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 1173 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 1174 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 1175 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1176 1177 /* Autoneg Expansion Register */ 1178 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 1179 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 1180 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 1181 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 1182 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 1183 1184 /* 1000BASE-T Control Register */ 1185 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 1186 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 1187 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 1188 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 1189 /* 0=DTE device */ 1190 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 1191 /* 0=Configure PHY as Slave */ 1192 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 1193 /* 0=Automatic Master/Slave config */ 1194 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 1195 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 1196 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 1197 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 1198 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 1199 1200 /* 1000BASE-T Status Register */ 1201 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 1202 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 1203 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 1204 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 1205 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 1206 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 1207 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */ 1208 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 1209 1210 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 1211 1212 /* PHY 1000 MII Register/Bit Definitions */ 1213 /* PHY Registers defined by IEEE */ 1214 #define PHY_CONTROL 0x00 /* Control Register */ 1215 #define PHY_STATUS 0x01 /* Status Register */ 1216 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 1217 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 1218 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 1219 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 1220 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 1221 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ 1222 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 1223 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 1224 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 1225 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 1226 1227 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 1228 1229 /* NVM Control */ 1230 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 1231 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 1232 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 1233 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 1234 #define E1000_EECD_FWE_MASK 0x00000030 1235 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1236 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1237 #define E1000_EECD_FWE_SHIFT 4 1238 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 1239 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 1240 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 1241 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 1242 /* NVM Addressing bits based on type 0=small, 1=large */ 1243 #define E1000_EECD_ADDR_BITS 0x00000400 1244 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ 1245 #ifndef E1000_NVM_GRANT_ATTEMPTS 1246 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 1247 #endif 1248 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 1249 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 1250 #define E1000_EECD_SIZE_EX_SHIFT 11 1251 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1252 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1253 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1254 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1255 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 1256 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1257 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1258 #define E1000_EECD_SECVAL_SHIFT 22 1259 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 1260 1261 #define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ 1262 #define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ 1263 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 1264 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1265 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 1266 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1267 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1268 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1269 #define E1000_FLASH_UPDATES 2000 1270 1271 /* NVM Word Offsets */ 1272 #define NVM_COMPAT 0x0003 1273 #define NVM_ID_LED_SETTINGS 0x0004 1274 #define NVM_VERSION 0x0005 1275 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ 1276 #define NVM_PHY_CLASS_WORD 0x0007 1277 #define NVM_INIT_CONTROL1_REG 0x000A 1278 #define NVM_INIT_CONTROL2_REG 0x000F 1279 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 1280 #define NVM_INIT_CONTROL3_PORT_B 0x0014 1281 #define NVM_INIT_3GIO_3 0x001A 1282 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1283 #define NVM_INIT_CONTROL3_PORT_A 0x0024 1284 #define NVM_CFG 0x0012 1285 #define NVM_FLASH_VERSION 0x0032 1286 #define NVM_ALT_MAC_ADDR_PTR 0x0037 1287 #define NVM_CHECKSUM_REG 0x003F 1288 1289 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 1290 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 1291 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 1292 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 1293 1294 #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) 1295 1296 /* Mask bits for fields in Word 0x0f of the NVM */ 1297 #define NVM_WORD0F_PAUSE_MASK 0x3000 1298 #define NVM_WORD0F_PAUSE 0x1000 1299 #define NVM_WORD0F_ASM_DIR 0x2000 1300 #define NVM_WORD0F_ANE 0x0800 1301 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1302 #define NVM_WORD0F_LPLU 0x0001 1303 1304 /* Mask bits for fields in Word 0x1a of the NVM */ 1305 #define NVM_WORD1A_ASPM_MASK 0x000C 1306 1307 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 1308 #define NVM_SUM 0xBABA 1309 1310 #define NVM_MAC_ADDR_OFFSET 0 1311 #define NVM_PBA_OFFSET_0 8 1312 #define NVM_PBA_OFFSET_1 9 1313 #define NVM_RESERVED_WORD 0xFFFF 1314 #define NVM_PHY_CLASS_A 0x8000 1315 #define NVM_SERDES_AMPLITUDE_MASK 0x000F 1316 #define NVM_SIZE_MASK 0x1C00 1317 #define NVM_SIZE_SHIFT 10 1318 #define NVM_WORD_SIZE_BASE_SHIFT 6 1319 #define NVM_SWDPIO_EXT_SHIFT 4 1320 1321 /* NVM Commands - Microwire */ 1322 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 1323 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 1324 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 1325 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 1326 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ 1327 1328 /* NVM Commands - SPI */ 1329 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1330 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 1331 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 1332 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1333 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 1334 #define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */ 1335 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 1336 #define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */ 1337 1338 /* SPI NVM Status Register */ 1339 #define NVM_STATUS_RDY_SPI 0x01 1340 #define NVM_STATUS_WEN_SPI 0x02 1341 #define NVM_STATUS_BP0_SPI 0x04 1342 #define NVM_STATUS_BP1_SPI 0x08 1343 #define NVM_STATUS_WPEN_SPI 0x80 1344 1345 /* Word definitions for ID LED Settings */ 1346 #define ID_LED_RESERVED_0000 0x0000 1347 #define ID_LED_RESERVED_FFFF 0xFFFF 1348 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1349 (ID_LED_OFF1_OFF2 << 8) | \ 1350 (ID_LED_DEF1_DEF2 << 4) | \ 1351 (ID_LED_DEF1_DEF2)) 1352 #define ID_LED_DEF1_DEF2 0x1 1353 #define ID_LED_DEF1_ON2 0x2 1354 #define ID_LED_DEF1_OFF2 0x3 1355 #define ID_LED_ON1_DEF2 0x4 1356 #define ID_LED_ON1_ON2 0x5 1357 #define ID_LED_ON1_OFF2 0x6 1358 #define ID_LED_OFF1_DEF2 0x7 1359 #define ID_LED_OFF1_ON2 0x8 1360 #define ID_LED_OFF1_OFF2 0x9 1361 1362 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1363 #define IGP_ACTIVITY_LED_ENABLE 0x0300 1364 #define IGP_LED3_MODE 0x07000000 1365 1366 /* PCI/PCI-X/PCI-EX Config space */ 1367 #define PCIX_COMMAND_REGISTER 0xE6 1368 #define PCIX_STATUS_REGISTER_LO 0xE8 1369 #define PCIX_STATUS_REGISTER_HI 0xEA 1370 #define PCI_HEADER_TYPE_REGISTER 0x0E 1371 #define PCIE_LINK_STATUS 0x12 1372 #define PCIE_DEVICE_CONTROL2 0x28 1373 1374 #define PCIX_COMMAND_MMRBC_MASK 0x000C 1375 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1376 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1377 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1378 #define PCIX_STATUS_HI_MMRBC_4K 0x3 1379 #define PCIX_STATUS_HI_MMRBC_2K 0x2 1380 #define PCIX_STATUS_LO_FUNC_MASK 0x7 1381 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 1382 #define PCIE_LINK_WIDTH_MASK 0x3F0 1383 #define PCIE_LINK_WIDTH_SHIFT 4 1384 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 1385 1386 #ifndef ETH_ADDR_LEN 1387 #define ETH_ADDR_LEN 6 1388 #endif 1389 1390 #define PHY_REVISION_MASK 0xFFFFFFF0 1391 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1392 #define MAX_PHY_MULTI_PAGE_REG 0xF 1393 1394 /* Bit definitions for valid PHY IDs. */ 1395 /* 1396 * I = Integrated 1397 * E = External 1398 */ 1399 #define M88E1000_E_PHY_ID 0x01410C50 1400 #define M88E1000_I_PHY_ID 0x01410C30 1401 #define M88E1011_I_PHY_ID 0x01410C20 1402 #define IGP01E1000_I_PHY_ID 0x02A80380 1403 #define M88E1011_I_REV_4 0x04 1404 #define M88E1111_I_PHY_ID 0x01410CC0 1405 #define GG82563_E_PHY_ID 0x01410CA0 1406 #define IGP03E1000_E_PHY_ID 0x02A80390 1407 #define IFE_E_PHY_ID 0x02A80330 1408 #define IFE_PLUS_E_PHY_ID 0x02A80320 1409 #define IFE_C_E_PHY_ID 0x02A80310 1410 #define BME1000_E_PHY_ID 0x01410CB0 1411 #define BME1000_E_PHY_ID_R2 0x01410CB1 1412 #define I82577_E_PHY_ID 0x01540050 1413 #define I82578_E_PHY_ID 0x004DD040 1414 #define I82580_I_PHY_ID 0x015403A0 1415 #define IGP04E1000_E_PHY_ID 0x02A80391 1416 #define M88_VENDOR 0x0141 1417 1418 /* M88E1000 Specific Registers */ 1419 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 1420 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 1421 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 1422 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 1423 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 1424 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1425 1426 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 1427 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 1428 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 1429 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 1430 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 1431 1432 /* M88E1000 PHY Specific Control Register */ 1433 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 1434 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ 1435 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 1436 /* 1=CLK125 low, 0=CLK125 toggling */ 1437 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 1438 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 1439 /* Manual MDI configuration */ 1440 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1441 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 1442 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 1443 /* Auto crossover enabled all speeds */ 1444 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 1445 /* 1446 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold 1447 * 0=Normal 10BASE-T Rx Threshold 1448 */ 1449 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 1450 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 1451 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 1452 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 1453 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 1454 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ 1455 1456 /* M88E1000 PHY Specific Status Register */ 1457 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 1458 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1459 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1460 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1461 /* 1462 * 0 = <50M 1463 * 1 = 50-80M 1464 * 2 = 80-110M 1465 * 3 = 110-140M 1466 * 4 = >140M 1467 */ 1468 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 1469 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1470 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1471 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 1472 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1473 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1474 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 1475 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1476 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1477 1478 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1479 1480 /* M88E1000 Extended PHY Specific Control Register */ 1481 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 1482 /* 1483 * 1 = Lost lock detect enabled. 1484 * Will assert lost lock and bring 1485 * link down if idle not seen 1486 * within 1ms in 1000BASE-T 1487 */ 1488 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 1489 /* 1490 * Number of times we will attempt to autonegotiate before downshifting if we 1491 * are the master 1492 */ 1493 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1494 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1495 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 1496 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 1497 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 1498 /* 1499 * Number of times we will attempt to autonegotiate before downshifting if we 1500 * are the slave 1501 */ 1502 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1503 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 1504 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1505 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 1506 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 1507 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 1508 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1509 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 1510 1511 /* M88EC018 Rev 2 specific DownShift settings */ 1512 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1513 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 1514 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 1515 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 1516 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 1517 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1518 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 1519 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 1520 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 1521 1522 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 1523 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 1524 1525 /* BME1000 PHY Specific Control Register */ 1526 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 1527 1528 /* 1529 * Bits... 1530 * 15-5: page 1531 * 4-0: register offset 1532 */ 1533 #define GG82563_PAGE_SHIFT 5 1534 #define GG82563_REG(page, reg) \ 1535 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1536 #define GG82563_MIN_ALT_REG 30 1537 1538 /* GG82563 Specific Registers */ 1539 #define GG82563_PHY_SPEC_CTRL \ 1540 GG82563_REG(0, 16) /* PHY Specific Control */ 1541 #define GG82563_PHY_SPEC_STATUS \ 1542 GG82563_REG(0, 17) /* PHY Specific Status */ 1543 #define GG82563_PHY_INT_ENABLE \ 1544 GG82563_REG(0, 18) /* Interrupt Enable */ 1545 #define GG82563_PHY_SPEC_STATUS_2 \ 1546 GG82563_REG(0, 19) /* PHY Specific Status 2 */ 1547 #define GG82563_PHY_RX_ERR_CNTR \ 1548 GG82563_REG(0, 21) /* Receive Error Counter */ 1549 #define GG82563_PHY_PAGE_SELECT \ 1550 GG82563_REG(0, 22) /* Page Select */ 1551 #define GG82563_PHY_SPEC_CTRL_2 \ 1552 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 1553 #define GG82563_PHY_PAGE_SELECT_ALT \ 1554 GG82563_REG(0, 29) /* Alternate Page Select */ 1555 #define GG82563_PHY_TEST_CLK_CTRL \ 1556 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ 1557 1558 #define GG82563_PHY_MAC_SPEC_CTRL \ 1559 GG82563_REG(2, 21) /* MAC Specific Control Register */ 1560 #define GG82563_PHY_MAC_SPEC_CTRL_2 \ 1561 GG82563_REG(2, 26) /* MAC Specific Control 2 */ 1562 1563 #define GG82563_PHY_DSP_DISTANCE \ 1564 GG82563_REG(5, 26) /* DSP Distance */ 1565 1566 /* Page 193 - Port Control Registers */ 1567 #define GG82563_PHY_KMRN_MODE_CTRL \ 1568 GG82563_REG(193, 16) /* Kumeran Mode Control */ 1569 #define GG82563_PHY_PORT_RESET \ 1570 GG82563_REG(193, 17) /* Port Reset */ 1571 #define GG82563_PHY_REVISION_ID \ 1572 GG82563_REG(193, 18) /* Revision ID */ 1573 #define GG82563_PHY_DEVICE_ID \ 1574 GG82563_REG(193, 19) /* Device ID */ 1575 #define GG82563_PHY_PWR_MGMT_CTRL \ 1576 GG82563_REG(193, 20) /* Power Management Control */ 1577 #define GG82563_PHY_RATE_ADAPT_CTRL \ 1578 GG82563_REG(193, 25) /* Rate Adaptation Control */ 1579 1580 /* Page 194 - KMRN Registers */ 1581 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ 1582 GG82563_REG(194, 16) /* FIFO's Control/Status */ 1583 #define GG82563_PHY_KMRN_CTRL \ 1584 GG82563_REG(194, 17) /* Control */ 1585 #define GG82563_PHY_INBAND_CTRL \ 1586 GG82563_REG(194, 18) /* Inband Control */ 1587 #define GG82563_PHY_KMRN_DIAGNOSTIC \ 1588 GG82563_REG(194, 19) /* Diagnostic */ 1589 #define GG82563_PHY_ACK_TIMEOUTS \ 1590 GG82563_REG(194, 20) /* Acknowledge Timeouts */ 1591 #define GG82563_PHY_ADV_ABILITY \ 1592 GG82563_REG(194, 21) /* Advertised Ability */ 1593 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ 1594 GG82563_REG(194, 23) /* Link Partner Advertised Ability */ 1595 #define GG82563_PHY_ADV_NEXT_PAGE \ 1596 GG82563_REG(194, 24) /* Advertised Next Page */ 1597 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ 1598 GG82563_REG(194, 25) /* Link Partner Advertised Next page */ 1599 #define GG82563_PHY_KMRN_MISC \ 1600 GG82563_REG(194, 26) /* Misc. */ 1601 1602 /* MDI Control */ 1603 #define E1000_MDIC_DATA_MASK 0x0000FFFF 1604 #define E1000_MDIC_REG_MASK 0x001F0000 1605 #define E1000_MDIC_REG_SHIFT 16 1606 #define E1000_MDIC_PHY_MASK 0x03E00000 1607 #define E1000_MDIC_PHY_SHIFT 21 1608 #define E1000_MDIC_OP_WRITE 0x04000000 1609 #define E1000_MDIC_OP_READ 0x08000000 1610 #define E1000_MDIC_READY 0x10000000 1611 #define E1000_MDIC_INT_EN 0x20000000 1612 #define E1000_MDIC_ERROR 0x40000000 1613 1614 /* SerDes Control */ 1615 #define E1000_GEN_CTL_READY 0x80000000 1616 #define E1000_GEN_CTL_ADDRESS_SHIFT 8 1617 #define E1000_GEN_POLL_TIMEOUT 640 1618 1619 /* LinkSec register fields */ 1620 #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000 1621 #define E1000_LSECTXCAP_SUM_SHIFT 16 1622 #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000 1623 #define E1000_LSECRXCAP_SUM_SHIFT 16 1624 1625 #define E1000_LSECTXCTRL_EN_MASK 0x00000003 1626 #define E1000_LSECTXCTRL_DISABLE 0x0 1627 #define E1000_LSECTXCTRL_AUTH 0x1 1628 #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 1629 #define E1000_LSECTXCTRL_AISCI 0x00000020 1630 #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 1631 #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8 1632 1633 #define E1000_LSECRXCTRL_EN_MASK 0x0000000C 1634 #define E1000_LSECRXCTRL_EN_SHIFT 2 1635 #define E1000_LSECRXCTRL_DISABLE 0x0 1636 #define E1000_LSECRXCTRL_CHECK 0x1 1637 #define E1000_LSECRXCTRL_STRICT 0x2 1638 #define E1000_LSECRXCTRL_DROP 0x3 1639 #define E1000_LSECRXCTRL_PLSH 0x00000040 1640 #define E1000_LSECRXCTRL_RP 0x00000080 1641 #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 1642 1643 1644 /* DMA Coalescing register fields */ 1645 #define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing 1646 * Watchdog Timer */ 1647 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Receive 1648 * Threshold */ 1649 #define E1000_DMACR_DMACTHR_SHIFT 16 1650 #define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe 1651 * transactions */ 1652 #define E1000_DMACR_DMAC_LX_SHIFT 28 1653 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 1654 1655 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit 1656 * Threshold */ 1657 1658 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1659 1660 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Receive Traffic Rate 1661 * Threshold */ 1662 #define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rcv packet rate in 1663 * current window */ 1664 1665 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rcv Traffic 1666 * Current Cnt */ 1667 1668 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rcv Threshold 1669 * High val */ 1670 #define E1000_FCRTC_RTH_COAL_SHIFT 4 1671 #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based 1672 on DMA coal */ 1673 1674 #endif /* _E1000_DEFINES_H_ */ 1675