1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #ifndef _E1000_BASE_H_ 36 #define _E1000_BASE_H_ 37 38 /* forward declaration */ 39 s32 e1000_init_hw_base(struct e1000_hw *hw); 40 void e1000_power_down_phy_copper_base(struct e1000_hw *hw); 41 extern void e1000_rx_fifo_flush_base(struct e1000_hw *hw); 42 s32 e1000_acquire_phy_base(struct e1000_hw *hw); 43 void e1000_release_phy_base(struct e1000_hw *hw); 44 45 /* Transmit Descriptor - Advanced */ 46 union e1000_adv_tx_desc { 47 struct { 48 __le64 buffer_addr; /* Address of descriptor's data buf */ 49 __le32 cmd_type_len; 50 __le32 olinfo_status; 51 } read; 52 struct { 53 __le64 rsvd; /* Reserved */ 54 __le32 nxtseq_seed; 55 __le32 status; 56 } wb; 57 }; 58 59 /* Context descriptors */ 60 struct e1000_adv_tx_context_desc { 61 __le32 vlan_macip_lens; 62 union { 63 __le32 launch_time; 64 __le32 seqnum_seed; 65 } u; 66 __le32 type_tucmd_mlhl; 67 __le32 mss_l4len_idx; 68 }; 69 70 /* Adv Transmit Descriptor Config Masks */ 71 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 72 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 73 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 74 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 75 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 76 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 77 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 78 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 79 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 80 #define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ 81 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ 82 #define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ 83 #define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 84 #define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 85 #define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 86 #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 87 /* 1st & Last TSO-full iSCSI PDU*/ 88 #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 89 #define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 90 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 91 92 /* Advanced Transmit Context Descriptor Config */ 93 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 94 #define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 95 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 96 #define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 97 #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 98 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 99 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 100 #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 101 /* IPSec Encrypt Enable for ESP */ 102 #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 103 /* Req requires Markers and CRC */ 104 #define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 105 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 106 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 107 /* Adv ctxt IPSec SA IDX mask */ 108 #define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF 109 /* Adv ctxt IPSec ESP len mask */ 110 #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF 111 112 #define E1000_RAR_ENTRIES_BASE 16 113 114 /* Receive Descriptor - Advanced */ 115 union e1000_adv_rx_desc { 116 struct { 117 __le64 pkt_addr; /* Packet buffer address */ 118 __le64 hdr_addr; /* Header buffer address */ 119 } read; 120 struct { 121 struct { 122 union { 123 __le32 data; 124 struct { 125 __le16 pkt_info; /*RSS type, Pkt type*/ 126 /* Split Header, header buffer len */ 127 __le16 hdr_info; 128 } hs_rss; 129 } lo_dword; 130 union { 131 __le32 rss; /* RSS Hash */ 132 struct { 133 __le16 ip_id; /* IP id */ 134 __le16 csum; /* Packet Checksum */ 135 } csum_ip; 136 } hi_dword; 137 } lower; 138 struct { 139 __le32 status_error; /* ext status/error */ 140 __le16 length; /* Packet length */ 141 __le16 vlan; /* VLAN tag */ 142 } upper; 143 } wb; /* writeback */ 144 }; 145 146 /* Additional Transmit Descriptor Control definitions */ 147 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ 148 149 /* Additional Receive Descriptor Control definitions */ 150 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ 151 152 /* SRRCTL bit definitions */ 153 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 154 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 155 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 156 157 #endif /* _E1000_BASE_H_ */ 158