1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #ifndef _E1000_82575_H_ 36 #define _E1000_82575_H_ 37 38 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ 39 (ID_LED_DEF1_DEF2 << 8) | \ 40 (ID_LED_DEF1_DEF2 << 4) | \ 41 (ID_LED_OFF1_ON2)) 42 /* 43 * Receive Address Register Count 44 * Number of high/low register pairs in the RAR. The RAR (Receive Address 45 * Registers) holds the directed and multicast addresses that we monitor. 46 * These entries are also used for MAC-based filtering. 47 */ 48 /* 49 * For 82576, there are an additional set of RARs that begin at an offset 50 * separate from the first set of RARs. 51 */ 52 #define E1000_RAR_ENTRIES_82575 16 53 #define E1000_RAR_ENTRIES_82576 24 54 #define E1000_RAR_ENTRIES_82580 24 55 #define E1000_RAR_ENTRIES_I350 32 56 #define E1000_SW_SYNCH_MB 0x00000100 57 #define E1000_STAT_DEV_RST_SET 0x00100000 58 59 struct e1000_adv_data_desc { 60 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 61 union { 62 u32 data; 63 struct { 64 u32 datalen:16; /* Data buffer length */ 65 u32 rsvd:4; 66 u32 dtyp:4; /* Descriptor type */ 67 u32 dcmd:8; /* Descriptor command */ 68 } config; 69 } lower; 70 union { 71 u32 data; 72 struct { 73 u32 status:4; /* Descriptor status */ 74 u32 idx:4; 75 u32 popts:6; /* Packet Options */ 76 u32 paylen:18; /* Payload length */ 77 } options; 78 } upper; 79 }; 80 81 #define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */ 82 #define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */ 83 #define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */ 84 #define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */ 85 #define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */ 86 #define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */ 87 #define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */ 88 #define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */ 89 #define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */ 90 #define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */ 91 #define E1000_ADV_DCMD_RS 0x8 /* Report Status */ 92 #define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */ 93 #define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */ 94 /* Extended Device Control */ 95 #define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */ 96 97 struct e1000_adv_context_desc { 98 union { 99 u32 ip_config; 100 struct { 101 u32 iplen:9; 102 u32 maclen:7; 103 u32 vlan_tag:16; 104 } fields; 105 } ip_setup; 106 u32 seq_num; 107 union { 108 u64 l4_config; 109 struct { 110 u32 mkrloc:9; 111 u32 tucmd:11; 112 u32 dtyp:4; 113 u32 adv:8; 114 u32 rsvd:4; 115 u32 idx:4; 116 u32 l4len:8; 117 u32 mss:16; 118 } fields; 119 } l4_setup; 120 }; 121 122 /* SRRCTL bit definitions */ 123 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 124 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 125 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 126 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 127 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 128 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 129 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 130 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 131 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 132 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 133 #define E1000_SRRCTL_TIMESTAMP 0x40000000 134 #define E1000_SRRCTL_DROP_EN 0x80000000 135 136 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 137 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 138 139 #define E1000_TX_HEAD_WB_ENABLE 0x1 140 #define E1000_TX_SEQNUM_WB_ENABLE 0x2 141 142 #define E1000_MRQC_ENABLE_RSS_MQ 0x00000002 143 #define E1000_MRQC_ENABLE_VMDQ 0x00000003 144 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 145 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 146 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 147 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 148 149 #define E1000_VMRCTL_MIRROR_PORT_SHIFT 8 150 #define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << \ 151 E1000_VMRCTL_MIRROR_PORT_SHIFT) 152 #define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) 153 #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1) 154 #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2) 155 156 #define E1000_EICR_TX_QUEUE ( \ 157 E1000_EICR_TX_QUEUE0 | \ 158 E1000_EICR_TX_QUEUE1 | \ 159 E1000_EICR_TX_QUEUE2 | \ 160 E1000_EICR_TX_QUEUE3) 161 162 #define E1000_EICR_RX_QUEUE ( \ 163 E1000_EICR_RX_QUEUE0 | \ 164 E1000_EICR_RX_QUEUE1 | \ 165 E1000_EICR_RX_QUEUE2 | \ 166 E1000_EICR_RX_QUEUE3) 167 168 #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE 169 #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE 170 171 #define EIMS_ENABLE_MASK ( \ 172 E1000_EIMS_RX_QUEUE | \ 173 E1000_EIMS_TX_QUEUE | \ 174 E1000_EIMS_TCP_TIMER | \ 175 E1000_EIMS_OTHER) 176 177 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 178 #define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 179 #define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 180 #define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 181 #define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 182 #define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 183 #define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 184 #define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 185 #define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 186 187 #define E1000_RXDADV_RSSTYPE_MASK 0x0000000F 188 #define E1000_RXDADV_RSSTYPE_SHIFT 12 189 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 190 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 191 #define E1000_RXDADV_SPLITHEADER_EN 0x00001000 192 #define E1000_RXDADV_SPH 0x8000 193 #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 194 #define E1000_RXDADV_ERR_HBO 0x00800000 195 196 /* RSS Hash results */ 197 #define E1000_RXDADV_RSSTYPE_NONE 0x00000000 198 #define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 199 #define E1000_RXDADV_RSSTYPE_IPV4 0x00000002 200 #define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 201 #define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004 202 #define E1000_RXDADV_RSSTYPE_IPV6 0x00000005 203 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 204 #define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 205 #define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 206 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 207 208 /* RSS Packet Types as indicated in the receive descriptor */ 209 #define E1000_RXDADV_PKTTYPE_ILMASK 0x000000F0 210 #define E1000_RXDADV_PKTTYPE_TLMASK 0x00000F00 211 #define E1000_RXDADV_PKTTYPE_NONE 0x00000000 212 #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 213 #define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ 214 #define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ 215 #define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ 216 #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 217 #define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 218 #define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 219 #define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 220 221 #define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 222 #define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 223 #define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 224 #define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 225 #define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 226 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 227 228 /* LinkSec results */ 229 /* Security Processing bit Indication */ 230 #define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000 231 #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 232 #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 233 #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 234 #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 235 236 #define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000 237 #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 238 #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 239 #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 240 #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000 241 242 /* Adv Transmit Descriptor Config Masks */ 243 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 244 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 245 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 246 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 247 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 248 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 249 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 250 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 251 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 252 #define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ 253 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ 254 #define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ 255 #define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 256 #define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 257 #define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 258 #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 259 /* 1st & Last TSO-full iSCSI PDU*/ 260 #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 261 #define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 262 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 263 264 /* Additional Transmit Descriptor Control definitions */ 265 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ 266 #define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */ 267 /* Tx Queue Arbitration Priority 0=low, 1=high */ 268 #define E1000_TXDCTL_PRIORITY 0x08000000 269 270 /* Additional Receive Descriptor Control definitions */ 271 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ 272 #define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */ 273 274 /* Direct Cache Access (DCA) definitions */ 275 #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 276 #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 277 278 #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 279 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 280 281 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 282 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 283 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */ 284 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */ 285 #define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */ 286 287 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 288 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 289 #define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 290 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 291 #define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 292 293 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 294 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ 295 #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */ 296 #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */ 297 298 /* Additional interrupt register bit definitions */ 299 #define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */ 300 #define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 301 #define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 302 303 /* 304 * ETQF filter list: one static filter per filter consumer. This is 305 * to avoid filter collisions later. Add new filters 306 * here!! 307 * 308 * Current filters: 309 * EAPOL 802.1x (0x888e): Filter 0 310 */ 311 #define E1000_ETQF_FILTER_EAPOL 0 312 313 #define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 314 #define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000 315 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 316 317 #define E1000_NVM_APME_82575 0x0400 318 #define MAX_NUM_VFS 7 319 320 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof cntrl */ 321 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof cntrl */ 322 #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ 323 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 324 #define E1000_DTXSWC_LLE_SHIFT 16 325 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1U << 31) /* global VF LB enable */ 326 327 /* Easy defines for setting default pool, would normally be left a zero */ 328 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 329 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) 330 331 /* Other useful VMD_CTL register defines */ 332 #define E1000_VT_CTL_IGNORE_MAC (1 << 28) 333 #define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) 334 #define E1000_VT_CTL_VM_REPL_EN (1 << 30) 335 336 /* Per VM Offload register setup */ 337 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 338 #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ 339 #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ 340 #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ 341 #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ 342 #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ 343 #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ 344 #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ 345 #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 346 #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 347 348 #define E1000_VMOLR_VPE 0x00800000 /* VLAN promiscuous enable */ 349 #define E1000_VMOLR_UPE 0x20000000 /* Unicast promisuous enable */ 350 #define E1000_DVMOLR_HIDVLAN 0x20000000 /* Vlan hiding enable */ 351 #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 352 #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 353 354 #define E1000_PBRWAC_WALPB 0x00000007 /* Wrap around event on LAN Rx PB */ 355 #define E1000_PBRWAC_PBE 0x00000008 /* Rx packet buffer empty */ 356 357 #define E1000_VLVF_ARRAY_SIZE 32 358 #define E1000_VLVF_VLANID_MASK 0x00000FFF 359 #define E1000_VLVF_POOLSEL_SHIFT 12 360 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) 361 #define E1000_VLVF_LVLAN 0x00100000 362 #define E1000_VLVF_VLANID_ENABLE 0x80000000 363 364 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 365 #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 366 367 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 368 369 #define E1000_IOVCTL 0x05BBC 370 #define E1000_IOVCTL_REUSE_VFQ 0x00000001 371 372 #define E1000_RPLOLR_STRVLAN 0x40000000 373 #define E1000_RPLOLR_STRCRC 0x80000000 374 375 #define E1000_TCTL_EXT_COLD 0x000FFC00 376 #define E1000_TCTL_EXT_COLD_SHIFT 10 377 378 #define E1000_DTXCTL_8023LL 0x0004 379 #define E1000_DTXCTL_VLAN_ADDED 0x0008 380 #define E1000_DTXCTL_OOS_ENABLE 0x0010 381 #define E1000_DTXCTL_MDP_EN 0x0020 382 #define E1000_DTXCTL_SPOOF_INT 0x0040 383 384 #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14) 385 386 #define ALL_QUEUES 0xFFFF 387 388 s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 389 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 390 391 /* Rx packet buffer size defines */ 392 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F 393 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable); 394 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf); 395 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable); 396 397 enum e1000_promisc_type { 398 e1000_promisc_disabled = 0, /* all promisc modes disabled */ 399 e1000_promisc_unicast = 1, /* unicast promiscuous enabled */ 400 e1000_promisc_multicast = 2, /* multicast promiscuous enabled */ 401 e1000_promisc_enabled = 3, /* both uni and multicast promisc */ 402 e1000_num_promisc_types 403 }; 404 405 void e1000_vfta_set_vf(struct e1000_hw *, u16, bool); 406 void e1000_rlpml_set_vf(struct e1000_hw *, u16); 407 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type); 408 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value); 409 u16 e1000_rxpbs_adjust_82580(u32 data); 410 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data); 411 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M); 412 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M); 413 s32 e1000_get_eee_status_i354(struct e1000_hw *, bool *); 414 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw); 415 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw); 416 417 /* I2C SDA and SCL timing parameters for standard mode */ 418 #define E1000_I2C_T_HD_STA 4 419 #define E1000_I2C_T_LOW 5 420 #define E1000_I2C_T_HIGH 4 421 #define E1000_I2C_T_SU_STA 5 422 #define E1000_I2C_T_HD_DATA 5 423 #define E1000_I2C_T_SU_DATA 1 424 #define E1000_I2C_T_RISE 1 425 #define E1000_I2C_T_FALL 1 426 #define E1000_I2C_T_SU_STO 4 427 #define E1000_I2C_T_BUF 5 428 429 s32 e1000_set_i2c_bb(struct e1000_hw *hw); 430 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 431 u8 dev_addr, u8 *data); 432 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 433 u8 dev_addr, u8 data); 434 void e1000_i2c_bus_clear(struct e1000_hw *hw); 435 #endif /* _E1000_82575_H_ */ 436