1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* e1000_82575 36 * e1000_82576 37 */ 38 39 #include "e1000_api.h" 40 41 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 42 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 43 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 44 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 45 static void e1000_release_phy_82575(struct e1000_hw *hw); 46 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 47 static void e1000_release_nvm_82575(struct e1000_hw *hw); 48 static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 49 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 50 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 51 u16 *duplex); 52 static s32 e1000_init_hw_82575(struct e1000_hw *hw); 53 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 54 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 55 u16 *data); 56 static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 57 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 58 bool active); 59 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 60 static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw); 61 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 62 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 63 u32 offset, u16 data); 64 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 65 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 66 static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw); 67 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 68 u16 *speed, u16 *duplex); 69 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 70 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 71 static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 72 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 73 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 74 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 75 76 static void e1000_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count); 77 static void e1000_update_mc_addr_list_82575(struct e1000_hw *hw, 78 u8 *mc_addr_list, u32 mc_addr_count, 79 u32 rar_used_count, u32 rar_count); 80 void e1000_remove_device_82575(struct e1000_hw *hw); 81 void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); 82 83 struct e1000_dev_spec_82575 { 84 bool sgmii_active; 85 }; 86 87 /** 88 * e1000_init_phy_params_82575 - Init PHY func ptrs. 89 * @hw: pointer to the HW structure 90 * 91 * This is a function pointer entry point called by the api module. 92 **/ 93 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 94 { 95 struct e1000_phy_info *phy = &hw->phy; 96 s32 ret_val = E1000_SUCCESS; 97 98 DEBUGFUNC("e1000_init_phy_params_82575"); 99 100 if (hw->phy.media_type != e1000_media_type_copper) { 101 phy->type = e1000_phy_none; 102 goto out; 103 } else { 104 phy->ops.power_up = e1000_power_up_phy_copper; 105 phy->ops.power_down = e1000_power_down_phy_copper_82575; 106 } 107 108 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 109 phy->reset_delay_us = 100; 110 111 phy->ops.acquire = e1000_acquire_phy_82575; 112 phy->ops.check_reset_block = e1000_check_reset_block_generic; 113 phy->ops.commit = e1000_phy_sw_reset_generic; 114 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 115 phy->ops.release = e1000_release_phy_82575; 116 117 if (e1000_sgmii_active_82575(hw)) { 118 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 119 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 120 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 121 } else { 122 phy->ops.reset = e1000_phy_hw_reset_generic; 123 phy->ops.read_reg = e1000_read_phy_reg_igp; 124 phy->ops.write_reg = e1000_write_phy_reg_igp; 125 } 126 127 /* Set phy->phy_addr and phy->id. */ 128 ret_val = e1000_get_phy_id_82575(hw); 129 130 /* Verify phy id and set remaining function pointers */ 131 switch (phy->id) { 132 case M88E1111_I_PHY_ID: 133 phy->type = e1000_phy_m88; 134 phy->ops.check_polarity = e1000_check_polarity_m88; 135 phy->ops.get_info = e1000_get_phy_info_m88; 136 phy->ops.get_cable_length = e1000_get_cable_length_m88; 137 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 138 break; 139 case IGP03E1000_E_PHY_ID: 140 case IGP04E1000_E_PHY_ID: 141 phy->type = e1000_phy_igp_3; 142 phy->ops.check_polarity = e1000_check_polarity_igp; 143 phy->ops.get_info = e1000_get_phy_info_igp; 144 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 145 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 146 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 147 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 148 break; 149 default: 150 ret_val = -E1000_ERR_PHY; 151 goto out; 152 } 153 154 out: 155 return ret_val; 156 } 157 158 /** 159 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 160 * @hw: pointer to the HW structure 161 * 162 * This is a function pointer entry point called by the api module. 163 **/ 164 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 165 { 166 struct e1000_nvm_info *nvm = &hw->nvm; 167 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 168 u16 size; 169 170 DEBUGFUNC("e1000_init_nvm_params_82575"); 171 172 nvm->opcode_bits = 8; 173 nvm->delay_usec = 1; 174 switch (nvm->override) { 175 case e1000_nvm_override_spi_large: 176 nvm->page_size = 32; 177 nvm->address_bits = 16; 178 break; 179 case e1000_nvm_override_spi_small: 180 nvm->page_size = 8; 181 nvm->address_bits = 8; 182 break; 183 default: 184 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 185 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 186 break; 187 } 188 189 nvm->type = e1000_nvm_eeprom_spi; 190 191 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 192 E1000_EECD_SIZE_EX_SHIFT); 193 194 /* 195 * Added to a constant, "size" becomes the left-shift value 196 * for setting word_size. 197 */ 198 size += NVM_WORD_SIZE_BASE_SHIFT; 199 200 /* EEPROM access above 16k is unsupported */ 201 if (size > 14) 202 size = 14; 203 nvm->word_size = 1 << size; 204 205 /* Function Pointers */ 206 nvm->ops.acquire = e1000_acquire_nvm_82575; 207 nvm->ops.read = e1000_read_nvm_eerd; 208 nvm->ops.release = e1000_release_nvm_82575; 209 nvm->ops.update = e1000_update_nvm_checksum_generic; 210 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 211 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 212 nvm->ops.write = e1000_write_nvm_spi; 213 214 return E1000_SUCCESS; 215 } 216 217 /** 218 * e1000_init_mac_params_82575 - Init MAC func ptrs. 219 * @hw: pointer to the HW structure 220 * 221 * This is a function pointer entry point called by the api module. 222 **/ 223 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 224 { 225 struct e1000_mac_info *mac = &hw->mac; 226 struct e1000_dev_spec_82575 *dev_spec; 227 u32 ctrl_ext = 0; 228 s32 ret_val = E1000_SUCCESS; 229 230 DEBUGFUNC("e1000_init_mac_params_82575"); 231 232 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82575); 233 234 /* Device-specific structure allocation */ 235 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 236 if (ret_val) 237 goto out; 238 239 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec; 240 241 /* Set media type */ 242 /* 243 * The 82575 uses bits 22:23 for link mode. The mode can be changed 244 * based on the EEPROM. We cannot rely upon device ID. There 245 * is no distinguishable difference between fiber and internal 246 * SerDes mode on the 82575. There can be an external PHY attached 247 * on the SGMII interface. For this, we'll set sgmii_active to TRUE. 248 */ 249 hw->phy.media_type = e1000_media_type_copper; 250 dev_spec->sgmii_active = FALSE; 251 252 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 253 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == 254 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { 255 hw->phy.media_type = e1000_media_type_internal_serdes; 256 ctrl_ext |= E1000_CTRL_I2C_ENA; 257 } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { 258 dev_spec->sgmii_active = TRUE; 259 ctrl_ext |= E1000_CTRL_I2C_ENA; 260 } else { 261 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 262 } 263 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 264 265 /* Set mta register count */ 266 mac->mta_reg_count = 128; 267 /* Set rar entry count */ 268 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 269 if (mac->type == e1000_82576) 270 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 271 /* Set if part includes ASF firmware */ 272 mac->asf_firmware_present = TRUE; 273 /* Set if manageability features are enabled. */ 274 mac->arc_subsystem_valid = 275 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 276 ? TRUE : FALSE; 277 278 /* Function pointers */ 279 280 /* bus type/speed/width */ 281 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 282 /* reset */ 283 mac->ops.reset_hw = e1000_reset_hw_82575; 284 /* hw initialization */ 285 mac->ops.init_hw = e1000_init_hw_82575; 286 /* link setup */ 287 mac->ops.setup_link = e1000_setup_link_generic; 288 /* physical interface link setup */ 289 mac->ops.setup_physical_interface = 290 (hw->phy.media_type == e1000_media_type_copper) 291 ? e1000_setup_copper_link_82575 292 : e1000_setup_fiber_serdes_link_82575; 293 /* physical interface shutdown */ 294 mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575; 295 /* check for link */ 296 mac->ops.check_for_link = e1000_check_for_link_82575; 297 /* receive address register setting */ 298 mac->ops.rar_set = e1000_rar_set_generic; 299 /* read mac address */ 300 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 301 /* multicast address update */ 302 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_82575; 303 /* writing VFTA */ 304 mac->ops.write_vfta = e1000_write_vfta_generic; 305 /* clearing VFTA */ 306 mac->ops.clear_vfta = e1000_clear_vfta_generic; 307 /* setting MTA */ 308 mac->ops.mta_set = e1000_mta_set_generic; 309 /* blink LED */ 310 mac->ops.blink_led = e1000_blink_led_generic; 311 /* setup LED */ 312 mac->ops.setup_led = e1000_setup_led_generic; 313 /* cleanup LED */ 314 mac->ops.cleanup_led = e1000_cleanup_led_generic; 315 /* turn on/off LED */ 316 mac->ops.led_on = e1000_led_on_generic; 317 mac->ops.led_off = e1000_led_off_generic; 318 /* remove device */ 319 mac->ops.remove_device = e1000_remove_device_82575; 320 /* clear hardware counters */ 321 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 322 /* link info */ 323 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 324 325 out: 326 return ret_val; 327 } 328 329 /** 330 * e1000_init_function_pointers_82575 - Init func ptrs. 331 * @hw: pointer to the HW structure 332 * 333 * The only function explicitly called by the api module to initialize 334 * all function pointers and parameters. 335 **/ 336 void e1000_init_function_pointers_82575(struct e1000_hw *hw) 337 { 338 DEBUGFUNC("e1000_init_function_pointers_82575"); 339 340 hw->mac.ops.init_params = e1000_init_mac_params_82575; 341 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 342 hw->phy.ops.init_params = e1000_init_phy_params_82575; 343 } 344 345 /** 346 * e1000_acquire_phy_82575 - Acquire rights to access PHY 347 * @hw: pointer to the HW structure 348 * 349 * Acquire access rights to the correct PHY. This is a 350 * function pointer entry point called by the api module. 351 **/ 352 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 353 { 354 u16 mask; 355 356 DEBUGFUNC("e1000_acquire_phy_82575"); 357 358 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 359 360 return e1000_acquire_swfw_sync_82575(hw, mask); 361 } 362 363 /** 364 * e1000_release_phy_82575 - Release rights to access PHY 365 * @hw: pointer to the HW structure 366 * 367 * A wrapper to release access rights to the correct PHY. This is a 368 * function pointer entry point called by the api module. 369 **/ 370 static void e1000_release_phy_82575(struct e1000_hw *hw) 371 { 372 u16 mask; 373 374 DEBUGFUNC("e1000_release_phy_82575"); 375 376 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 377 e1000_release_swfw_sync_82575(hw, mask); 378 } 379 380 /** 381 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 382 * @hw: pointer to the HW structure 383 * @offset: register offset to be read 384 * @data: pointer to the read data 385 * 386 * Reads the PHY register at offset using the serial gigabit media independent 387 * interface and stores the retrieved information in data. 388 **/ 389 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 390 u16 *data) 391 { 392 struct e1000_phy_info *phy = &hw->phy; 393 u32 i, i2ccmd = 0; 394 395 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 396 397 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 398 DEBUGOUT1("PHY Address %u is out of range\n", offset); 399 return -E1000_ERR_PARAM; 400 } 401 402 /* 403 * Set up Op-code, Phy Address, and register address in the I2CCMD 404 * register. The MAC will take care of interfacing with the 405 * PHY to retrieve the desired data. 406 */ 407 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 408 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 409 (E1000_I2CCMD_OPCODE_READ)); 410 411 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 412 413 /* Poll the ready bit to see if the I2C read completed */ 414 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 415 usec_delay(50); 416 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 417 if (i2ccmd & E1000_I2CCMD_READY) 418 break; 419 } 420 if (!(i2ccmd & E1000_I2CCMD_READY)) { 421 DEBUGOUT("I2CCMD Read did not complete\n"); 422 return -E1000_ERR_PHY; 423 } 424 if (i2ccmd & E1000_I2CCMD_ERROR) { 425 DEBUGOUT("I2CCMD Error bit set\n"); 426 return -E1000_ERR_PHY; 427 } 428 429 /* Need to byte-swap the 16-bit value. */ 430 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 431 432 return E1000_SUCCESS; 433 } 434 435 /** 436 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 437 * @hw: pointer to the HW structure 438 * @offset: register offset to write to 439 * @data: data to write at register offset 440 * 441 * Writes the data to PHY register at the offset using the serial gigabit 442 * media independent interface. 443 **/ 444 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 445 u16 data) 446 { 447 struct e1000_phy_info *phy = &hw->phy; 448 u32 i, i2ccmd = 0; 449 u16 phy_data_swapped; 450 451 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 452 453 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 454 DEBUGOUT1("PHY Address %d is out of range\n", offset); 455 return -E1000_ERR_PARAM; 456 } 457 458 /* Swap the data bytes for the I2C interface */ 459 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 460 461 /* 462 * Set up Op-code, Phy Address, and register address in the I2CCMD 463 * register. The MAC will take care of interfacing with the 464 * PHY to retrieve the desired data. 465 */ 466 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 467 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 468 E1000_I2CCMD_OPCODE_WRITE | 469 phy_data_swapped); 470 471 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 472 473 /* Poll the ready bit to see if the I2C read completed */ 474 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 475 usec_delay(50); 476 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 477 if (i2ccmd & E1000_I2CCMD_READY) 478 break; 479 } 480 if (!(i2ccmd & E1000_I2CCMD_READY)) { 481 DEBUGOUT("I2CCMD Write did not complete\n"); 482 return -E1000_ERR_PHY; 483 } 484 if (i2ccmd & E1000_I2CCMD_ERROR) { 485 DEBUGOUT("I2CCMD Error bit set\n"); 486 return -E1000_ERR_PHY; 487 } 488 489 return E1000_SUCCESS; 490 } 491 492 /** 493 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 494 * @hw: pointer to the HW structure 495 * 496 * Retrieves the PHY address and ID for both PHY's which do and do not use 497 * sgmi interface. 498 **/ 499 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 500 { 501 struct e1000_phy_info *phy = &hw->phy; 502 s32 ret_val = E1000_SUCCESS; 503 u16 phy_id; 504 505 DEBUGFUNC("e1000_get_phy_id_82575"); 506 507 /* 508 * For SGMII PHYs, we try the list of possible addresses until 509 * we find one that works. For non-SGMII PHYs 510 * (e.g. integrated copper PHYs), an address of 1 should 511 * work. The result of this function should mean phy->phy_addr 512 * and phy->id are set correctly. 513 */ 514 if (!(e1000_sgmii_active_82575(hw))) { 515 phy->addr = 1; 516 ret_val = e1000_get_phy_id(hw); 517 goto out; 518 } 519 520 /* 521 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 522 * Therefore, we need to test 1-7 523 */ 524 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 525 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 526 if (ret_val == E1000_SUCCESS) { 527 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 528 phy_id, 529 phy->addr); 530 /* 531 * At the time of this writing, The M88 part is 532 * the only supported SGMII PHY product. 533 */ 534 if (phy_id == M88_VENDOR) 535 break; 536 } else { 537 DEBUGOUT1("PHY address %u was unreadable\n", 538 phy->addr); 539 } 540 } 541 542 /* A valid PHY type couldn't be found. */ 543 if (phy->addr == 8) { 544 phy->addr = 0; 545 ret_val = -E1000_ERR_PHY; 546 goto out; 547 } 548 549 ret_val = e1000_get_phy_id(hw); 550 551 out: 552 return ret_val; 553 } 554 555 /** 556 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 557 * @hw: pointer to the HW structure 558 * 559 * Resets the PHY using the serial gigabit media independent interface. 560 **/ 561 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 562 { 563 s32 ret_val = E1000_SUCCESS; 564 565 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 566 567 /* 568 * This isn't a TRUE "hard" reset, but is the only reset 569 * available to us at this time. 570 */ 571 572 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 573 574 if (!(hw->phy.ops.write_reg)) 575 goto out; 576 577 /* 578 * SFP documentation requires the following to configure the SPF module 579 * to work on SGMII. No further documentation is given. 580 */ 581 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 582 if (ret_val) 583 goto out; 584 585 ret_val = hw->phy.ops.commit(hw); 586 587 out: 588 return ret_val; 589 } 590 591 /** 592 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 593 * @hw: pointer to the HW structure 594 * @active: TRUE to enable LPLU, FALSE to disable 595 * 596 * Sets the LPLU D0 state according to the active flag. When 597 * activating LPLU this function also disables smart speed 598 * and vice versa. LPLU will not be activated unless the 599 * device autonegotiation advertisement meets standards of 600 * either 10 or 10/100 or 10/100/1000 at all duplexes. 601 * This is a function pointer entry point only called by 602 * PHY setup routines. 603 **/ 604 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 605 { 606 struct e1000_phy_info *phy = &hw->phy; 607 s32 ret_val = E1000_SUCCESS; 608 u16 data; 609 610 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 611 612 if (!(hw->phy.ops.read_reg)) 613 goto out; 614 615 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 616 if (ret_val) 617 goto out; 618 619 if (active) { 620 data |= IGP02E1000_PM_D0_LPLU; 621 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 622 data); 623 if (ret_val) 624 goto out; 625 626 /* When LPLU is enabled, we should disable SmartSpeed */ 627 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 628 &data); 629 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 630 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 631 data); 632 if (ret_val) 633 goto out; 634 } else { 635 data &= ~IGP02E1000_PM_D0_LPLU; 636 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 637 data); 638 /* 639 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 640 * during Dx states where the power conservation is most 641 * important. During driver activity we should enable 642 * SmartSpeed, so performance is maintained. 643 */ 644 if (phy->smart_speed == e1000_smart_speed_on) { 645 ret_val = phy->ops.read_reg(hw, 646 IGP01E1000_PHY_PORT_CONFIG, 647 &data); 648 if (ret_val) 649 goto out; 650 651 data |= IGP01E1000_PSCFR_SMART_SPEED; 652 ret_val = phy->ops.write_reg(hw, 653 IGP01E1000_PHY_PORT_CONFIG, 654 data); 655 if (ret_val) 656 goto out; 657 } else if (phy->smart_speed == e1000_smart_speed_off) { 658 ret_val = phy->ops.read_reg(hw, 659 IGP01E1000_PHY_PORT_CONFIG, 660 &data); 661 if (ret_val) 662 goto out; 663 664 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 665 ret_val = phy->ops.write_reg(hw, 666 IGP01E1000_PHY_PORT_CONFIG, 667 data); 668 if (ret_val) 669 goto out; 670 } 671 } 672 673 out: 674 return ret_val; 675 } 676 677 /** 678 * e1000_acquire_nvm_82575 - Request for access to EEPROM 679 * @hw: pointer to the HW structure 680 * 681 * Acquire the necessary semaphores for exclusive access to the EEPROM. 682 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 683 * Return successful if access grant bit set, else clear the request for 684 * EEPROM access and return -E1000_ERR_NVM (-1). 685 **/ 686 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 687 { 688 s32 ret_val; 689 690 DEBUGFUNC("e1000_acquire_nvm_82575"); 691 692 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 693 if (ret_val) 694 goto out; 695 696 ret_val = e1000_acquire_nvm_generic(hw); 697 698 if (ret_val) 699 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 700 701 out: 702 return ret_val; 703 } 704 705 /** 706 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 707 * @hw: pointer to the HW structure 708 * 709 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 710 * then release the semaphores acquired. 711 **/ 712 static void e1000_release_nvm_82575(struct e1000_hw *hw) 713 { 714 DEBUGFUNC("e1000_release_nvm_82575"); 715 716 e1000_release_nvm_generic(hw); 717 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 718 } 719 720 /** 721 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 722 * @hw: pointer to the HW structure 723 * @mask: specifies which semaphore to acquire 724 * 725 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 726 * will also specify which port we're acquiring the lock for. 727 **/ 728 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 729 { 730 u32 swfw_sync; 731 u32 swmask = mask; 732 u32 fwmask = mask << 16; 733 s32 ret_val = E1000_SUCCESS; 734 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 735 736 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 737 738 while (i < timeout) { 739 if (e1000_get_hw_semaphore_generic(hw)) { 740 ret_val = -E1000_ERR_SWFW_SYNC; 741 goto out; 742 } 743 744 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 745 if (!(swfw_sync & (fwmask | swmask))) 746 break; 747 748 /* 749 * Firmware currently using resource (fwmask) 750 * or other software thread using resource (swmask) 751 */ 752 e1000_put_hw_semaphore_generic(hw); 753 msec_delay_irq(5); 754 i++; 755 } 756 757 if (i == timeout) { 758 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 759 ret_val = -E1000_ERR_SWFW_SYNC; 760 goto out; 761 } 762 763 swfw_sync |= swmask; 764 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 765 766 e1000_put_hw_semaphore_generic(hw); 767 768 out: 769 return ret_val; 770 } 771 772 /** 773 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 774 * @hw: pointer to the HW structure 775 * @mask: specifies which semaphore to acquire 776 * 777 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 778 * will also specify which port we're releasing the lock for. 779 **/ 780 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 781 { 782 u32 swfw_sync; 783 784 DEBUGFUNC("e1000_release_swfw_sync_82575"); 785 786 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 787 /* Empty */ 788 789 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 790 swfw_sync &= ~mask; 791 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 792 793 e1000_put_hw_semaphore_generic(hw); 794 } 795 796 /** 797 * e1000_get_cfg_done_82575 - Read config done bit 798 * @hw: pointer to the HW structure 799 * 800 * Read the management control register for the config done bit for 801 * completion status. NOTE: silicon which is EEPROM-less will fail trying 802 * to read the config done bit, so an error is *ONLY* logged and returns 803 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 804 * would not be able to be reset or change link. 805 **/ 806 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 807 { 808 s32 timeout = PHY_CFG_TIMEOUT; 809 s32 ret_val = E1000_SUCCESS; 810 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 811 812 DEBUGFUNC("e1000_get_cfg_done_82575"); 813 814 if (hw->bus.func == 1) 815 mask = E1000_NVM_CFG_DONE_PORT_1; 816 817 while (timeout) { 818 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 819 break; 820 msec_delay(1); 821 timeout--; 822 } 823 if (!timeout) { 824 DEBUGOUT("MNG configuration cycle has not completed.\n"); 825 } 826 827 /* If EEPROM is not marked present, init the PHY manually */ 828 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 829 (hw->phy.type == e1000_phy_igp_3)) { 830 e1000_phy_init_script_igp3(hw); 831 } 832 833 return ret_val; 834 } 835 836 /** 837 * e1000_get_link_up_info_82575 - Get link speed/duplex info 838 * @hw: pointer to the HW structure 839 * @speed: stores the current speed 840 * @duplex: stores the current duplex 841 * 842 * This is a wrapper function, if using the serial gigabit media independent 843 * interface, use PCS to retrieve the link speed and duplex information. 844 * Otherwise, use the generic function to get the link speed and duplex info. 845 **/ 846 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 847 u16 *duplex) 848 { 849 s32 ret_val; 850 851 DEBUGFUNC("e1000_get_link_up_info_82575"); 852 853 if (hw->phy.media_type != e1000_media_type_copper || 854 e1000_sgmii_active_82575(hw)) { 855 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 856 duplex); 857 } else { 858 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 859 duplex); 860 } 861 862 return ret_val; 863 } 864 865 /** 866 * e1000_check_for_link_82575 - Check for link 867 * @hw: pointer to the HW structure 868 * 869 * If sgmii is enabled, then use the pcs register to determine link, otherwise 870 * use the generic interface for determining link. 871 **/ 872 static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 873 { 874 s32 ret_val; 875 u16 speed, duplex; 876 877 DEBUGFUNC("e1000_check_for_link_82575"); 878 879 /* SGMII link check is done through the PCS register. */ 880 if ((hw->phy.media_type != e1000_media_type_copper) || 881 (e1000_sgmii_active_82575(hw))) 882 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 883 &duplex); 884 else 885 ret_val = e1000_check_for_copper_link_generic(hw); 886 887 return ret_val; 888 } 889 890 /** 891 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 892 * @hw: pointer to the HW structure 893 * @speed: stores the current speed 894 * @duplex: stores the current duplex 895 * 896 * Using the physical coding sub-layer (PCS), retrieve the current speed and 897 * duplex, then store the values in the pointers provided. 898 **/ 899 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 900 u16 *speed, u16 *duplex) 901 { 902 struct e1000_mac_info *mac = &hw->mac; 903 u32 pcs; 904 905 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 906 907 /* Set up defaults for the return values of this function */ 908 mac->serdes_has_link = FALSE; 909 *speed = 0; 910 *duplex = 0; 911 912 /* 913 * Read the PCS Status register for link state. For non-copper mode, 914 * the status register is not accurate. The PCS status register is 915 * used instead. 916 */ 917 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 918 919 /* 920 * The link up bit determines when link is up on autoneg. The sync ok 921 * gets set once both sides sync up and agree upon link. Stable link 922 * can be determined by checking for both link up and link sync ok 923 */ 924 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 925 mac->serdes_has_link = TRUE; 926 927 /* Detect and store PCS speed */ 928 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 929 *speed = SPEED_1000; 930 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 931 *speed = SPEED_100; 932 } else { 933 *speed = SPEED_10; 934 } 935 936 /* Detect and store PCS duplex */ 937 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 938 *duplex = FULL_DUPLEX; 939 } else { 940 *duplex = HALF_DUPLEX; 941 } 942 } 943 944 return E1000_SUCCESS; 945 } 946 947 /** 948 * e1000_init_rx_addrs_82575 - Initialize receive address's 949 * @hw: pointer to the HW structure 950 * @rar_count: receive address registers 951 * 952 * Setups the receive address registers by setting the base receive address 953 * register to the devices MAC address and clearing all the other receive 954 * address registers to 0. 955 **/ 956 static void e1000_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count) 957 { 958 u32 i; 959 u8 addr[6] = {0,0,0,0,0,0}; 960 /* 961 * This function is essentially the same as that of 962 * e1000_init_rx_addrs_generic. However it also takes care 963 * of the special case where the register offset of the 964 * second set of RARs begins elsewhere. This is implicitly taken care by 965 * function e1000_rar_set_generic. 966 */ 967 968 DEBUGFUNC("e1000_init_rx_addrs_82575"); 969 970 /* Setup the receive address */ 971 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 972 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 973 974 /* Zero out the other (rar_entry_count - 1) receive addresses */ 975 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 976 for (i = 1; i < rar_count; i++) { 977 hw->mac.ops.rar_set(hw, addr, i); 978 } 979 } 980 981 /** 982 * e1000_update_mc_addr_list_82575 - Update Multicast addresses 983 * @hw: pointer to the HW structure 984 * @mc_addr_list: array of multicast addresses to program 985 * @mc_addr_count: number of multicast addresses to program 986 * @rar_used_count: the first RAR register free to program 987 * @rar_count: total number of supported Receive Address Registers 988 * 989 * Updates the Receive Address Registers and Multicast Table Array. 990 * The caller must have a packed mc_addr_list of multicast addresses. 991 * The parameter rar_count will usually be hw->mac.rar_entry_count 992 * unless there are workarounds that change this. 993 **/ 994 static void e1000_update_mc_addr_list_82575(struct e1000_hw *hw, 995 u8 *mc_addr_list, u32 mc_addr_count, 996 u32 rar_used_count, u32 rar_count) 997 { 998 u32 hash_value; 999 u32 i; 1000 u8 addr[6] = {0,0,0,0,0,0}; 1001 /* 1002 * This function is essentially the same as that of 1003 * e1000_update_mc_addr_list_generic. However it also takes care 1004 * of the special case where the register offset of the 1005 * second set of RARs begins elsewhere. This is implicitly taken care by 1006 * function e1000_rar_set_generic. 1007 */ 1008 1009 DEBUGFUNC("e1000_update_mc_addr_list_82575"); 1010 1011 /* 1012 * Load the first set of multicast addresses into the exact 1013 * filters (RAR). If there are not enough to fill the RAR 1014 * array, clear the filters. 1015 */ 1016 for (i = rar_used_count; i < rar_count; i++) { 1017 if (mc_addr_count) { 1018 e1000_rar_set_generic(hw, mc_addr_list, i); 1019 mc_addr_count--; 1020 mc_addr_list += ETH_ADDR_LEN; 1021 } else { 1022 e1000_rar_set_generic(hw, addr, i); 1023 } 1024 } 1025 1026 /* Clear the old settings from the MTA */ 1027 DEBUGOUT("Clearing MTA\n"); 1028 for (i = 0; i < hw->mac.mta_reg_count; i++) { 1029 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1030 E1000_WRITE_FLUSH(hw); 1031 } 1032 1033 /* Load any remaining multicast addresses into the hash table. */ 1034 for (; mc_addr_count > 0; mc_addr_count--) { 1035 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 1036 DEBUGOUT1("Hash value = 0x%03X\n", hash_value); 1037 hw->mac.ops.mta_set(hw, hash_value); 1038 mc_addr_list += ETH_ADDR_LEN; 1039 } 1040 } 1041 1042 /** 1043 * e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down 1044 * @hw: pointer to the HW structure 1045 * 1046 * In the case of fiber serdes shut down optics and PCS on driver unload 1047 * when management pass thru is not enabled. 1048 **/ 1049 void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) 1050 { 1051 u32 reg; 1052 1053 if (hw->mac.type != e1000_82576 || 1054 (hw->phy.media_type != e1000_media_type_fiber && 1055 hw->phy.media_type != e1000_media_type_internal_serdes)) 1056 return; 1057 1058 /* if the management interface is not enabled, then power down */ 1059 if (!e1000_enable_mng_pass_thru(hw)) { 1060 /* Disable PCS to turn off link */ 1061 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1062 reg &= ~E1000_PCS_CFG_PCS_EN; 1063 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1064 1065 /* shutdown the laser */ 1066 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1067 reg |= E1000_CTRL_EXT_SDP7_DATA; 1068 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1069 1070 /* flush the write to verfiy completion */ 1071 E1000_WRITE_FLUSH(hw); 1072 msec_delay(1); 1073 } 1074 1075 return; 1076 } 1077 1078 /** 1079 * e1000_reset_hw_82575 - Reset hardware 1080 * @hw: pointer to the HW structure 1081 * 1082 * This resets the hardware into a known state. This is a 1083 * function pointer entry point called by the api module. 1084 **/ 1085 static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1086 { 1087 u32 ctrl, icr; 1088 s32 ret_val; 1089 1090 DEBUGFUNC("e1000_reset_hw_82575"); 1091 1092 /* 1093 * Prevent the PCI-E bus from sticking if there is no TLP connection 1094 * on the last TLP read/write transaction when MAC is reset. 1095 */ 1096 ret_val = e1000_disable_pcie_master_generic(hw); 1097 if (ret_val) { 1098 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1099 } 1100 1101 DEBUGOUT("Masking off all interrupts\n"); 1102 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1103 1104 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1105 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1106 E1000_WRITE_FLUSH(hw); 1107 1108 msec_delay(10); 1109 1110 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1111 1112 DEBUGOUT("Issuing a global reset to MAC\n"); 1113 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1114 1115 ret_val = e1000_get_auto_rd_done_generic(hw); 1116 if (ret_val) { 1117 /* 1118 * When auto config read does not complete, do not 1119 * return with an error. This can happen in situations 1120 * where there is no eeprom and prevents getting link. 1121 */ 1122 DEBUGOUT("Auto Read Done did not complete\n"); 1123 } 1124 1125 /* If EEPROM is not present, run manual init scripts */ 1126 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1127 e1000_reset_init_script_82575(hw); 1128 1129 /* Clear any pending interrupt events. */ 1130 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1131 icr = E1000_READ_REG(hw, E1000_ICR); 1132 1133 e1000_check_alt_mac_addr_generic(hw); 1134 1135 return ret_val; 1136 } 1137 1138 /** 1139 * e1000_init_hw_82575 - Initialize hardware 1140 * @hw: pointer to the HW structure 1141 * 1142 * This inits the hardware readying it for operation. 1143 **/ 1144 static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1145 { 1146 struct e1000_mac_info *mac = &hw->mac; 1147 s32 ret_val; 1148 u16 i, rar_count = mac->rar_entry_count; 1149 1150 DEBUGFUNC("e1000_init_hw_82575"); 1151 1152 /* Initialize identification LED */ 1153 ret_val = e1000_id_led_init_generic(hw); 1154 if (ret_val) { 1155 DEBUGOUT("Error initializing identification LED\n"); 1156 /* This is not fatal and we should not stop init due to this */ 1157 } 1158 1159 /* Disabling VLAN filtering */ 1160 DEBUGOUT("Initializing the IEEE VLAN\n"); 1161 mac->ops.clear_vfta(hw); 1162 1163 /* Setup the receive address */ 1164 e1000_init_rx_addrs_82575(hw, rar_count); 1165 /* Zero out the Multicast HASH table */ 1166 DEBUGOUT("Zeroing the MTA\n"); 1167 for (i = 0; i < mac->mta_reg_count; i++) 1168 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1169 1170 /* Setup link and flow control */ 1171 ret_val = mac->ops.setup_link(hw); 1172 1173 /* 1174 * Clear all of the statistics registers (clear on read). It is 1175 * important that we do this after we have tried to establish link 1176 * because the symbol error count will increment wildly if there 1177 * is no link. 1178 */ 1179 e1000_clear_hw_cntrs_82575(hw); 1180 1181 return ret_val; 1182 } 1183 1184 /** 1185 * e1000_setup_copper_link_82575 - Configure copper link settings 1186 * @hw: pointer to the HW structure 1187 * 1188 * Configures the link for auto-neg or forced speed and duplex. Then we check 1189 * for link, once link is established calls to configure collision distance 1190 * and flow control are called. 1191 **/ 1192 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1193 { 1194 u32 ctrl, led_ctrl; 1195 s32 ret_val; 1196 bool link; 1197 1198 DEBUGFUNC("e1000_setup_copper_link_82575"); 1199 1200 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1201 ctrl |= E1000_CTRL_SLU; 1202 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1203 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1204 1205 switch (hw->phy.type) { 1206 case e1000_phy_m88: 1207 ret_val = e1000_copper_link_setup_m88(hw); 1208 break; 1209 case e1000_phy_igp_3: 1210 ret_val = e1000_copper_link_setup_igp(hw); 1211 /* Setup activity LED */ 1212 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1213 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1214 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1215 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1216 break; 1217 default: 1218 ret_val = -E1000_ERR_PHY; 1219 break; 1220 } 1221 1222 if (ret_val) 1223 goto out; 1224 1225 if (hw->mac.autoneg) { 1226 /* 1227 * Setup autoneg and flow control advertisement 1228 * and perform autonegotiation. 1229 */ 1230 ret_val = e1000_copper_link_autoneg(hw); 1231 if (ret_val) 1232 goto out; 1233 } else { 1234 /* 1235 * PHY will be set to 10H, 10F, 100H or 100F 1236 * depending on user settings. 1237 */ 1238 DEBUGOUT("Forcing Speed and Duplex\n"); 1239 ret_val = hw->phy.ops.force_speed_duplex(hw); 1240 if (ret_val) { 1241 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1242 goto out; 1243 } 1244 } 1245 1246 ret_val = e1000_configure_pcs_link_82575(hw); 1247 if (ret_val) 1248 goto out; 1249 1250 /* 1251 * Check link status. Wait up to 100 microseconds for link to become 1252 * valid. 1253 */ 1254 ret_val = e1000_phy_has_link_generic(hw, 1255 COPPER_LINK_UP_LIMIT, 1256 10, 1257 &link); 1258 if (ret_val) 1259 goto out; 1260 1261 if (link) { 1262 DEBUGOUT("Valid link established!!!\n"); 1263 /* Config the MAC and PHY after link is up */ 1264 e1000_config_collision_dist_generic(hw); 1265 ret_val = e1000_config_fc_after_link_up_generic(hw); 1266 } else { 1267 DEBUGOUT("Unable to establish link!!!\n"); 1268 } 1269 1270 out: 1271 return ret_val; 1272 } 1273 1274 /** 1275 * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes 1276 * @hw: pointer to the HW structure 1277 * 1278 * Configures speed and duplex for fiber and serdes links. 1279 **/ 1280 static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw) 1281 { 1282 u32 reg; 1283 1284 DEBUGFUNC("e1000_setup_fiber_serdes_link_82575"); 1285 1286 /* 1287 * On the 82575, SerDes loopback mode persists until it is 1288 * explicitly turned off or a power cycle is performed. A read to 1289 * the register does not indicate its status. Therefore, we ensure 1290 * loopback mode is disabled during initialization. 1291 */ 1292 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1293 1294 /* Force link up, set 1gb, set both sw defined pins */ 1295 reg = E1000_READ_REG(hw, E1000_CTRL); 1296 reg |= E1000_CTRL_SLU | 1297 E1000_CTRL_SPD_1000 | 1298 E1000_CTRL_FRCSPD | 1299 E1000_CTRL_SWDPIN0 | 1300 E1000_CTRL_SWDPIN1; 1301 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1302 1303 /* Power on phy for 82576 fiber adapters */ 1304 if (hw->mac.type == e1000_82576) { 1305 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1306 reg &= ~E1000_CTRL_EXT_SDP7_DATA; 1307 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1308 } 1309 1310 /* Set switch control to serdes energy detect */ 1311 reg = E1000_READ_REG(hw, E1000_CONNSW); 1312 reg |= E1000_CONNSW_ENRGSRC; 1313 E1000_WRITE_REG(hw, E1000_CONNSW, reg); 1314 1315 /* 1316 * New SerDes mode allows for forcing speed or autonegotiating speed 1317 * at 1gb. Autoneg should be default set by most drivers. This is the 1318 * mode that will be compatible with older link partners and switches. 1319 * However, both are supported by the hardware and some drivers/tools. 1320 */ 1321 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1322 1323 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1324 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1325 1326 if (hw->mac.autoneg) { 1327 /* Set PCS register for autoneg */ 1328 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1329 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1330 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1331 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1332 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 1333 } else { 1334 /* Set PCS register for forced speed */ 1335 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1336 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1337 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1338 E1000_PCS_LCTL_FSD | /* Force Speed */ 1339 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1340 DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); 1341 } 1342 1343 if (hw->mac.type == e1000_82576) { 1344 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1345 e1000_force_mac_fc_generic(hw); 1346 } 1347 1348 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1349 1350 return E1000_SUCCESS; 1351 } 1352 1353 /** 1354 * e1000_valid_led_default_82575 - Verify a valid default LED config 1355 * @hw: pointer to the HW structure 1356 * @data: pointer to the NVM (EEPROM) 1357 * 1358 * Read the EEPROM for the current default LED configuration. If the 1359 * LED configuration is not valid, set to a valid LED configuration. 1360 **/ 1361 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1362 { 1363 s32 ret_val; 1364 1365 DEBUGFUNC("e1000_valid_led_default_82575"); 1366 1367 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1368 if (ret_val) { 1369 DEBUGOUT("NVM Read Error\n"); 1370 goto out; 1371 } 1372 1373 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1374 switch(hw->phy.media_type) { 1375 case e1000_media_type_fiber: 1376 case e1000_media_type_internal_serdes: 1377 *data = ID_LED_DEFAULT_82575_SERDES; 1378 break; 1379 case e1000_media_type_copper: 1380 default: 1381 *data = ID_LED_DEFAULT; 1382 break; 1383 } 1384 } 1385 out: 1386 return ret_val; 1387 } 1388 1389 /** 1390 * e1000_configure_pcs_link_82575 - Configure PCS link 1391 * @hw: pointer to the HW structure 1392 * 1393 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1394 * only used on copper connections where the serialized gigabit media 1395 * independent interface (sgmii) is being used. Configures the link 1396 * for auto-negotiation or forces speed/duplex. 1397 **/ 1398 static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw) 1399 { 1400 struct e1000_mac_info *mac = &hw->mac; 1401 u32 reg = 0; 1402 1403 DEBUGFUNC("e1000_configure_pcs_link_82575"); 1404 1405 if (hw->phy.media_type != e1000_media_type_copper || 1406 !(e1000_sgmii_active_82575(hw))) 1407 goto out; 1408 1409 /* For SGMII, we need to issue a PCS autoneg restart */ 1410 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1411 1412 /* AN time out should be disabled for SGMII mode */ 1413 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1414 1415 if (mac->autoneg) { 1416 /* Make sure forced speed and force link are not set */ 1417 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1418 1419 /* 1420 * The PHY should be setup prior to calling this function. 1421 * All we need to do is restart autoneg and enable autoneg. 1422 */ 1423 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; 1424 } else { 1425 /* Set PCS register for forced speed */ 1426 1427 /* Turn off bits for full duplex, speed, and autoneg */ 1428 reg &= ~(E1000_PCS_LCTL_FSV_1000 | 1429 E1000_PCS_LCTL_FSV_100 | 1430 E1000_PCS_LCTL_FDV_FULL | 1431 E1000_PCS_LCTL_AN_ENABLE); 1432 1433 /* Check for duplex first */ 1434 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX) 1435 reg |= E1000_PCS_LCTL_FDV_FULL; 1436 1437 /* Now set speed */ 1438 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) 1439 reg |= E1000_PCS_LCTL_FSV_100; 1440 1441 /* Force speed and force link */ 1442 reg |= E1000_PCS_LCTL_FSD | 1443 E1000_PCS_LCTL_FORCE_LINK | 1444 E1000_PCS_LCTL_FLV_LINK_UP; 1445 1446 DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n", 1447 reg); 1448 } 1449 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1450 1451 out: 1452 return E1000_SUCCESS; 1453 } 1454 1455 /** 1456 * e1000_sgmii_active_82575 - Return sgmii state 1457 * @hw: pointer to the HW structure 1458 * 1459 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1460 * which can be enabled for use in the embedded applications. Simply 1461 * return the current state of the sgmii interface. 1462 **/ 1463 static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1464 { 1465 struct e1000_dev_spec_82575 *dev_spec; 1466 bool ret_val; 1467 1468 DEBUGFUNC("e1000_sgmii_active_82575"); 1469 1470 if (hw->mac.type != e1000_82575 && hw->mac.type != e1000_82576) { 1471 ret_val = FALSE; 1472 goto out; 1473 } 1474 1475 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec; 1476 1477 ret_val = dev_spec->sgmii_active; 1478 1479 out: 1480 return ret_val; 1481 } 1482 1483 /** 1484 * e1000_translate_register_82576 - Translate the proper register offset 1485 * @reg: e1000 register to be read 1486 * 1487 * Registers in 82576 are located in different offsets than other adapters 1488 * even though they function in the same manner. This function takes in 1489 * the name of the register to read and returns the correct offset for 1490 * 82576 silicon. 1491 **/ 1492 u32 e1000_translate_register_82576(u32 reg) 1493 { 1494 /* 1495 * Some of the 82576 registers are located at different 1496 * offsets than they are in older adapters. 1497 * Despite the difference in location, the registers 1498 * function in the same manner. 1499 */ 1500 switch (reg) { 1501 case E1000_TDBAL(0): 1502 reg = 0x0E000; 1503 break; 1504 case E1000_TDBAH(0): 1505 reg = 0x0E004; 1506 break; 1507 case E1000_TDLEN(0): 1508 reg = 0x0E008; 1509 break; 1510 case E1000_TDH(0): 1511 reg = 0x0E010; 1512 break; 1513 case E1000_TDT(0): 1514 reg = 0x0E018; 1515 break; 1516 case E1000_TXDCTL(0): 1517 reg = 0x0E028; 1518 break; 1519 case E1000_RDBAL(0): 1520 reg = 0x0C000; 1521 break; 1522 case E1000_RDBAH(0): 1523 reg = 0x0C004; 1524 break; 1525 case E1000_RDLEN(0): 1526 reg = 0x0C008; 1527 break; 1528 case E1000_RDH(0): 1529 reg = 0x0C010; 1530 break; 1531 case E1000_RDT(0): 1532 reg = 0x0C018; 1533 break; 1534 case E1000_RXDCTL(0): 1535 reg = 0x0C028; 1536 break; 1537 case E1000_SRRCTL(0): 1538 reg = 0x0C00C; 1539 break; 1540 default: 1541 break; 1542 } 1543 1544 return reg; 1545 } 1546 1547 /** 1548 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1549 * @hw: pointer to the HW structure 1550 * 1551 * Inits recommended HW defaults after a reset when there is no EEPROM 1552 * detected. This is only for the 82575. 1553 **/ 1554 static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) 1555 { 1556 DEBUGFUNC("e1000_reset_init_script_82575"); 1557 1558 if (hw->mac.type == e1000_82575) { 1559 DEBUGOUT("Running reset init script for 82575\n"); 1560 /* SerDes configuration via SERDESCTRL */ 1561 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1562 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1563 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1564 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1565 1566 /* CCM configuration via CCMCTL register */ 1567 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1568 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1569 1570 /* PCIe lanes configuration */ 1571 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1572 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1573 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1574 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1575 1576 /* PCIe PLL Configuration */ 1577 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1578 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1579 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1580 } 1581 1582 return E1000_SUCCESS; 1583 } 1584 1585 /** 1586 * e1000_read_mac_addr_82575 - Read device MAC address 1587 * @hw: pointer to the HW structure 1588 **/ 1589 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1590 { 1591 s32 ret_val = E1000_SUCCESS; 1592 1593 DEBUGFUNC("e1000_read_mac_addr_82575"); 1594 if (e1000_check_alt_mac_addr_generic(hw)) 1595 ret_val = e1000_read_mac_addr_generic(hw); 1596 1597 return ret_val; 1598 } 1599 1600 /** 1601 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1602 * @hw: pointer to the HW structure 1603 * 1604 * In the case of a PHY power down to save power, or to turn off link during a 1605 * driver unload, or wake on lan is not enabled, remove the link. 1606 **/ 1607 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1608 { 1609 struct e1000_phy_info *phy = &hw->phy; 1610 struct e1000_mac_info *mac = &hw->mac; 1611 1612 if (!(phy->ops.check_reset_block)) 1613 return; 1614 1615 /* If the management interface is not enabled, then power down */ 1616 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1617 e1000_power_down_phy_copper(hw); 1618 1619 return; 1620 } 1621 1622 /** 1623 * e1000_remove_device_82575 - Free device specific structure 1624 * @hw: pointer to the HW structure 1625 * 1626 * If a device specific structure was allocated, this function will 1627 * free it after shutting down the serdes interface if available. 1628 **/ 1629 void e1000_remove_device_82575(struct e1000_hw *hw) 1630 { 1631 u16 eeprom_data = 0; 1632 1633 /* 1634 * If APM is enabled in the EEPROM then leave the port on for fiber 1635 * serdes adapters. 1636 */ 1637 if (hw->bus.func == 0) 1638 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 1639 1640 if (!(eeprom_data & E1000_NVM_APME_82575)) 1641 e1000_shutdown_fiber_serdes_link_82575(hw); 1642 1643 e1000_remove_device_generic(hw); 1644 } 1645 1646 /** 1647 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1648 * @hw: pointer to the HW structure 1649 * 1650 * Clears the hardware counters by reading the counter registers. 1651 **/ 1652 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1653 { 1654 volatile u32 temp; 1655 1656 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1657 1658 e1000_clear_hw_cntrs_base_generic(hw); 1659 1660 temp = E1000_READ_REG(hw, E1000_PRC64); 1661 temp = E1000_READ_REG(hw, E1000_PRC127); 1662 temp = E1000_READ_REG(hw, E1000_PRC255); 1663 temp = E1000_READ_REG(hw, E1000_PRC511); 1664 temp = E1000_READ_REG(hw, E1000_PRC1023); 1665 temp = E1000_READ_REG(hw, E1000_PRC1522); 1666 temp = E1000_READ_REG(hw, E1000_PTC64); 1667 temp = E1000_READ_REG(hw, E1000_PTC127); 1668 temp = E1000_READ_REG(hw, E1000_PTC255); 1669 temp = E1000_READ_REG(hw, E1000_PTC511); 1670 temp = E1000_READ_REG(hw, E1000_PTC1023); 1671 temp = E1000_READ_REG(hw, E1000_PTC1522); 1672 1673 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1674 temp = E1000_READ_REG(hw, E1000_RXERRC); 1675 temp = E1000_READ_REG(hw, E1000_TNCRS); 1676 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1677 temp = E1000_READ_REG(hw, E1000_TSCTC); 1678 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1679 1680 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1681 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1682 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1683 1684 temp = E1000_READ_REG(hw, E1000_IAC); 1685 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1686 1687 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1688 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1689 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1690 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1691 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1692 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1693 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1694 1695 temp = E1000_READ_REG(hw, E1000_CBTMPC); 1696 temp = E1000_READ_REG(hw, E1000_HTDPMC); 1697 temp = E1000_READ_REG(hw, E1000_CBRMPC); 1698 temp = E1000_READ_REG(hw, E1000_RPTHC); 1699 temp = E1000_READ_REG(hw, E1000_HGPTC); 1700 temp = E1000_READ_REG(hw, E1000_HTCBDPC); 1701 temp = E1000_READ_REG(hw, E1000_HGORCL); 1702 temp = E1000_READ_REG(hw, E1000_HGORCH); 1703 temp = E1000_READ_REG(hw, E1000_HGOTCL); 1704 temp = E1000_READ_REG(hw, E1000_HGOTCH); 1705 temp = E1000_READ_REG(hw, E1000_LENERRS); 1706 1707 /* This register should not be read in copper configurations */ 1708 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1709 temp = E1000_READ_REG(hw, E1000_SCVPC); 1710 } 1711 /** 1712 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1713 * @hw: pointer to the HW structure 1714 * 1715 * After rx enable if managability is enabled then there is likely some 1716 * bad data at the start of the fifo and possibly in the DMA fifo. This 1717 * function clears the fifos and flushes any packets that came in as rx was 1718 * being enabled. 1719 **/ 1720 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 1721 { 1722 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1723 int i, ms_wait; 1724 1725 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 1726 if (hw->mac.type != e1000_82575 || 1727 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1728 return; 1729 1730 /* Disable all RX queues */ 1731 for (i = 0; i < 4; i++) { 1732 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 1733 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 1734 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1735 } 1736 /* Poll all queues to verify they have shut down */ 1737 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1738 msec_delay(1); 1739 rx_enabled = 0; 1740 for (i = 0; i < 4; i++) 1741 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 1742 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1743 break; 1744 } 1745 1746 if (ms_wait == 10) 1747 DEBUGOUT("Queue disable timed out after 10ms\n"); 1748 1749 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1750 * incoming packets are rejected. Set enable and wait 2ms so that 1751 * any packet that was coming in as RCTL.EN was set is flushed 1752 */ 1753 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 1754 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1755 1756 rlpml = E1000_READ_REG(hw, E1000_RLPML); 1757 E1000_WRITE_REG(hw, E1000_RLPML, 0); 1758 1759 rctl = E1000_READ_REG(hw, E1000_RCTL); 1760 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1761 temp_rctl |= E1000_RCTL_LPE; 1762 1763 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 1764 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1765 E1000_WRITE_FLUSH(hw); 1766 msec_delay(2); 1767 1768 /* Enable RX queues that were previously enabled and restore our 1769 * previous state 1770 */ 1771 for (i = 0; i < 4; i++) 1772 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 1773 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1774 E1000_WRITE_FLUSH(hw); 1775 1776 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 1777 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 1778 1779 /* Flush receive errors generated by workaround */ 1780 E1000_READ_REG(hw, E1000_ROC); 1781 E1000_READ_REG(hw, E1000_RNBC); 1782 E1000_READ_REG(hw, E1000_MPC); 1783 } 1784