1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 /* 36 * 82575EB Gigabit Network Connection 37 * 82575EB Gigabit Backplane Connection 38 * 82575GB Gigabit Network Connection 39 * 82576 Gigabit Network Connection 40 * 82576 Quad Port Gigabit Mezzanine Adapter 41 * 82580 Gigabit Network Connection 42 * I350 Gigabit Network Connection 43 */ 44 45 #include "e1000_api.h" 46 #include "e1000_i210.h" 47 48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 50 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 51 static void e1000_release_nvm_82575(struct e1000_hw *hw); 52 static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 53 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw); 54 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 55 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 56 u16 *duplex); 57 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 58 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 59 u16 *data); 60 static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 61 static s32 e1000_init_hw_82575(struct e1000_hw *hw); 62 static s32 e1000_reset_hw_82580(struct e1000_hw *hw); 63 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 64 u32 offset, u16 *data); 65 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 66 u32 offset, u16 data); 67 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, 68 bool active); 69 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, 70 bool active); 71 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 72 bool active); 73 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 74 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 75 static s32 e1000_get_media_type_82575(struct e1000_hw *hw); 76 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw); 77 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 78 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 79 u32 offset, u16 data); 80 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 81 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 82 u16 *speed, u16 *duplex); 83 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 84 static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 85 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 86 static void e1000_config_collision_dist_82575(struct e1000_hw *hw); 87 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 88 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 89 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 90 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 91 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); 92 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); 93 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, 94 u16 offset); 95 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 96 u16 offset); 97 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); 98 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); 99 static void e1000_clear_vfta_i350(struct e1000_hw *hw); 100 101 static void e1000_i2c_start(struct e1000_hw *hw); 102 static void e1000_i2c_stop(struct e1000_hw *hw); 103 static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data); 104 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data); 105 static s32 e1000_get_i2c_ack(struct e1000_hw *hw); 106 static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data); 107 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data); 108 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 109 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 110 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data); 111 static bool e1000_get_i2c_data(u32 *i2cctl); 112 113 static const u16 e1000_82580_rxpbs_table[] = { 114 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 115 #define E1000_82580_RXPBS_TABLE_SIZE \ 116 (sizeof(e1000_82580_rxpbs_table) / \ 117 sizeof(e1000_82580_rxpbs_table[0])) 118 119 120 /** 121 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 122 * @hw: pointer to the HW structure 123 * 124 * Called to determine if the I2C pins are being used for I2C or as an 125 * external MDIO interface since the two options are mutually exclusive. 126 **/ 127 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 128 { 129 u32 reg = 0; 130 bool ext_mdio = false; 131 132 DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 133 134 switch (hw->mac.type) { 135 case e1000_82575: 136 case e1000_82576: 137 reg = E1000_READ_REG(hw, E1000_MDIC); 138 ext_mdio = !!(reg & E1000_MDIC_DEST); 139 break; 140 case e1000_82580: 141 case e1000_i350: 142 case e1000_i354: 143 case e1000_i210: 144 case e1000_i211: 145 reg = E1000_READ_REG(hw, E1000_MDICNFG); 146 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 147 break; 148 default: 149 break; 150 } 151 return ext_mdio; 152 } 153 154 /** 155 * e1000_init_phy_params_82575 - Initialize PHY function ptrs 156 * @hw: pointer to the HW structure 157 **/ 158 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 159 { 160 struct e1000_phy_info *phy = &hw->phy; 161 s32 ret_val = E1000_SUCCESS; 162 u32 ctrl_ext; 163 164 DEBUGFUNC("e1000_init_phy_params_82575"); 165 166 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; 167 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; 168 169 if (hw->phy.media_type != e1000_media_type_copper) { 170 phy->type = e1000_phy_none; 171 goto out; 172 } 173 174 phy->ops.power_up = e1000_power_up_phy_copper; 175 phy->ops.power_down = e1000_power_down_phy_copper_base; 176 177 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 178 phy->reset_delay_us = 100; 179 180 phy->ops.acquire = e1000_acquire_phy_base; 181 phy->ops.check_reset_block = e1000_check_reset_block_generic; 182 phy->ops.commit = e1000_phy_sw_reset_generic; 183 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 184 phy->ops.release = e1000_release_phy_base; 185 186 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 187 188 if (e1000_sgmii_active_82575(hw)) { 189 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 190 ctrl_ext |= E1000_CTRL_I2C_ENA; 191 } else { 192 phy->ops.reset = e1000_phy_hw_reset_generic; 193 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 194 } 195 196 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 197 e1000_reset_mdicnfg_82580(hw); 198 199 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 200 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 201 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 202 } else { 203 switch (hw->mac.type) { 204 case e1000_82580: 205 case e1000_i350: 206 case e1000_i354: 207 phy->ops.read_reg = e1000_read_phy_reg_82580; 208 phy->ops.write_reg = e1000_write_phy_reg_82580; 209 break; 210 case e1000_i210: 211 case e1000_i211: 212 phy->ops.read_reg = e1000_read_phy_reg_gs40g; 213 phy->ops.write_reg = e1000_write_phy_reg_gs40g; 214 break; 215 default: 216 phy->ops.read_reg = e1000_read_phy_reg_igp; 217 phy->ops.write_reg = e1000_write_phy_reg_igp; 218 } 219 } 220 221 /* Set phy->phy_addr and phy->id. */ 222 ret_val = e1000_get_phy_id_82575(hw); 223 224 /* Verify phy id and set remaining function pointers */ 225 switch (phy->id) { 226 case M88E1543_E_PHY_ID: 227 case M88E1512_E_PHY_ID: 228 case I347AT4_E_PHY_ID: 229 case M88E1112_E_PHY_ID: 230 case M88E1340M_E_PHY_ID: 231 phy->type = e1000_phy_m88; 232 phy->ops.check_polarity = e1000_check_polarity_m88; 233 phy->ops.get_info = e1000_get_phy_info_m88; 234 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 235 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 236 break; 237 case M88E1111_I_PHY_ID: 238 phy->type = e1000_phy_m88; 239 phy->ops.check_polarity = e1000_check_polarity_m88; 240 phy->ops.get_info = e1000_get_phy_info_m88; 241 phy->ops.get_cable_length = e1000_get_cable_length_m88; 242 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 243 break; 244 case IGP03E1000_E_PHY_ID: 245 case IGP04E1000_E_PHY_ID: 246 phy->type = e1000_phy_igp_3; 247 phy->ops.check_polarity = e1000_check_polarity_igp; 248 phy->ops.get_info = e1000_get_phy_info_igp; 249 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 250 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 251 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 252 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 253 break; 254 case I82580_I_PHY_ID: 255 case I350_I_PHY_ID: 256 phy->type = e1000_phy_82580; 257 phy->ops.check_polarity = e1000_check_polarity_82577; 258 phy->ops.get_info = e1000_get_phy_info_82577; 259 phy->ops.get_cable_length = e1000_get_cable_length_82577; 260 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 261 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 262 phy->ops.force_speed_duplex = 263 e1000_phy_force_speed_duplex_82577; 264 break; 265 case I210_I_PHY_ID: 266 phy->type = e1000_phy_i210; 267 phy->ops.check_polarity = e1000_check_polarity_m88; 268 phy->ops.get_info = e1000_get_phy_info_m88; 269 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 270 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 271 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 272 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 273 break; 274 default: 275 ret_val = -E1000_ERR_PHY; 276 goto out; 277 } 278 279 /* Check if this PHY is configured for media swap. */ 280 switch (phy->id) { 281 case M88E1112_E_PHY_ID: 282 { 283 u16 data; 284 285 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2); 286 if (ret_val) 287 goto out; 288 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1, 289 &data); 290 if (ret_val) 291 goto out; 292 293 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 294 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 295 if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 296 data == E1000_M88E1112_AUTO_COPPER_BASEX) 297 hw->mac.ops.check_for_link = 298 e1000_check_for_link_media_swap; 299 break; 300 } 301 case M88E1512_E_PHY_ID: 302 { 303 ret_val = e1000_initialize_M88E1512_phy(hw); 304 break; 305 } 306 case M88E1543_E_PHY_ID: 307 { 308 ret_val = e1000_initialize_M88E1543_phy(hw); 309 break; 310 } 311 default: 312 goto out; 313 } 314 315 out: 316 return ret_val; 317 } 318 319 /** 320 * e1000_init_mac_params_82575 - Init MAC func ptrs. 321 * @hw: pointer to the HW structure 322 **/ 323 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 324 { 325 struct e1000_mac_info *mac = &hw->mac; 326 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 327 328 DEBUGFUNC("e1000_init_mac_params_82575"); 329 330 /* Initialize function pointer */ 331 e1000_init_mac_ops_generic(hw); 332 333 /* Derives media type */ 334 e1000_get_media_type_82575(hw); 335 /* Set MTA register count */ 336 mac->mta_reg_count = 128; 337 /* Set UTA register count */ 338 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 339 /* Set RAR entry count */ 340 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 341 if (mac->type == e1000_82576) 342 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 343 if (mac->type == e1000_82580) 344 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 345 if (mac->type == e1000_i350 || mac->type == e1000_i354) 346 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 347 348 /* Enable EEE default settings for EEE supported devices */ 349 if (mac->type >= e1000_i350) 350 dev_spec->eee_disable = false; 351 352 /* Allow a single clear of the SW semaphore on I210 and newer */ 353 if (mac->type >= e1000_i210) 354 dev_spec->clear_semaphore_once = true; 355 356 /* Set if part includes ASF firmware */ 357 mac->asf_firmware_present = true; 358 /* FWSM register */ 359 mac->has_fwsm = true; 360 /* ARC supported; valid only if manageability features are enabled. */ 361 mac->arc_subsystem_valid = 362 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK); 363 364 /* Function pointers */ 365 366 /* bus type/speed/width */ 367 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 368 /* reset */ 369 if (mac->type >= e1000_82580) 370 mac->ops.reset_hw = e1000_reset_hw_82580; 371 else 372 mac->ops.reset_hw = e1000_reset_hw_82575; 373 /* HW initialization */ 374 if ((mac->type == e1000_i210) || (mac->type == e1000_i211)) 375 mac->ops.init_hw = e1000_init_hw_i210; 376 else 377 mac->ops.init_hw = e1000_init_hw_82575; 378 /* link setup */ 379 mac->ops.setup_link = e1000_setup_link_generic; 380 /* physical interface link setup */ 381 mac->ops.setup_physical_interface = 382 (hw->phy.media_type == e1000_media_type_copper) 383 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575; 384 /* physical interface shutdown */ 385 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 386 /* physical interface power up */ 387 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 388 /* check for link */ 389 mac->ops.check_for_link = e1000_check_for_link_82575; 390 /* read mac address */ 391 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 392 /* configure collision distance */ 393 mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 394 /* multicast address update */ 395 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 396 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) { 397 /* writing VFTA */ 398 mac->ops.write_vfta = e1000_write_vfta_i350; 399 /* clearing VFTA */ 400 mac->ops.clear_vfta = e1000_clear_vfta_i350; 401 } else { 402 /* writing VFTA */ 403 mac->ops.write_vfta = e1000_write_vfta_generic; 404 /* clearing VFTA */ 405 mac->ops.clear_vfta = e1000_clear_vfta_generic; 406 } 407 if (hw->mac.type >= e1000_82580) 408 mac->ops.validate_mdi_setting = 409 e1000_validate_mdi_setting_crossover_generic; 410 /* ID LED init */ 411 mac->ops.id_led_init = e1000_id_led_init_generic; 412 /* blink LED */ 413 mac->ops.blink_led = e1000_blink_led_generic; 414 /* setup LED */ 415 mac->ops.setup_led = e1000_setup_led_generic; 416 /* cleanup LED */ 417 mac->ops.cleanup_led = e1000_cleanup_led_generic; 418 /* turn on/off LED */ 419 mac->ops.led_on = e1000_led_on_generic; 420 mac->ops.led_off = e1000_led_off_generic; 421 /* clear hardware counters */ 422 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 423 /* link info */ 424 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 425 /* acquire SW_FW sync */ 426 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync; 427 /* release SW_FW sync */ 428 mac->ops.release_swfw_sync = e1000_release_swfw_sync; 429 430 /* set lan id for port to determine which phy lock to use */ 431 hw->mac.ops.set_lan_id(hw); 432 433 return E1000_SUCCESS; 434 } 435 436 /** 437 * e1000_init_nvm_params_82575 - Initialize NVM function ptrs 438 * @hw: pointer to the HW structure 439 **/ 440 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 441 { 442 struct e1000_nvm_info *nvm = &hw->nvm; 443 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 444 u16 size; 445 446 DEBUGFUNC("e1000_init_nvm_params_82575"); 447 448 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 449 E1000_EECD_SIZE_EX_SHIFT); 450 /* Added to a constant, "size" becomes the left-shift value 451 * for setting word_size. 452 */ 453 size += NVM_WORD_SIZE_BASE_SHIFT; 454 455 /* Just in case size is out of range, cap it to the largest 456 * EEPROM size supported 457 */ 458 if (size > 15) 459 size = 15; 460 461 nvm->word_size = 1 << size; 462 if (hw->mac.type < e1000_i210) { 463 nvm->opcode_bits = 8; 464 nvm->delay_usec = 1; 465 466 switch (nvm->override) { 467 case e1000_nvm_override_spi_large: 468 nvm->page_size = 32; 469 nvm->address_bits = 16; 470 break; 471 case e1000_nvm_override_spi_small: 472 nvm->page_size = 8; 473 nvm->address_bits = 8; 474 break; 475 default: 476 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 477 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 478 16 : 8; 479 break; 480 } 481 if (nvm->word_size == (1 << 15)) 482 nvm->page_size = 128; 483 484 nvm->type = e1000_nvm_eeprom_spi; 485 } else { 486 nvm->type = e1000_nvm_flash_hw; 487 } 488 489 /* Function Pointers */ 490 nvm->ops.acquire = e1000_acquire_nvm_82575; 491 nvm->ops.release = e1000_release_nvm_82575; 492 if (nvm->word_size < (1 << 15)) 493 nvm->ops.read = e1000_read_nvm_eerd; 494 else 495 nvm->ops.read = e1000_read_nvm_spi; 496 497 nvm->ops.write = e1000_write_nvm_spi; 498 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 499 nvm->ops.update = e1000_update_nvm_checksum_generic; 500 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 501 502 /* override generic family function pointers for specific descendants */ 503 switch (hw->mac.type) { 504 case e1000_82580: 505 nvm->ops.validate = e1000_validate_nvm_checksum_82580; 506 nvm->ops.update = e1000_update_nvm_checksum_82580; 507 break; 508 case e1000_i350: 509 nvm->ops.validate = e1000_validate_nvm_checksum_i350; 510 nvm->ops.update = e1000_update_nvm_checksum_i350; 511 break; 512 default: 513 break; 514 } 515 516 return E1000_SUCCESS; 517 } 518 519 /** 520 * e1000_init_function_pointers_82575 - Init func ptrs. 521 * @hw: pointer to the HW structure 522 * 523 * Called to initialize all function pointers and parameters. 524 **/ 525 void e1000_init_function_pointers_82575(struct e1000_hw *hw) 526 { 527 DEBUGFUNC("e1000_init_function_pointers_82575"); 528 529 hw->mac.ops.init_params = e1000_init_mac_params_82575; 530 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 531 hw->phy.ops.init_params = e1000_init_phy_params_82575; 532 hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 533 } 534 535 /** 536 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 537 * @hw: pointer to the HW structure 538 * @offset: register offset to be read 539 * @data: pointer to the read data 540 * 541 * Reads the PHY register at offset using the serial gigabit media independent 542 * interface and stores the retrieved information in data. 543 **/ 544 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 545 u16 *data) 546 { 547 s32 ret_val = -E1000_ERR_PARAM; 548 549 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 550 551 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 552 DEBUGOUT1("PHY Address %u is out of range\n", offset); 553 goto out; 554 } 555 556 ret_val = hw->phy.ops.acquire(hw); 557 if (ret_val) 558 goto out; 559 560 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 561 562 hw->phy.ops.release(hw); 563 564 out: 565 return ret_val; 566 } 567 568 /** 569 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 570 * @hw: pointer to the HW structure 571 * @offset: register offset to write to 572 * @data: data to write at register offset 573 * 574 * Writes the data to PHY register at the offset using the serial gigabit 575 * media independent interface. 576 **/ 577 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 578 u16 data) 579 { 580 s32 ret_val = -E1000_ERR_PARAM; 581 582 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 583 584 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 585 DEBUGOUT1("PHY Address %d is out of range\n", offset); 586 goto out; 587 } 588 589 ret_val = hw->phy.ops.acquire(hw); 590 if (ret_val) 591 goto out; 592 593 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 594 595 hw->phy.ops.release(hw); 596 597 out: 598 return ret_val; 599 } 600 601 /** 602 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 603 * @hw: pointer to the HW structure 604 * 605 * Retrieves the PHY address and ID for both PHY's which do and do not use 606 * sgmi interface. 607 **/ 608 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 609 { 610 struct e1000_phy_info *phy = &hw->phy; 611 s32 ret_val = E1000_SUCCESS; 612 u16 phy_id; 613 u32 ctrl_ext; 614 u32 mdic; 615 616 DEBUGFUNC("e1000_get_phy_id_82575"); 617 618 /* some i354 devices need an extra read for phy id */ 619 if (hw->mac.type == e1000_i354) 620 e1000_get_phy_id(hw); 621 622 /* 623 * For SGMII PHYs, we try the list of possible addresses until 624 * we find one that works. For non-SGMII PHYs 625 * (e.g. integrated copper PHYs), an address of 1 should 626 * work. The result of this function should mean phy->phy_addr 627 * and phy->id are set correctly. 628 */ 629 if (!e1000_sgmii_active_82575(hw)) { 630 phy->addr = 1; 631 ret_val = e1000_get_phy_id(hw); 632 goto out; 633 } 634 635 if (e1000_sgmii_uses_mdio_82575(hw)) { 636 switch (hw->mac.type) { 637 case e1000_82575: 638 case e1000_82576: 639 mdic = E1000_READ_REG(hw, E1000_MDIC); 640 mdic &= E1000_MDIC_PHY_MASK; 641 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 642 break; 643 case e1000_82580: 644 case e1000_i350: 645 case e1000_i354: 646 case e1000_i210: 647 case e1000_i211: 648 mdic = E1000_READ_REG(hw, E1000_MDICNFG); 649 mdic &= E1000_MDICNFG_PHY_MASK; 650 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 651 break; 652 default: 653 ret_val = -E1000_ERR_PHY; 654 goto out; 655 break; 656 } 657 ret_val = e1000_get_phy_id(hw); 658 goto out; 659 } 660 661 /* Power on sgmii phy if it is disabled */ 662 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 663 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 664 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 665 E1000_WRITE_FLUSH(hw); 666 msec_delay(300); 667 668 /* 669 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 670 * Therefore, we need to test 1-7 671 */ 672 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 673 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 674 if (ret_val == E1000_SUCCESS) { 675 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 676 phy_id, phy->addr); 677 /* 678 * At the time of this writing, The M88 part is 679 * the only supported SGMII PHY product. 680 */ 681 if (phy_id == M88_VENDOR) 682 break; 683 } else { 684 DEBUGOUT1("PHY address %u was unreadable\n", 685 phy->addr); 686 } 687 } 688 689 /* A valid PHY type couldn't be found. */ 690 if (phy->addr == 8) { 691 phy->addr = 0; 692 ret_val = -E1000_ERR_PHY; 693 } else { 694 ret_val = e1000_get_phy_id(hw); 695 } 696 697 /* restore previous sfp cage power state */ 698 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 699 700 out: 701 return ret_val; 702 } 703 704 /** 705 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 706 * @hw: pointer to the HW structure 707 * 708 * Resets the PHY using the serial gigabit media independent interface. 709 **/ 710 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 711 { 712 s32 ret_val = E1000_SUCCESS; 713 struct e1000_phy_info *phy = &hw->phy; 714 715 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 716 717 /* 718 * This isn't a true "hard" reset, but is the only reset 719 * available to us at this time. 720 */ 721 722 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 723 724 if (!(hw->phy.ops.write_reg)) 725 goto out; 726 727 /* 728 * SFP documentation requires the following to configure the SPF module 729 * to work on SGMII. No further documentation is given. 730 */ 731 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 732 if (ret_val) 733 goto out; 734 735 ret_val = hw->phy.ops.commit(hw); 736 if (ret_val) 737 goto out; 738 739 if (phy->id == M88E1512_E_PHY_ID) 740 ret_val = e1000_initialize_M88E1512_phy(hw); 741 out: 742 return ret_val; 743 } 744 745 /** 746 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 747 * @hw: pointer to the HW structure 748 * @active: true to enable LPLU, false to disable 749 * 750 * Sets the LPLU D0 state according to the active flag. When 751 * activating LPLU this function also disables smart speed 752 * and vice versa. LPLU will not be activated unless the 753 * device autonegotiation advertisement meets standards of 754 * either 10 or 10/100 or 10/100/1000 at all duplexes. 755 * This is a function pointer entry point only called by 756 * PHY setup routines. 757 **/ 758 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 759 { 760 struct e1000_phy_info *phy = &hw->phy; 761 s32 ret_val = E1000_SUCCESS; 762 u16 data; 763 764 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 765 766 if (!(hw->phy.ops.read_reg)) 767 goto out; 768 769 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 770 if (ret_val) 771 goto out; 772 773 if (active) { 774 data |= IGP02E1000_PM_D0_LPLU; 775 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 776 data); 777 if (ret_val) 778 goto out; 779 780 /* When LPLU is enabled, we should disable SmartSpeed */ 781 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 782 &data); 783 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 784 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 785 data); 786 if (ret_val) 787 goto out; 788 } else { 789 data &= ~IGP02E1000_PM_D0_LPLU; 790 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 791 data); 792 /* 793 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 794 * during Dx states where the power conservation is most 795 * important. During driver activity we should enable 796 * SmartSpeed, so performance is maintained. 797 */ 798 if (phy->smart_speed == e1000_smart_speed_on) { 799 ret_val = phy->ops.read_reg(hw, 800 IGP01E1000_PHY_PORT_CONFIG, 801 &data); 802 if (ret_val) 803 goto out; 804 805 data |= IGP01E1000_PSCFR_SMART_SPEED; 806 ret_val = phy->ops.write_reg(hw, 807 IGP01E1000_PHY_PORT_CONFIG, 808 data); 809 if (ret_val) 810 goto out; 811 } else if (phy->smart_speed == e1000_smart_speed_off) { 812 ret_val = phy->ops.read_reg(hw, 813 IGP01E1000_PHY_PORT_CONFIG, 814 &data); 815 if (ret_val) 816 goto out; 817 818 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 819 ret_val = phy->ops.write_reg(hw, 820 IGP01E1000_PHY_PORT_CONFIG, 821 data); 822 if (ret_val) 823 goto out; 824 } 825 } 826 827 out: 828 return ret_val; 829 } 830 831 /** 832 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 833 * @hw: pointer to the HW structure 834 * @active: true to enable LPLU, false to disable 835 * 836 * Sets the LPLU D0 state according to the active flag. When 837 * activating LPLU this function also disables smart speed 838 * and vice versa. LPLU will not be activated unless the 839 * device autonegotiation advertisement meets standards of 840 * either 10 or 10/100 or 10/100/1000 at all duplexes. 841 * This is a function pointer entry point only called by 842 * PHY setup routines. 843 **/ 844 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 845 { 846 struct e1000_phy_info *phy = &hw->phy; 847 u32 data; 848 849 DEBUGFUNC("e1000_set_d0_lplu_state_82580"); 850 851 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 852 853 if (active) { 854 data |= E1000_82580_PM_D0_LPLU; 855 856 /* When LPLU is enabled, we should disable SmartSpeed */ 857 data &= ~E1000_82580_PM_SPD; 858 } else { 859 data &= ~E1000_82580_PM_D0_LPLU; 860 861 /* 862 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 863 * during Dx states where the power conservation is most 864 * important. During driver activity we should enable 865 * SmartSpeed, so performance is maintained. 866 */ 867 if (phy->smart_speed == e1000_smart_speed_on) 868 data |= E1000_82580_PM_SPD; 869 else if (phy->smart_speed == e1000_smart_speed_off) 870 data &= ~E1000_82580_PM_SPD; 871 } 872 873 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 874 return E1000_SUCCESS; 875 } 876 877 /** 878 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 879 * @hw: pointer to the HW structure 880 * @active: boolean used to enable/disable lplu 881 * 882 * Success returns 0, Failure returns 1 883 * 884 * The low power link up (lplu) state is set to the power management level D3 885 * and SmartSpeed is disabled when active is true, else clear lplu for D3 886 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 887 * is used during Dx states where the power conservation is most important. 888 * During driver activity, SmartSpeed should be enabled so performance is 889 * maintained. 890 **/ 891 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 892 { 893 struct e1000_phy_info *phy = &hw->phy; 894 u32 data; 895 896 DEBUGFUNC("e1000_set_d3_lplu_state_82580"); 897 898 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 899 900 if (!active) { 901 data &= ~E1000_82580_PM_D3_LPLU; 902 /* 903 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 904 * during Dx states where the power conservation is most 905 * important. During driver activity we should enable 906 * SmartSpeed, so performance is maintained. 907 */ 908 if (phy->smart_speed == e1000_smart_speed_on) 909 data |= E1000_82580_PM_SPD; 910 else if (phy->smart_speed == e1000_smart_speed_off) 911 data &= ~E1000_82580_PM_SPD; 912 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 913 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 914 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 915 data |= E1000_82580_PM_D3_LPLU; 916 /* When LPLU is enabled, we should disable SmartSpeed */ 917 data &= ~E1000_82580_PM_SPD; 918 } 919 920 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 921 return E1000_SUCCESS; 922 } 923 924 /** 925 * e1000_acquire_nvm_82575 - Request for access to EEPROM 926 * @hw: pointer to the HW structure 927 * 928 * Acquire the necessary semaphores for exclusive access to the EEPROM. 929 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 930 * Return successful if access grant bit set, else clear the request for 931 * EEPROM access and return -E1000_ERR_NVM (-1). 932 **/ 933 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 934 { 935 s32 ret_val = E1000_SUCCESS; 936 937 DEBUGFUNC("e1000_acquire_nvm_82575"); 938 939 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); 940 if (ret_val) 941 goto out; 942 943 /* 944 * Check if there is some access 945 * error this access may hook on 946 */ 947 if (hw->mac.type == e1000_i350) { 948 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 949 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT | 950 E1000_EECD_TIMEOUT)) { 951 /* Clear all access error flags */ 952 E1000_WRITE_REG(hw, E1000_EECD, eecd | 953 E1000_EECD_ERROR_CLR); 954 DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 955 } 956 } 957 958 if (hw->mac.type == e1000_82580) { 959 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 960 if (eecd & E1000_EECD_BLOCKED) { 961 /* Clear access error flag */ 962 E1000_WRITE_REG(hw, E1000_EECD, eecd | 963 E1000_EECD_BLOCKED); 964 DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 965 } 966 } 967 968 ret_val = e1000_acquire_nvm_generic(hw); 969 if (ret_val) 970 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM); 971 972 out: 973 return ret_val; 974 } 975 976 /** 977 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 978 * @hw: pointer to the HW structure 979 * 980 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 981 * then release the semaphores acquired. 982 **/ 983 static void e1000_release_nvm_82575(struct e1000_hw *hw) 984 { 985 DEBUGFUNC("e1000_release_nvm_82575"); 986 987 e1000_release_nvm_generic(hw); 988 989 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM); 990 } 991 992 /** 993 * e1000_get_cfg_done_82575 - Read config done bit 994 * @hw: pointer to the HW structure 995 * 996 * Read the management control register for the config done bit for 997 * completion status. NOTE: silicon which is EEPROM-less will fail trying 998 * to read the config done bit, so an error is *ONLY* logged and returns 999 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 1000 * would not be able to be reset or change link. 1001 **/ 1002 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 1003 { 1004 s32 timeout = PHY_CFG_TIMEOUT; 1005 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1006 1007 DEBUGFUNC("e1000_get_cfg_done_82575"); 1008 1009 if (hw->bus.func == E1000_FUNC_1) 1010 mask = E1000_NVM_CFG_DONE_PORT_1; 1011 else if (hw->bus.func == E1000_FUNC_2) 1012 mask = E1000_NVM_CFG_DONE_PORT_2; 1013 else if (hw->bus.func == E1000_FUNC_3) 1014 mask = E1000_NVM_CFG_DONE_PORT_3; 1015 while (timeout) { 1016 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 1017 break; 1018 msec_delay(1); 1019 timeout--; 1020 } 1021 if (!timeout) 1022 DEBUGOUT("MNG configuration cycle has not completed.\n"); 1023 1024 /* If EEPROM is not marked present, init the PHY manually */ 1025 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 1026 (hw->phy.type == e1000_phy_igp_3)) 1027 e1000_phy_init_script_igp3(hw); 1028 1029 return E1000_SUCCESS; 1030 } 1031 1032 /** 1033 * e1000_get_link_up_info_82575 - Get link speed/duplex info 1034 * @hw: pointer to the HW structure 1035 * @speed: stores the current speed 1036 * @duplex: stores the current duplex 1037 * 1038 * This is a wrapper function, if using the serial gigabit media independent 1039 * interface, use PCS to retrieve the link speed and duplex information. 1040 * Otherwise, use the generic function to get the link speed and duplex info. 1041 **/ 1042 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1043 u16 *duplex) 1044 { 1045 s32 ret_val; 1046 1047 DEBUGFUNC("e1000_get_link_up_info_82575"); 1048 1049 if (hw->phy.media_type != e1000_media_type_copper) 1050 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 1051 duplex); 1052 else 1053 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 1054 duplex); 1055 1056 return ret_val; 1057 } 1058 1059 /** 1060 * e1000_check_for_link_82575 - Check for link 1061 * @hw: pointer to the HW structure 1062 * 1063 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1064 * use the generic interface for determining link. 1065 **/ 1066 static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 1067 { 1068 s32 ret_val; 1069 u16 speed, duplex; 1070 1071 DEBUGFUNC("e1000_check_for_link_82575"); 1072 1073 if (hw->phy.media_type != e1000_media_type_copper) { 1074 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 1075 &duplex); 1076 /* 1077 * Use this flag to determine if link needs to be checked or 1078 * not. If we have link clear the flag so that we do not 1079 * continue to check for link. 1080 */ 1081 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1082 1083 /* 1084 * Configure Flow Control now that Auto-Neg has completed. 1085 * First, we need to restore the desired flow control 1086 * settings because we may have had to re-autoneg with a 1087 * different link partner. 1088 */ 1089 ret_val = e1000_config_fc_after_link_up_generic(hw); 1090 if (ret_val) 1091 DEBUGOUT("Error configuring flow control\n"); 1092 } else { 1093 ret_val = e1000_check_for_copper_link_generic(hw); 1094 } 1095 1096 return ret_val; 1097 } 1098 1099 /** 1100 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked 1101 * @hw: pointer to the HW structure 1102 * 1103 * Poll the M88E1112 interfaces to see which interface achieved link. 1104 */ 1105 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw) 1106 { 1107 struct e1000_phy_info *phy = &hw->phy; 1108 s32 ret_val; 1109 u16 data; 1110 u8 port = 0; 1111 1112 DEBUGFUNC("e1000_check_for_link_media_swap"); 1113 1114 /* Check for copper. */ 1115 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1116 if (ret_val) 1117 return ret_val; 1118 1119 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 1120 if (ret_val) 1121 return ret_val; 1122 1123 if (data & E1000_M88E1112_STATUS_LINK) 1124 port = E1000_MEDIA_PORT_COPPER; 1125 1126 /* Check for other. */ 1127 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); 1128 if (ret_val) 1129 return ret_val; 1130 1131 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 1132 if (ret_val) 1133 return ret_val; 1134 1135 if (data & E1000_M88E1112_STATUS_LINK) 1136 port = E1000_MEDIA_PORT_OTHER; 1137 1138 /* Determine if a swap needs to happen. */ 1139 if (port && (hw->dev_spec._82575.media_port != port)) { 1140 hw->dev_spec._82575.media_port = port; 1141 hw->dev_spec._82575.media_changed = true; 1142 } 1143 1144 if (port == E1000_MEDIA_PORT_COPPER) { 1145 /* reset page to 0 */ 1146 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1147 if (ret_val) 1148 return ret_val; 1149 e1000_check_for_link_82575(hw); 1150 } else { 1151 e1000_check_for_link_82575(hw); 1152 /* reset page to 0 */ 1153 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1154 if (ret_val) 1155 return ret_val; 1156 } 1157 1158 return E1000_SUCCESS; 1159 } 1160 1161 /** 1162 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1163 * @hw: pointer to the HW structure 1164 **/ 1165 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 1166 { 1167 u32 reg; 1168 1169 DEBUGFUNC("e1000_power_up_serdes_link_82575"); 1170 1171 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1172 !e1000_sgmii_active_82575(hw)) 1173 return; 1174 1175 /* Enable PCS to turn on link */ 1176 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1177 reg |= E1000_PCS_CFG_PCS_EN; 1178 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1179 1180 /* Power up the laser */ 1181 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1182 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1183 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1184 1185 /* flush the write to verify completion */ 1186 E1000_WRITE_FLUSH(hw); 1187 msec_delay(1); 1188 } 1189 1190 /** 1191 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1192 * @hw: pointer to the HW structure 1193 * @speed: stores the current speed 1194 * @duplex: stores the current duplex 1195 * 1196 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1197 * duplex, then store the values in the pointers provided. 1198 **/ 1199 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 1200 u16 *speed, u16 *duplex) 1201 { 1202 struct e1000_mac_info *mac = &hw->mac; 1203 u32 pcs; 1204 u32 status; 1205 1206 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 1207 1208 /* 1209 * Read the PCS Status register for link state. For non-copper mode, 1210 * the status register is not accurate. The PCS status register is 1211 * used instead. 1212 */ 1213 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1214 1215 /* 1216 * The link up bit determines when link is up on autoneg. 1217 */ 1218 if (pcs & E1000_PCS_LSTS_LINK_OK) { 1219 mac->serdes_has_link = true; 1220 1221 /* Detect and store PCS speed */ 1222 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1223 *speed = SPEED_1000; 1224 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1225 *speed = SPEED_100; 1226 else 1227 *speed = SPEED_10; 1228 1229 /* Detect and store PCS duplex */ 1230 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1231 *duplex = FULL_DUPLEX; 1232 else 1233 *duplex = HALF_DUPLEX; 1234 1235 /* Check if it is an I354 2.5Gb backplane connection. */ 1236 if (mac->type == e1000_i354) { 1237 status = E1000_READ_REG(hw, E1000_STATUS); 1238 if ((status & E1000_STATUS_2P5_SKU) && 1239 !(status & E1000_STATUS_2P5_SKU_OVER)) { 1240 *speed = SPEED_2500; 1241 *duplex = FULL_DUPLEX; 1242 DEBUGOUT("2500 Mbs, "); 1243 DEBUGOUT("Full Duplex\n"); 1244 } 1245 } 1246 1247 } else { 1248 mac->serdes_has_link = false; 1249 *speed = 0; 1250 *duplex = 0; 1251 } 1252 1253 return E1000_SUCCESS; 1254 } 1255 1256 /** 1257 * e1000_shutdown_serdes_link_82575 - Remove link during power down 1258 * @hw: pointer to the HW structure 1259 * 1260 * In the case of serdes shut down sfp and PCS on driver unload 1261 * when management pass thru is not enabled. 1262 **/ 1263 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1264 { 1265 u32 reg; 1266 1267 DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1268 1269 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1270 !e1000_sgmii_active_82575(hw)) 1271 return; 1272 1273 if (!e1000_enable_mng_pass_thru(hw)) { 1274 /* Disable PCS to turn off link */ 1275 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1276 reg &= ~E1000_PCS_CFG_PCS_EN; 1277 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1278 1279 /* shutdown the laser */ 1280 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1281 reg |= E1000_CTRL_EXT_SDP3_DATA; 1282 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1283 1284 /* flush the write to verify completion */ 1285 E1000_WRITE_FLUSH(hw); 1286 msec_delay(1); 1287 } 1288 1289 return; 1290 } 1291 1292 /** 1293 * e1000_reset_hw_82575 - Reset hardware 1294 * @hw: pointer to the HW structure 1295 * 1296 * This resets the hardware into a known state. 1297 **/ 1298 static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1299 { 1300 u32 ctrl; 1301 s32 ret_val; 1302 1303 DEBUGFUNC("e1000_reset_hw_82575"); 1304 1305 /* 1306 * Prevent the PCI-E bus from sticking if there is no TLP connection 1307 * on the last TLP read/write transaction when MAC is reset. 1308 */ 1309 ret_val = e1000_disable_pcie_master_generic(hw); 1310 if (ret_val) 1311 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1312 1313 /* set the completion timeout for interface */ 1314 ret_val = e1000_set_pcie_completion_timeout(hw); 1315 if (ret_val) 1316 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1317 1318 DEBUGOUT("Masking off all interrupts\n"); 1319 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1320 1321 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1322 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1323 E1000_WRITE_FLUSH(hw); 1324 1325 msec_delay(10); 1326 1327 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1328 1329 DEBUGOUT("Issuing a global reset to MAC\n"); 1330 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1331 1332 ret_val = e1000_get_auto_rd_done_generic(hw); 1333 if (ret_val) { 1334 /* 1335 * When auto config read does not complete, do not 1336 * return with an error. This can happen in situations 1337 * where there is no eeprom and prevents getting link. 1338 */ 1339 DEBUGOUT("Auto Read Done did not complete\n"); 1340 } 1341 1342 /* If EEPROM is not present, run manual init scripts */ 1343 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 1344 e1000_reset_init_script_82575(hw); 1345 1346 /* Clear any pending interrupt events. */ 1347 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1348 E1000_READ_REG(hw, E1000_ICR); 1349 1350 /* Install any alternate MAC address into RAR0 */ 1351 ret_val = e1000_check_alt_mac_addr_generic(hw); 1352 1353 return ret_val; 1354 } 1355 1356 /** 1357 * e1000_init_hw_82575 - Initialize hardware 1358 * @hw: pointer to the HW structure 1359 * 1360 * This inits the hardware readying it for operation. 1361 **/ 1362 static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1363 { 1364 struct e1000_mac_info *mac = &hw->mac; 1365 s32 ret_val; 1366 1367 DEBUGFUNC("e1000_init_hw_82575"); 1368 1369 /* Initialize identification LED */ 1370 ret_val = mac->ops.id_led_init(hw); 1371 if (ret_val) { 1372 DEBUGOUT("Error initializing identification LED\n"); 1373 /* This is not fatal and we should not stop init due to this */ 1374 } 1375 1376 /* Disabling VLAN filtering */ 1377 DEBUGOUT("Initializing the IEEE VLAN\n"); 1378 mac->ops.clear_vfta(hw); 1379 1380 ret_val = e1000_init_hw_base(hw); 1381 1382 /* Set the default MTU size */ 1383 hw->dev_spec._82575.mtu = 1500; 1384 1385 /* Clear all of the statistics registers (clear on read). It is 1386 * important that we do this after we have tried to establish link 1387 * because the symbol error count will increment wildly if there 1388 * is no link. 1389 */ 1390 e1000_clear_hw_cntrs_82575(hw); 1391 1392 return ret_val; 1393 } 1394 /** 1395 * e1000_setup_copper_link_82575 - Configure copper link settings 1396 * @hw: pointer to the HW structure 1397 * 1398 * Configures the link for auto-neg or forced speed and duplex. Then we check 1399 * for link, once link is established calls to configure collision distance 1400 * and flow control are called. 1401 **/ 1402 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1403 { 1404 u32 phpm_reg; 1405 u32 ctrl; 1406 s32 ret_val; 1407 1408 DEBUGFUNC("e1000_setup_copper_link_82575"); 1409 1410 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1411 ctrl |= E1000_CTRL_SLU; 1412 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1413 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1414 1415 /* Clear Go Link Disconnect bit on supported devices */ 1416 switch (hw->mac.type) { 1417 case e1000_82580: 1418 case e1000_i350: 1419 case e1000_i210: 1420 case e1000_i211: 1421 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1422 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1423 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1424 break; 1425 default: 1426 break; 1427 } 1428 1429 ret_val = e1000_setup_serdes_link_82575(hw); 1430 if (ret_val) 1431 goto out; 1432 1433 if (e1000_sgmii_active_82575(hw)) { 1434 /* allow time for SFP cage time to power up phy */ 1435 msec_delay(300); 1436 1437 ret_val = hw->phy.ops.reset(hw); 1438 if (ret_val) { 1439 DEBUGOUT("Error resetting the PHY.\n"); 1440 goto out; 1441 } 1442 } 1443 switch (hw->phy.type) { 1444 case e1000_phy_i210: 1445 /* FALLTHROUGH */ 1446 case e1000_phy_m88: 1447 switch (hw->phy.id) { 1448 case I347AT4_E_PHY_ID: 1449 /* FALLTHROUGH */ 1450 case M88E1112_E_PHY_ID: 1451 /* FALLTHROUGH */ 1452 case M88E1340M_E_PHY_ID: 1453 /* FALLTHROUGH */ 1454 case M88E1543_E_PHY_ID: 1455 /* FALLTHROUGH */ 1456 case M88E1512_E_PHY_ID: 1457 /* FALLTHROUGH */ 1458 case I210_I_PHY_ID: 1459 ret_val = e1000_copper_link_setup_m88_gen2(hw); 1460 break; 1461 default: 1462 ret_val = e1000_copper_link_setup_m88(hw); 1463 break; 1464 } 1465 break; 1466 case e1000_phy_igp_3: 1467 ret_val = e1000_copper_link_setup_igp(hw); 1468 break; 1469 case e1000_phy_82580: 1470 ret_val = e1000_copper_link_setup_82577(hw); 1471 break; 1472 default: 1473 ret_val = -E1000_ERR_PHY; 1474 break; 1475 } 1476 1477 if (ret_val) 1478 goto out; 1479 1480 ret_val = e1000_setup_copper_link_generic(hw); 1481 out: 1482 return ret_val; 1483 } 1484 1485 /** 1486 * e1000_setup_serdes_link_82575 - Setup link for serdes 1487 * @hw: pointer to the HW structure 1488 * 1489 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1490 * used on copper connections where the serialized gigabit media independent 1491 * interface (sgmii), or serdes fiber is being used. Configures the link 1492 * for auto-negotiation or forces speed/duplex. 1493 **/ 1494 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1495 { 1496 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1497 bool pcs_autoneg; 1498 s32 ret_val = E1000_SUCCESS; 1499 u16 data; 1500 1501 DEBUGFUNC("e1000_setup_serdes_link_82575"); 1502 1503 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1504 !e1000_sgmii_active_82575(hw)) 1505 return ret_val; 1506 1507 /* 1508 * On the 82575, SerDes loopback mode persists until it is 1509 * explicitly turned off or a power cycle is performed. A read to 1510 * the register does not indicate its status. Therefore, we ensure 1511 * loopback mode is disabled during initialization. 1512 */ 1513 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1514 1515 /* power on the sfp cage if present */ 1516 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1517 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1518 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1519 1520 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1521 ctrl_reg |= E1000_CTRL_SLU; 1522 1523 /* set both sw defined pins on 82575/82576*/ 1524 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1525 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1526 1527 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1528 1529 /* default pcs_autoneg to the same setting as mac autoneg */ 1530 pcs_autoneg = hw->mac.autoneg; 1531 1532 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1533 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1534 /* sgmii mode lets the phy handle forcing speed/duplex */ 1535 pcs_autoneg = true; 1536 /* autoneg time out should be disabled for SGMII mode */ 1537 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1538 break; 1539 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1540 /* disable PCS autoneg and support parallel detect only */ 1541 pcs_autoneg = false; 1542 /* FALLTHROUGH */ 1543 default: 1544 if (hw->mac.type == e1000_82575 || 1545 hw->mac.type == e1000_82576) { 1546 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1547 if (ret_val) { 1548 DEBUGOUT("NVM Read Error\n"); 1549 return ret_val; 1550 } 1551 1552 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1553 pcs_autoneg = false; 1554 } 1555 1556 /* 1557 * non-SGMII modes only supports a speed of 1000/Full for the 1558 * link so it is best to just force the MAC and let the pcs 1559 * link either autoneg or be forced to 1000/Full 1560 */ 1561 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1562 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1563 1564 /* set speed of 1000/Full if speed/duplex is forced */ 1565 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1566 break; 1567 } 1568 1569 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1570 1571 /* 1572 * New SerDes mode allows for forcing speed or autonegotiating speed 1573 * at 1gb. Autoneg should be default set by most drivers. This is the 1574 * mode that will be compatible with older link partners and switches. 1575 * However, both are supported by the hardware and some drivers/tools. 1576 */ 1577 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1578 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1579 1580 if (pcs_autoneg) { 1581 /* Set PCS register for autoneg */ 1582 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1583 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1584 1585 /* Disable force flow control for autoneg */ 1586 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1587 1588 /* Configure flow control advertisement for autoneg */ 1589 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1590 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1591 1592 switch (hw->fc.requested_mode) { 1593 case e1000_fc_full: 1594 case e1000_fc_rx_pause: 1595 anadv_reg |= E1000_TXCW_ASM_DIR; 1596 anadv_reg |= E1000_TXCW_PAUSE; 1597 break; 1598 case e1000_fc_tx_pause: 1599 anadv_reg |= E1000_TXCW_ASM_DIR; 1600 break; 1601 default: 1602 break; 1603 } 1604 1605 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg); 1606 1607 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1608 } else { 1609 /* Set PCS register for forced link */ 1610 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1611 1612 /* Force flow control for forced link */ 1613 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1614 1615 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1616 } 1617 1618 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1619 1620 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw)) 1621 e1000_force_mac_fc_generic(hw); 1622 1623 return ret_val; 1624 } 1625 1626 /** 1627 * e1000_get_media_type_82575 - derives current media type. 1628 * @hw: pointer to the HW structure 1629 * 1630 * The media type is chosen reflecting few settings. 1631 * The following are taken into account: 1632 * - link mode set in the current port Init Control Word #3 1633 * - current link mode settings in CSR register 1634 * - MDIO vs. I2C PHY control interface chosen 1635 * - SFP module media type 1636 **/ 1637 static s32 e1000_get_media_type_82575(struct e1000_hw *hw) 1638 { 1639 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1640 s32 ret_val = E1000_SUCCESS; 1641 u32 ctrl_ext = 0; 1642 u32 link_mode = 0; 1643 1644 /* Set internal phy as default */ 1645 dev_spec->sgmii_active = false; 1646 dev_spec->module_plugged = false; 1647 1648 /* Get CSR setting */ 1649 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1650 1651 /* extract link mode setting */ 1652 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 1653 1654 switch (link_mode) { 1655 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1656 hw->phy.media_type = e1000_media_type_internal_serdes; 1657 break; 1658 case E1000_CTRL_EXT_LINK_MODE_GMII: 1659 hw->phy.media_type = e1000_media_type_copper; 1660 break; 1661 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1662 /* Get phy control interface type set (MDIO vs. I2C)*/ 1663 if (e1000_sgmii_uses_mdio_82575(hw)) { 1664 hw->phy.media_type = e1000_media_type_copper; 1665 dev_spec->sgmii_active = true; 1666 break; 1667 } 1668 /* fall through for I2C based SGMII */ 1669 /* FALLTHROUGH */ 1670 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1671 /* read media type from SFP EEPROM */ 1672 ret_val = e1000_set_sfp_media_type_82575(hw); 1673 if ((ret_val != E1000_SUCCESS) || 1674 (hw->phy.media_type == e1000_media_type_unknown)) { 1675 /* 1676 * If media type was not identified then return media 1677 * type defined by the CTRL_EXT settings. 1678 */ 1679 hw->phy.media_type = e1000_media_type_internal_serdes; 1680 1681 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 1682 hw->phy.media_type = e1000_media_type_copper; 1683 dev_spec->sgmii_active = true; 1684 } 1685 1686 break; 1687 } 1688 1689 /* do not change link mode for 100BaseFX */ 1690 if (dev_spec->eth_flags.e100_base_fx) 1691 break; 1692 1693 /* change current link mode setting */ 1694 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1695 1696 if (hw->phy.media_type == e1000_media_type_copper) 1697 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 1698 else 1699 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1700 1701 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1702 1703 break; 1704 } 1705 1706 return ret_val; 1707 } 1708 1709 /** 1710 * e1000_set_sfp_media_type_82575 - derives SFP module media type. 1711 * @hw: pointer to the HW structure 1712 * 1713 * The media type is chosen based on SFP module. 1714 * compatibility flags retrieved from SFP ID EEPROM. 1715 **/ 1716 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) 1717 { 1718 s32 ret_val = E1000_ERR_CONFIG; 1719 u32 ctrl_ext = 0; 1720 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1721 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags; 1722 u8 tranceiver_type = 0; 1723 s32 timeout = 3; 1724 1725 /* Turn I2C interface ON and power on sfp cage */ 1726 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1727 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1728 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 1729 1730 E1000_WRITE_FLUSH(hw); 1731 1732 /* Read SFP module data */ 1733 while (timeout) { 1734 ret_val = e1000_read_sfp_data_byte(hw, 1735 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 1736 &tranceiver_type); 1737 if (ret_val == E1000_SUCCESS) 1738 break; 1739 msec_delay(100); 1740 timeout--; 1741 } 1742 if (ret_val != E1000_SUCCESS) 1743 goto out; 1744 1745 ret_val = e1000_read_sfp_data_byte(hw, 1746 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 1747 (u8 *)eth_flags); 1748 if (ret_val != E1000_SUCCESS) 1749 goto out; 1750 1751 /* Check if there is some SFP module plugged and powered */ 1752 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 1753 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 1754 dev_spec->module_plugged = true; 1755 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 1756 hw->phy.media_type = e1000_media_type_internal_serdes; 1757 } else if (eth_flags->e100_base_fx) { 1758 dev_spec->sgmii_active = true; 1759 hw->phy.media_type = e1000_media_type_internal_serdes; 1760 } else if (eth_flags->e1000_base_t) { 1761 dev_spec->sgmii_active = true; 1762 hw->phy.media_type = e1000_media_type_copper; 1763 } else { 1764 hw->phy.media_type = e1000_media_type_unknown; 1765 DEBUGOUT("PHY module has not been recognized\n"); 1766 goto out; 1767 } 1768 } else { 1769 hw->phy.media_type = e1000_media_type_unknown; 1770 } 1771 ret_val = E1000_SUCCESS; 1772 out: 1773 /* Restore I2C interface setting */ 1774 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1775 return ret_val; 1776 } 1777 1778 /** 1779 * e1000_valid_led_default_82575 - Verify a valid default LED config 1780 * @hw: pointer to the HW structure 1781 * @data: pointer to the NVM (EEPROM) 1782 * 1783 * Read the EEPROM for the current default LED configuration. If the 1784 * LED configuration is not valid, set to a valid LED configuration. 1785 **/ 1786 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1787 { 1788 s32 ret_val; 1789 1790 DEBUGFUNC("e1000_valid_led_default_82575"); 1791 1792 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1793 if (ret_val) { 1794 DEBUGOUT("NVM Read Error\n"); 1795 goto out; 1796 } 1797 1798 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1799 switch (hw->phy.media_type) { 1800 case e1000_media_type_internal_serdes: 1801 *data = ID_LED_DEFAULT_82575_SERDES; 1802 break; 1803 case e1000_media_type_copper: 1804 default: 1805 *data = ID_LED_DEFAULT; 1806 break; 1807 } 1808 } 1809 out: 1810 return ret_val; 1811 } 1812 1813 /** 1814 * e1000_sgmii_active_82575 - Return sgmii state 1815 * @hw: pointer to the HW structure 1816 * 1817 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1818 * which can be enabled for use in the embedded applications. Simply 1819 * return the current state of the sgmii interface. 1820 **/ 1821 static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1822 { 1823 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1824 return dev_spec->sgmii_active; 1825 } 1826 1827 /** 1828 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1829 * @hw: pointer to the HW structure 1830 * 1831 * Inits recommended HW defaults after a reset when there is no EEPROM 1832 * detected. This is only for the 82575. 1833 **/ 1834 s32 e1000_reset_init_script_82575(struct e1000_hw *hw) 1835 { 1836 DEBUGFUNC("e1000_reset_init_script_82575"); 1837 1838 if (hw->mac.type == e1000_82575) { 1839 DEBUGOUT("Running reset init script for 82575\n"); 1840 /* SerDes configuration via SERDESCTRL */ 1841 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1842 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1843 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1844 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1845 1846 /* CCM configuration via CCMCTL register */ 1847 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1848 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1849 1850 /* PCIe lanes configuration */ 1851 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1852 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1853 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1854 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1855 1856 /* PCIe PLL Configuration */ 1857 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1858 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1859 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1860 } 1861 1862 return E1000_SUCCESS; 1863 } 1864 1865 /** 1866 * e1000_read_mac_addr_82575 - Read device MAC address 1867 * @hw: pointer to the HW structure 1868 **/ 1869 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1870 { 1871 s32 ret_val; 1872 1873 DEBUGFUNC("e1000_read_mac_addr_82575"); 1874 1875 /* 1876 * If there's an alternate MAC address place it in RAR0 1877 * so that it will override the Si installed default perm 1878 * address. 1879 */ 1880 ret_val = e1000_check_alt_mac_addr_generic(hw); 1881 if (ret_val) 1882 goto out; 1883 1884 ret_val = e1000_read_mac_addr_generic(hw); 1885 1886 out: 1887 return ret_val; 1888 } 1889 1890 /** 1891 * e1000_config_collision_dist_82575 - Configure collision distance 1892 * @hw: pointer to the HW structure 1893 * 1894 * Configures the collision distance to the default value and is used 1895 * during link setup. 1896 **/ 1897 static void e1000_config_collision_dist_82575(struct e1000_hw *hw) 1898 { 1899 u32 tctl_ext; 1900 1901 DEBUGFUNC("e1000_config_collision_dist_82575"); 1902 1903 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 1904 1905 tctl_ext &= ~E1000_TCTL_EXT_COLD; 1906 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 1907 1908 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 1909 E1000_WRITE_FLUSH(hw); 1910 } 1911 1912 /** 1913 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1914 * @hw: pointer to the HW structure 1915 * 1916 * Clears the hardware counters by reading the counter registers. 1917 **/ 1918 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1919 { 1920 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1921 1922 e1000_clear_hw_cntrs_base_generic(hw); 1923 1924 E1000_READ_REG(hw, E1000_PRC64); 1925 E1000_READ_REG(hw, E1000_PRC127); 1926 E1000_READ_REG(hw, E1000_PRC255); 1927 E1000_READ_REG(hw, E1000_PRC511); 1928 E1000_READ_REG(hw, E1000_PRC1023); 1929 E1000_READ_REG(hw, E1000_PRC1522); 1930 E1000_READ_REG(hw, E1000_PTC64); 1931 E1000_READ_REG(hw, E1000_PTC127); 1932 E1000_READ_REG(hw, E1000_PTC255); 1933 E1000_READ_REG(hw, E1000_PTC511); 1934 E1000_READ_REG(hw, E1000_PTC1023); 1935 E1000_READ_REG(hw, E1000_PTC1522); 1936 1937 E1000_READ_REG(hw, E1000_ALGNERRC); 1938 E1000_READ_REG(hw, E1000_RXERRC); 1939 E1000_READ_REG(hw, E1000_TNCRS); 1940 E1000_READ_REG(hw, E1000_CEXTERR); 1941 E1000_READ_REG(hw, E1000_TSCTC); 1942 E1000_READ_REG(hw, E1000_TSCTFC); 1943 1944 E1000_READ_REG(hw, E1000_MGTPRC); 1945 E1000_READ_REG(hw, E1000_MGTPDC); 1946 E1000_READ_REG(hw, E1000_MGTPTC); 1947 1948 E1000_READ_REG(hw, E1000_IAC); 1949 E1000_READ_REG(hw, E1000_ICRXOC); 1950 1951 E1000_READ_REG(hw, E1000_ICRXPTC); 1952 E1000_READ_REG(hw, E1000_ICRXATC); 1953 E1000_READ_REG(hw, E1000_ICTXPTC); 1954 E1000_READ_REG(hw, E1000_ICTXATC); 1955 E1000_READ_REG(hw, E1000_ICTXQEC); 1956 E1000_READ_REG(hw, E1000_ICTXQMTC); 1957 E1000_READ_REG(hw, E1000_ICRXDMTC); 1958 1959 E1000_READ_REG(hw, E1000_CBTMPC); 1960 E1000_READ_REG(hw, E1000_HTDPMC); 1961 E1000_READ_REG(hw, E1000_CBRMPC); 1962 E1000_READ_REG(hw, E1000_RPTHC); 1963 E1000_READ_REG(hw, E1000_HGPTC); 1964 E1000_READ_REG(hw, E1000_HTCBDPC); 1965 E1000_READ_REG(hw, E1000_HGORCL); 1966 E1000_READ_REG(hw, E1000_HGORCH); 1967 E1000_READ_REG(hw, E1000_HGOTCL); 1968 E1000_READ_REG(hw, E1000_HGOTCH); 1969 E1000_READ_REG(hw, E1000_LENERRS); 1970 1971 /* This register should not be read in copper configurations */ 1972 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 1973 e1000_sgmii_active_82575(hw)) 1974 E1000_READ_REG(hw, E1000_SCVPC); 1975 } 1976 1977 /** 1978 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 1979 * @hw: pointer to the HW structure 1980 * 1981 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1982 * however the hardware default for these parts is 500us to 1ms which is less 1983 * than the 10ms recommended by the pci-e spec. To address this we need to 1984 * increase the value to either 10ms to 200ms for capability version 1 config, 1985 * or 16ms to 55ms for version 2. 1986 **/ 1987 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 1988 { 1989 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 1990 s32 ret_val = E1000_SUCCESS; 1991 u16 pcie_devctl2; 1992 1993 /* only take action if timeout value is defaulted to 0 */ 1994 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1995 goto out; 1996 1997 /* 1998 * if capababilities version is type 1 we can write the 1999 * timeout of 10ms to 200ms through the GCR register 2000 */ 2001 if (!(gcr & E1000_GCR_CAP_VER2)) { 2002 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2003 goto out; 2004 } 2005 2006 /* 2007 * for version 2 capabilities we need to write the config space 2008 * directly in order to set the completion timeout value for 2009 * 16ms to 55ms 2010 */ 2011 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2012 &pcie_devctl2); 2013 if (ret_val) 2014 goto out; 2015 2016 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2017 2018 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2019 &pcie_devctl2); 2020 out: 2021 /* disable completion timeout resend */ 2022 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2023 2024 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2025 return ret_val; 2026 } 2027 2028 /** 2029 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2030 * @hw: pointer to the hardware struct 2031 * @enable: state to enter, either enabled or disabled 2032 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2033 * 2034 * enables/disables L2 switch anti-spoofing functionality. 2035 **/ 2036 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2037 { 2038 u32 reg_val, reg_offset; 2039 2040 switch (hw->mac.type) { 2041 case e1000_82576: 2042 reg_offset = E1000_DTXSWC; 2043 break; 2044 case e1000_i350: 2045 case e1000_i354: 2046 reg_offset = E1000_TXSWC; 2047 break; 2048 default: 2049 return; 2050 } 2051 2052 reg_val = E1000_READ_REG(hw, reg_offset); 2053 if (enable) { 2054 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2055 E1000_DTXSWC_VLAN_SPOOF_MASK); 2056 /* The PF can spoof - it has to in order to 2057 * support emulation mode NICs 2058 */ 2059 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 2060 } else { 2061 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2062 E1000_DTXSWC_VLAN_SPOOF_MASK); 2063 } 2064 E1000_WRITE_REG(hw, reg_offset, reg_val); 2065 } 2066 2067 /** 2068 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 2069 * @hw: pointer to the hardware struct 2070 * @enable: state to enter, either enabled or disabled 2071 * 2072 * enables/disables L2 switch loopback functionality. 2073 **/ 2074 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2075 { 2076 u32 dtxswc; 2077 2078 switch (hw->mac.type) { 2079 case e1000_82576: 2080 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2081 if (enable) 2082 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2083 else 2084 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2085 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2086 break; 2087 case e1000_i350: 2088 case e1000_i354: 2089 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2090 if (enable) 2091 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2092 else 2093 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2094 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2095 break; 2096 default: 2097 /* Currently no other hardware supports loopback */ 2098 break; 2099 } 2100 2101 2102 } 2103 2104 /** 2105 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 2106 * @hw: pointer to the hardware struct 2107 * @enable: state to enter, either enabled or disabled 2108 * 2109 * enables/disables replication of packets across multiple pools. 2110 **/ 2111 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2112 { 2113 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 2114 2115 if (enable) 2116 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2117 else 2118 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2119 2120 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 2121 } 2122 2123 /** 2124 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 2125 * @hw: pointer to the HW structure 2126 * @offset: register offset to be read 2127 * @data: pointer to the read data 2128 * 2129 * Reads the MDI control register in the PHY at offset and stores the 2130 * information read to data. 2131 **/ 2132 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2133 { 2134 s32 ret_val; 2135 2136 DEBUGFUNC("e1000_read_phy_reg_82580"); 2137 2138 ret_val = hw->phy.ops.acquire(hw); 2139 if (ret_val) 2140 goto out; 2141 2142 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 2143 2144 hw->phy.ops.release(hw); 2145 2146 out: 2147 return ret_val; 2148 } 2149 2150 /** 2151 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 2152 * @hw: pointer to the HW structure 2153 * @offset: register offset to write to 2154 * @data: data to write to register at offset 2155 * 2156 * Writes data to MDI control register in the PHY at offset. 2157 **/ 2158 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2159 { 2160 s32 ret_val; 2161 2162 DEBUGFUNC("e1000_write_phy_reg_82580"); 2163 2164 ret_val = hw->phy.ops.acquire(hw); 2165 if (ret_val) 2166 goto out; 2167 2168 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 2169 2170 hw->phy.ops.release(hw); 2171 2172 out: 2173 return ret_val; 2174 } 2175 2176 /** 2177 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2178 * @hw: pointer to the HW structure 2179 * 2180 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2181 * the values found in the EEPROM. This addresses an issue in which these 2182 * bits are not restored from EEPROM after reset. 2183 **/ 2184 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 2185 { 2186 s32 ret_val = E1000_SUCCESS; 2187 u32 mdicnfg; 2188 u16 nvm_data = 0; 2189 2190 DEBUGFUNC("e1000_reset_mdicnfg_82580"); 2191 2192 if (hw->mac.type != e1000_82580) 2193 goto out; 2194 if (!e1000_sgmii_active_82575(hw)) 2195 goto out; 2196 2197 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2198 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2199 &nvm_data); 2200 if (ret_val) { 2201 DEBUGOUT("NVM Read Error\n"); 2202 goto out; 2203 } 2204 2205 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 2206 if (nvm_data & NVM_WORD24_EXT_MDIO) 2207 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2208 if (nvm_data & NVM_WORD24_COM_MDIO) 2209 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2210 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 2211 out: 2212 return ret_val; 2213 } 2214 2215 /** 2216 * e1000_reset_hw_82580 - Reset hardware 2217 * @hw: pointer to the HW structure 2218 * 2219 * This resets function or entire device (all ports, etc.) 2220 * to a known state. 2221 **/ 2222 static s32 e1000_reset_hw_82580(struct e1000_hw *hw) 2223 { 2224 s32 ret_val = E1000_SUCCESS; 2225 /* BH SW mailbox bit in SW_FW_SYNC */ 2226 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2227 u32 ctrl; 2228 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2229 2230 DEBUGFUNC("e1000_reset_hw_82580"); 2231 2232 hw->dev_spec._82575.global_device_reset = false; 2233 2234 /* 82580 does not reliably do global_device_reset due to hw errata */ 2235 if (hw->mac.type == e1000_82580) 2236 global_device_reset = false; 2237 2238 /* Get current control state. */ 2239 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2240 2241 /* 2242 * Prevent the PCI-E bus from sticking if there is no TLP connection 2243 * on the last TLP read/write transaction when MAC is reset. 2244 */ 2245 ret_val = e1000_disable_pcie_master_generic(hw); 2246 if (ret_val) 2247 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2248 2249 DEBUGOUT("Masking off all interrupts\n"); 2250 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2251 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2252 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2253 E1000_WRITE_FLUSH(hw); 2254 2255 msec_delay(10); 2256 2257 /* Determine whether or not a global dev reset is requested */ 2258 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw, 2259 swmbsw_mask)) 2260 global_device_reset = false; 2261 2262 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) & 2263 E1000_STAT_DEV_RST_SET)) 2264 ctrl |= E1000_CTRL_DEV_RST; 2265 else 2266 ctrl |= E1000_CTRL_RST; 2267 2268 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2269 2270 switch (hw->device_id) { 2271 case E1000_DEV_ID_DH89XXCC_SGMII: 2272 break; 2273 default: 2274 E1000_WRITE_FLUSH(hw); 2275 break; 2276 } 2277 2278 /* Add delay to insure DEV_RST or RST has time to complete */ 2279 msec_delay(5); 2280 2281 ret_val = e1000_get_auto_rd_done_generic(hw); 2282 if (ret_val) { 2283 /* 2284 * When auto config read does not complete, do not 2285 * return with an error. This can happen in situations 2286 * where there is no eeprom and prevents getting link. 2287 */ 2288 DEBUGOUT("Auto Read Done did not complete\n"); 2289 } 2290 2291 /* clear global device reset status bit */ 2292 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 2293 2294 /* Clear any pending interrupt events. */ 2295 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2296 E1000_READ_REG(hw, E1000_ICR); 2297 2298 ret_val = e1000_reset_mdicnfg_82580(hw); 2299 if (ret_val) 2300 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 2301 2302 /* Install any alternate MAC address into RAR0 */ 2303 ret_val = e1000_check_alt_mac_addr_generic(hw); 2304 2305 /* Release semaphore */ 2306 if (global_device_reset) 2307 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2308 2309 return ret_val; 2310 } 2311 2312 /** 2313 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size 2314 * @data: data received by reading RXPBS register 2315 * 2316 * The 82580 uses a table based approach for packet buffer allocation sizes. 2317 * This function converts the retrieved value into the correct table value 2318 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2319 * 0x0 36 72 144 1 2 4 8 16 2320 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2321 */ 2322 u16 e1000_rxpbs_adjust_82580(u32 data) 2323 { 2324 u16 ret_val = 0; 2325 2326 if (data < E1000_82580_RXPBS_TABLE_SIZE) 2327 ret_val = e1000_82580_rxpbs_table[data]; 2328 2329 return ret_val; 2330 } 2331 2332 /** 2333 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM 2334 * checksum 2335 * @hw: pointer to the HW structure 2336 * @offset: offset in words of the checksum protected region 2337 * 2338 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2339 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2340 **/ 2341 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2342 { 2343 s32 ret_val = E1000_SUCCESS; 2344 u16 checksum = 0; 2345 u16 i, nvm_data; 2346 2347 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); 2348 2349 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2350 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2351 if (ret_val) { 2352 DEBUGOUT("NVM Read Error\n"); 2353 goto out; 2354 } 2355 checksum += nvm_data; 2356 } 2357 2358 if (checksum != (u16) NVM_SUM) { 2359 DEBUGOUT("NVM Checksum Invalid\n"); 2360 ret_val = -E1000_ERR_NVM; 2361 goto out; 2362 } 2363 2364 out: 2365 return ret_val; 2366 } 2367 2368 /** 2369 * e1000_update_nvm_checksum_with_offset - Update EEPROM 2370 * checksum 2371 * @hw: pointer to the HW structure 2372 * @offset: offset in words of the checksum protected region 2373 * 2374 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2375 * up to the checksum. Then calculates the EEPROM checksum and writes the 2376 * value to the EEPROM. 2377 **/ 2378 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2379 { 2380 s32 ret_val; 2381 u16 checksum = 0; 2382 u16 i, nvm_data; 2383 2384 DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); 2385 2386 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2387 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2388 if (ret_val) { 2389 DEBUGOUT("NVM Read Error while updating checksum.\n"); 2390 goto out; 2391 } 2392 checksum += nvm_data; 2393 } 2394 checksum = (u16) NVM_SUM - checksum; 2395 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2396 &checksum); 2397 if (ret_val) 2398 DEBUGOUT("NVM Write Error while updating checksum.\n"); 2399 2400 out: 2401 return ret_val; 2402 } 2403 2404 /** 2405 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum 2406 * @hw: pointer to the HW structure 2407 * 2408 * Calculates the EEPROM section checksum by reading/adding each word of 2409 * the EEPROM and then verifies that the sum of the EEPROM is 2410 * equal to 0xBABA. 2411 **/ 2412 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) 2413 { 2414 s32 ret_val; 2415 u16 eeprom_regions_count = 1; 2416 u16 j, nvm_data; 2417 u16 nvm_offset; 2418 2419 DEBUGFUNC("e1000_validate_nvm_checksum_82580"); 2420 2421 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2422 if (ret_val) { 2423 DEBUGOUT("NVM Read Error\n"); 2424 goto out; 2425 } 2426 2427 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2428 /* if checksums compatibility bit is set validate checksums 2429 * for all 4 ports. */ 2430 eeprom_regions_count = 4; 2431 } 2432 2433 for (j = 0; j < eeprom_regions_count; j++) { 2434 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2435 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2436 nvm_offset); 2437 if (ret_val != E1000_SUCCESS) 2438 goto out; 2439 } 2440 2441 out: 2442 return ret_val; 2443 } 2444 2445 /** 2446 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum 2447 * @hw: pointer to the HW structure 2448 * 2449 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2450 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2451 * checksum and writes the value to the EEPROM. 2452 **/ 2453 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) 2454 { 2455 s32 ret_val; 2456 u16 j, nvm_data; 2457 u16 nvm_offset; 2458 2459 DEBUGFUNC("e1000_update_nvm_checksum_82580"); 2460 2461 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2462 if (ret_val) { 2463 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n"); 2464 goto out; 2465 } 2466 2467 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) { 2468 /* set compatibility bit to validate checksums appropriately */ 2469 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2470 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2471 &nvm_data); 2472 if (ret_val) { 2473 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n"); 2474 goto out; 2475 } 2476 } 2477 2478 for (j = 0; j < 4; j++) { 2479 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2480 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2481 if (ret_val) 2482 goto out; 2483 } 2484 2485 out: 2486 return ret_val; 2487 } 2488 2489 /** 2490 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum 2491 * @hw: pointer to the HW structure 2492 * 2493 * Calculates the EEPROM section checksum by reading/adding each word of 2494 * the EEPROM and then verifies that the sum of the EEPROM is 2495 * equal to 0xBABA. 2496 **/ 2497 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) 2498 { 2499 s32 ret_val = E1000_SUCCESS; 2500 u16 j; 2501 u16 nvm_offset; 2502 2503 DEBUGFUNC("e1000_validate_nvm_checksum_i350"); 2504 2505 for (j = 0; j < 4; j++) { 2506 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2507 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2508 nvm_offset); 2509 if (ret_val != E1000_SUCCESS) 2510 goto out; 2511 } 2512 2513 out: 2514 return ret_val; 2515 } 2516 2517 /** 2518 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum 2519 * @hw: pointer to the HW structure 2520 * 2521 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2522 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2523 * checksum and writes the value to the EEPROM. 2524 **/ 2525 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) 2526 { 2527 s32 ret_val = E1000_SUCCESS; 2528 u16 j; 2529 u16 nvm_offset; 2530 2531 DEBUGFUNC("e1000_update_nvm_checksum_i350"); 2532 2533 for (j = 0; j < 4; j++) { 2534 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2535 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2536 if (ret_val != E1000_SUCCESS) 2537 goto out; 2538 } 2539 2540 out: 2541 return ret_val; 2542 } 2543 2544 /** 2545 * __e1000_access_emi_reg - Read/write EMI register 2546 * @hw: pointer to the HW structure 2547 * @address: EMI address to program 2548 * @data: pointer to value to read/write from/to the EMI address 2549 * @read: boolean flag to indicate read or write 2550 **/ 2551 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address, 2552 u16 *data, bool read) 2553 { 2554 s32 ret_val; 2555 2556 DEBUGFUNC("__e1000_access_emi_reg"); 2557 2558 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); 2559 if (ret_val) 2560 return ret_val; 2561 2562 if (read) 2563 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); 2564 else 2565 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); 2566 2567 return ret_val; 2568 } 2569 2570 /** 2571 * e1000_read_emi_reg - Read Extended Management Interface register 2572 * @hw: pointer to the HW structure 2573 * @addr: EMI address to program 2574 * @data: value to be read from the EMI address 2575 **/ 2576 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) 2577 { 2578 DEBUGFUNC("e1000_read_emi_reg"); 2579 2580 return __e1000_access_emi_reg(hw, addr, data, true); 2581 } 2582 2583 /** 2584 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY 2585 * @hw: pointer to the HW structure 2586 * 2587 * Initialize Marvell 1512 to work correctly with Avoton. 2588 **/ 2589 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw) 2590 { 2591 struct e1000_phy_info *phy = &hw->phy; 2592 s32 ret_val = E1000_SUCCESS; 2593 2594 DEBUGFUNC("e1000_initialize_M88E1512_phy"); 2595 2596 /* Check if this is correct PHY. */ 2597 if (phy->id != M88E1512_E_PHY_ID) 2598 goto out; 2599 2600 /* Switch to PHY page 0xFF. */ 2601 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2602 if (ret_val) 2603 goto out; 2604 2605 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2606 if (ret_val) 2607 goto out; 2608 2609 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2610 if (ret_val) 2611 goto out; 2612 2613 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2614 if (ret_val) 2615 goto out; 2616 2617 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2618 if (ret_val) 2619 goto out; 2620 2621 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2622 if (ret_val) 2623 goto out; 2624 2625 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2626 if (ret_val) 2627 goto out; 2628 2629 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C); 2630 if (ret_val) 2631 goto out; 2632 2633 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2634 if (ret_val) 2635 goto out; 2636 2637 /* Switch to PHY page 0xFB. */ 2638 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2639 if (ret_val) 2640 goto out; 2641 2642 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D); 2643 if (ret_val) 2644 goto out; 2645 2646 /* Switch to PHY page 0x12. */ 2647 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2648 if (ret_val) 2649 goto out; 2650 2651 /* Change mode to SGMII-to-Copper */ 2652 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2653 if (ret_val) 2654 goto out; 2655 2656 /* Return the PHY to page 0. */ 2657 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2658 if (ret_val) 2659 goto out; 2660 2661 ret_val = phy->ops.commit(hw); 2662 if (ret_val) { 2663 DEBUGOUT("Error committing the PHY changes\n"); 2664 return ret_val; 2665 } 2666 2667 msec_delay(1000); 2668 out: 2669 return ret_val; 2670 } 2671 2672 /** 2673 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY 2674 * @hw: pointer to the HW structure 2675 * 2676 * Initialize Marvell 1543 to work correctly with Avoton. 2677 **/ 2678 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw) 2679 { 2680 struct e1000_phy_info *phy = &hw->phy; 2681 s32 ret_val = E1000_SUCCESS; 2682 2683 DEBUGFUNC("e1000_initialize_M88E1543_phy"); 2684 2685 /* Check if this is correct PHY. */ 2686 if (phy->id != M88E1543_E_PHY_ID) 2687 goto out; 2688 2689 /* Switch to PHY page 0xFF. */ 2690 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2691 if (ret_val) 2692 goto out; 2693 2694 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2695 if (ret_val) 2696 goto out; 2697 2698 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2699 if (ret_val) 2700 goto out; 2701 2702 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2703 if (ret_val) 2704 goto out; 2705 2706 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2707 if (ret_val) 2708 goto out; 2709 2710 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2711 if (ret_val) 2712 goto out; 2713 2714 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2715 if (ret_val) 2716 goto out; 2717 2718 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C); 2719 if (ret_val) 2720 goto out; 2721 2722 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2723 if (ret_val) 2724 goto out; 2725 2726 /* Switch to PHY page 0xFB. */ 2727 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2728 if (ret_val) 2729 goto out; 2730 2731 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D); 2732 if (ret_val) 2733 goto out; 2734 2735 /* Switch to PHY page 0x12. */ 2736 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2737 if (ret_val) 2738 goto out; 2739 2740 /* Change mode to SGMII-to-Copper */ 2741 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2742 if (ret_val) 2743 goto out; 2744 2745 /* Switch to PHY page 1. */ 2746 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1); 2747 if (ret_val) 2748 goto out; 2749 2750 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */ 2751 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140); 2752 if (ret_val) 2753 goto out; 2754 2755 /* Return the PHY to page 0. */ 2756 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2757 if (ret_val) 2758 goto out; 2759 2760 ret_val = phy->ops.commit(hw); 2761 if (ret_val) { 2762 DEBUGOUT("Error committing the PHY changes\n"); 2763 return ret_val; 2764 } 2765 2766 msec_delay(1000); 2767 out: 2768 return ret_val; 2769 } 2770 2771 /** 2772 * e1000_set_eee_i350 - Enable/disable EEE support 2773 * @hw: pointer to the HW structure 2774 * @adv1G: boolean flag enabling 1G EEE advertisement 2775 * @adv100M: boolean flag enabling 100M EEE advertisement 2776 * 2777 * Enable/disable EEE based on setting in dev_spec structure. 2778 * 2779 **/ 2780 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) 2781 { 2782 u32 ipcnfg, eeer; 2783 2784 DEBUGFUNC("e1000_set_eee_i350"); 2785 2786 if ((hw->mac.type < e1000_i350) || 2787 (hw->phy.media_type != e1000_media_type_copper)) 2788 goto out; 2789 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); 2790 eeer = E1000_READ_REG(hw, E1000_EEER); 2791 2792 /* enable or disable per user setting */ 2793 if (!(hw->dev_spec._82575.eee_disable)) { 2794 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); 2795 2796 if (adv100M) 2797 ipcnfg |= E1000_IPCNFG_EEE_100M_AN; 2798 else 2799 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN; 2800 2801 if (adv1G) 2802 ipcnfg |= E1000_IPCNFG_EEE_1G_AN; 2803 else 2804 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN; 2805 2806 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2807 E1000_EEER_LPI_FC); 2808 2809 /* This bit should not be set in normal operation. */ 2810 if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 2811 DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); 2812 } else { 2813 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2814 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2815 E1000_EEER_LPI_FC); 2816 } 2817 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 2818 E1000_WRITE_REG(hw, E1000_EEER, eeer); 2819 E1000_READ_REG(hw, E1000_IPCNFG); 2820 E1000_READ_REG(hw, E1000_EEER); 2821 out: 2822 2823 return E1000_SUCCESS; 2824 } 2825 2826 /** 2827 * e1000_set_eee_i354 - Enable/disable EEE support 2828 * @hw: pointer to the HW structure 2829 * @adv1G: boolean flag enabling 1G EEE advertisement 2830 * @adv100M: boolean flag enabling 100M EEE advertisement 2831 * 2832 * Enable/disable EEE legacy mode based on setting in dev_spec structure. 2833 * 2834 **/ 2835 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) 2836 { 2837 struct e1000_phy_info *phy = &hw->phy; 2838 s32 ret_val = E1000_SUCCESS; 2839 u16 phy_data; 2840 2841 DEBUGFUNC("e1000_set_eee_i354"); 2842 2843 if ((hw->phy.media_type != e1000_media_type_copper) || 2844 ((phy->id != M88E1543_E_PHY_ID) && 2845 (phy->id != M88E1512_E_PHY_ID))) 2846 goto out; 2847 2848 if (!hw->dev_spec._82575.eee_disable) { 2849 /* Switch to PHY page 18. */ 2850 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 2851 if (ret_val) 2852 goto out; 2853 2854 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2855 &phy_data); 2856 if (ret_val) 2857 goto out; 2858 2859 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 2860 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2861 phy_data); 2862 if (ret_val) 2863 goto out; 2864 2865 /* Return the PHY to page 0. */ 2866 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2867 if (ret_val) 2868 goto out; 2869 2870 /* Turn on EEE advertisement. */ 2871 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2872 E1000_EEE_ADV_DEV_I354, 2873 &phy_data); 2874 if (ret_val) 2875 goto out; 2876 2877 if (adv100M) 2878 phy_data |= E1000_EEE_ADV_100_SUPPORTED; 2879 else 2880 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED; 2881 2882 if (adv1G) 2883 phy_data |= E1000_EEE_ADV_1000_SUPPORTED; 2884 else 2885 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED; 2886 2887 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2888 E1000_EEE_ADV_DEV_I354, 2889 phy_data); 2890 } else { 2891 /* Turn off EEE advertisement. */ 2892 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2893 E1000_EEE_ADV_DEV_I354, 2894 &phy_data); 2895 if (ret_val) 2896 goto out; 2897 2898 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 2899 E1000_EEE_ADV_1000_SUPPORTED); 2900 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2901 E1000_EEE_ADV_DEV_I354, 2902 phy_data); 2903 } 2904 2905 out: 2906 return ret_val; 2907 } 2908 2909 /** 2910 * e1000_get_eee_status_i354 - Get EEE status 2911 * @hw: pointer to the HW structure 2912 * @status: EEE status 2913 * 2914 * Get EEE status by guessing based on whether Tx or Rx LPI indications have 2915 * been received. 2916 **/ 2917 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status) 2918 { 2919 struct e1000_phy_info *phy = &hw->phy; 2920 s32 ret_val = E1000_SUCCESS; 2921 u16 phy_data; 2922 2923 DEBUGFUNC("e1000_get_eee_status_i354"); 2924 2925 /* Check if EEE is supported on this device. */ 2926 if ((hw->phy.media_type != e1000_media_type_copper) || 2927 ((phy->id != M88E1543_E_PHY_ID) && 2928 (phy->id != M88E1512_E_PHY_ID))) 2929 goto out; 2930 2931 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 2932 E1000_PCS_STATUS_DEV_I354, 2933 &phy_data); 2934 if (ret_val) 2935 goto out; 2936 2937 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 2938 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false; 2939 2940 out: 2941 return ret_val; 2942 } 2943 2944 /* Due to a hw errata, if the host tries to configure the VFTA register 2945 * while performing queries from the BMC or DMA, then the VFTA in some 2946 * cases won't be written. 2947 */ 2948 2949 /** 2950 * e1000_clear_vfta_i350 - Clear VLAN filter table 2951 * @hw: pointer to the HW structure 2952 * 2953 * Clears the register array which contains the VLAN filter table by 2954 * setting all the values to 0. 2955 **/ 2956 void e1000_clear_vfta_i350(struct e1000_hw *hw) 2957 { 2958 u32 offset; 2959 int i; 2960 2961 DEBUGFUNC("e1000_clear_vfta_350"); 2962 2963 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 2964 for (i = 0; i < 10; i++) 2965 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 2966 2967 E1000_WRITE_FLUSH(hw); 2968 } 2969 } 2970 2971 /** 2972 * e1000_write_vfta_i350 - Write value to VLAN filter table 2973 * @hw: pointer to the HW structure 2974 * @offset: register offset in VLAN filter table 2975 * @value: register value written to VLAN filter table 2976 * 2977 * Writes value at the given offset in the register array which stores 2978 * the VLAN filter table. 2979 **/ 2980 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 2981 { 2982 int i; 2983 2984 DEBUGFUNC("e1000_write_vfta_350"); 2985 2986 for (i = 0; i < 10; i++) 2987 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 2988 2989 E1000_WRITE_FLUSH(hw); 2990 } 2991 2992 2993 /** 2994 * e1000_set_i2c_bb - Enable I2C bit-bang 2995 * @hw: pointer to the HW structure 2996 * 2997 * Enable I2C bit-bang interface 2998 * 2999 **/ 3000 s32 e1000_set_i2c_bb(struct e1000_hw *hw) 3001 { 3002 s32 ret_val = E1000_SUCCESS; 3003 u32 ctrl_ext, i2cparams; 3004 3005 DEBUGFUNC("e1000_set_i2c_bb"); 3006 3007 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3008 ctrl_ext |= E1000_CTRL_I2C_ENA; 3009 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3010 E1000_WRITE_FLUSH(hw); 3011 3012 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS); 3013 i2cparams |= E1000_I2CBB_EN; 3014 i2cparams |= E1000_I2C_DATA_OE_N; 3015 i2cparams |= E1000_I2C_CLK_OE_N; 3016 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams); 3017 E1000_WRITE_FLUSH(hw); 3018 3019 return ret_val; 3020 } 3021 3022 /** 3023 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C 3024 * @hw: pointer to hardware structure 3025 * @byte_offset: byte offset to read 3026 * @dev_addr: device address 3027 * @data: value read 3028 * 3029 * Performs byte read operation over I2C interface at 3030 * a specified device address. 3031 **/ 3032 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 3033 u8 dev_addr, u8 *data) 3034 { 3035 s32 status = E1000_SUCCESS; 3036 u32 max_retry = 10; 3037 u32 retry = 1; 3038 u16 swfw_mask = 0; 3039 3040 bool nack = true; 3041 3042 DEBUGFUNC("e1000_read_i2c_byte_generic"); 3043 3044 swfw_mask = E1000_SWFW_PHY0_SM; 3045 3046 do { 3047 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 3048 != E1000_SUCCESS) { 3049 status = E1000_ERR_SWFW_SYNC; 3050 goto read_byte_out; 3051 } 3052 3053 e1000_i2c_start(hw); 3054 3055 /* Device Address and write indication */ 3056 status = e1000_clock_out_i2c_byte(hw, dev_addr); 3057 if (status != E1000_SUCCESS) 3058 goto fail; 3059 3060 status = e1000_get_i2c_ack(hw); 3061 if (status != E1000_SUCCESS) 3062 goto fail; 3063 3064 status = e1000_clock_out_i2c_byte(hw, byte_offset); 3065 if (status != E1000_SUCCESS) 3066 goto fail; 3067 3068 status = e1000_get_i2c_ack(hw); 3069 if (status != E1000_SUCCESS) 3070 goto fail; 3071 3072 e1000_i2c_start(hw); 3073 3074 /* Device Address and read indication */ 3075 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 3076 if (status != E1000_SUCCESS) 3077 goto fail; 3078 3079 status = e1000_get_i2c_ack(hw); 3080 if (status != E1000_SUCCESS) 3081 goto fail; 3082 3083 e1000_clock_in_i2c_byte(hw, data); 3084 3085 status = e1000_clock_out_i2c_bit(hw, nack); 3086 if (status != E1000_SUCCESS) 3087 goto fail; 3088 3089 e1000_i2c_stop(hw); 3090 break; 3091 3092 fail: 3093 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3094 msec_delay(100); 3095 e1000_i2c_bus_clear(hw); 3096 retry++; 3097 if (retry < max_retry) 3098 DEBUGOUT("I2C byte read error - Retrying.\n"); 3099 else 3100 DEBUGOUT("I2C byte read error.\n"); 3101 3102 } while (retry < max_retry); 3103 3104 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3105 3106 read_byte_out: 3107 3108 return status; 3109 } 3110 3111 /** 3112 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C 3113 * @hw: pointer to hardware structure 3114 * @byte_offset: byte offset to write 3115 * @dev_addr: device address 3116 * @data: value to write 3117 * 3118 * Performs byte write operation over I2C interface at 3119 * a specified device address. 3120 **/ 3121 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 3122 u8 dev_addr, u8 data) 3123 { 3124 s32 status = E1000_SUCCESS; 3125 u32 max_retry = 1; 3126 u32 retry = 0; 3127 u16 swfw_mask = 0; 3128 3129 DEBUGFUNC("e1000_write_i2c_byte_generic"); 3130 3131 swfw_mask = E1000_SWFW_PHY0_SM; 3132 3133 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) { 3134 status = E1000_ERR_SWFW_SYNC; 3135 goto write_byte_out; 3136 } 3137 3138 do { 3139 e1000_i2c_start(hw); 3140 3141 status = e1000_clock_out_i2c_byte(hw, dev_addr); 3142 if (status != E1000_SUCCESS) 3143 goto fail; 3144 3145 status = e1000_get_i2c_ack(hw); 3146 if (status != E1000_SUCCESS) 3147 goto fail; 3148 3149 status = e1000_clock_out_i2c_byte(hw, byte_offset); 3150 if (status != E1000_SUCCESS) 3151 goto fail; 3152 3153 status = e1000_get_i2c_ack(hw); 3154 if (status != E1000_SUCCESS) 3155 goto fail; 3156 3157 status = e1000_clock_out_i2c_byte(hw, data); 3158 if (status != E1000_SUCCESS) 3159 goto fail; 3160 3161 status = e1000_get_i2c_ack(hw); 3162 if (status != E1000_SUCCESS) 3163 goto fail; 3164 3165 e1000_i2c_stop(hw); 3166 break; 3167 3168 fail: 3169 e1000_i2c_bus_clear(hw); 3170 retry++; 3171 if (retry < max_retry) 3172 DEBUGOUT("I2C byte write error - Retrying.\n"); 3173 else 3174 DEBUGOUT("I2C byte write error.\n"); 3175 } while (retry < max_retry); 3176 3177 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3178 3179 write_byte_out: 3180 3181 return status; 3182 } 3183 3184 /** 3185 * e1000_i2c_start - Sets I2C start condition 3186 * @hw: pointer to hardware structure 3187 * 3188 * Sets I2C start condition (High -> Low on SDA while SCL is High) 3189 **/ 3190 static void e1000_i2c_start(struct e1000_hw *hw) 3191 { 3192 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3193 3194 DEBUGFUNC("e1000_i2c_start"); 3195 3196 /* Start condition must begin with data and clock high */ 3197 e1000_set_i2c_data(hw, &i2cctl, 1); 3198 e1000_raise_i2c_clk(hw, &i2cctl); 3199 3200 /* Setup time for start condition (4.7us) */ 3201 usec_delay(E1000_I2C_T_SU_STA); 3202 3203 e1000_set_i2c_data(hw, &i2cctl, 0); 3204 3205 /* Hold time for start condition (4us) */ 3206 usec_delay(E1000_I2C_T_HD_STA); 3207 3208 e1000_lower_i2c_clk(hw, &i2cctl); 3209 3210 /* Minimum low period of clock is 4.7 us */ 3211 usec_delay(E1000_I2C_T_LOW); 3212 3213 } 3214 3215 /** 3216 * e1000_i2c_stop - Sets I2C stop condition 3217 * @hw: pointer to hardware structure 3218 * 3219 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 3220 **/ 3221 static void e1000_i2c_stop(struct e1000_hw *hw) 3222 { 3223 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3224 3225 DEBUGFUNC("e1000_i2c_stop"); 3226 3227 /* Stop condition must begin with data low and clock high */ 3228 e1000_set_i2c_data(hw, &i2cctl, 0); 3229 e1000_raise_i2c_clk(hw, &i2cctl); 3230 3231 /* Setup time for stop condition (4us) */ 3232 usec_delay(E1000_I2C_T_SU_STO); 3233 3234 e1000_set_i2c_data(hw, &i2cctl, 1); 3235 3236 /* bus free time between stop and start (4.7us)*/ 3237 usec_delay(E1000_I2C_T_BUF); 3238 } 3239 3240 /** 3241 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C 3242 * @hw: pointer to hardware structure 3243 * @data: data byte to clock in 3244 * 3245 * Clocks in one byte data via I2C data/clock 3246 **/ 3247 static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data) 3248 { 3249 s32 i; 3250 bool bit = 0; 3251 3252 DEBUGFUNC("e1000_clock_in_i2c_byte"); 3253 3254 *data = 0; 3255 for (i = 7; i >= 0; i--) { 3256 e1000_clock_in_i2c_bit(hw, &bit); 3257 *data |= bit << i; 3258 } 3259 } 3260 3261 /** 3262 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C 3263 * @hw: pointer to hardware structure 3264 * @data: data byte clocked out 3265 * 3266 * Clocks out one byte data via I2C data/clock 3267 **/ 3268 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data) 3269 { 3270 s32 status = E1000_SUCCESS; 3271 s32 i; 3272 u32 i2cctl; 3273 bool bit = 0; 3274 3275 DEBUGFUNC("e1000_clock_out_i2c_byte"); 3276 3277 for (i = 7; i >= 0; i--) { 3278 bit = (data >> i) & 0x1; 3279 status = e1000_clock_out_i2c_bit(hw, bit); 3280 3281 if (status != E1000_SUCCESS) 3282 break; 3283 } 3284 3285 /* Release SDA line (set high) */ 3286 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3287 3288 i2cctl |= E1000_I2C_DATA_OE_N; 3289 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl); 3290 E1000_WRITE_FLUSH(hw); 3291 3292 return status; 3293 } 3294 3295 /** 3296 * e1000_get_i2c_ack - Polls for I2C ACK 3297 * @hw: pointer to hardware structure 3298 * 3299 * Clocks in/out one bit via I2C data/clock 3300 **/ 3301 static s32 e1000_get_i2c_ack(struct e1000_hw *hw) 3302 { 3303 s32 status = E1000_SUCCESS; 3304 u32 i = 0; 3305 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3306 u32 timeout = 10; 3307 bool ack = true; 3308 3309 DEBUGFUNC("e1000_get_i2c_ack"); 3310 3311 e1000_raise_i2c_clk(hw, &i2cctl); 3312 3313 /* Minimum high period of clock is 4us */ 3314 usec_delay(E1000_I2C_T_HIGH); 3315 3316 /* Wait until SCL returns high */ 3317 for (i = 0; i < timeout; i++) { 3318 usec_delay(1); 3319 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3320 if (i2cctl & E1000_I2C_CLK_IN) 3321 break; 3322 } 3323 if (!(i2cctl & E1000_I2C_CLK_IN)) 3324 return E1000_ERR_I2C; 3325 3326 ack = e1000_get_i2c_data(&i2cctl); 3327 if (ack) { 3328 DEBUGOUT("I2C ack was not received.\n"); 3329 status = E1000_ERR_I2C; 3330 } 3331 3332 e1000_lower_i2c_clk(hw, &i2cctl); 3333 3334 /* Minimum low period of clock is 4.7 us */ 3335 usec_delay(E1000_I2C_T_LOW); 3336 3337 return status; 3338 } 3339 3340 /** 3341 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 3342 * @hw: pointer to hardware structure 3343 * @data: read data value 3344 * 3345 * Clocks in one bit via I2C data/clock 3346 **/ 3347 static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data) 3348 { 3349 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3350 3351 DEBUGFUNC("e1000_clock_in_i2c_bit"); 3352 3353 e1000_raise_i2c_clk(hw, &i2cctl); 3354 3355 /* Minimum high period of clock is 4us */ 3356 usec_delay(E1000_I2C_T_HIGH); 3357 3358 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3359 *data = e1000_get_i2c_data(&i2cctl); 3360 3361 e1000_lower_i2c_clk(hw, &i2cctl); 3362 3363 /* Minimum low period of clock is 4.7 us */ 3364 usec_delay(E1000_I2C_T_LOW); 3365 } 3366 3367 /** 3368 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 3369 * @hw: pointer to hardware structure 3370 * @data: data value to write 3371 * 3372 * Clocks out one bit via I2C data/clock 3373 **/ 3374 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data) 3375 { 3376 s32 status; 3377 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3378 3379 DEBUGFUNC("e1000_clock_out_i2c_bit"); 3380 3381 status = e1000_set_i2c_data(hw, &i2cctl, data); 3382 if (status == E1000_SUCCESS) { 3383 e1000_raise_i2c_clk(hw, &i2cctl); 3384 3385 /* Minimum high period of clock is 4us */ 3386 usec_delay(E1000_I2C_T_HIGH); 3387 3388 e1000_lower_i2c_clk(hw, &i2cctl); 3389 3390 /* Minimum low period of clock is 4.7 us. 3391 * This also takes care of the data hold time. 3392 */ 3393 usec_delay(E1000_I2C_T_LOW); 3394 } else { 3395 status = E1000_ERR_I2C; 3396 DEBUGOUT1("I2C data was not set to %X\n", data); 3397 } 3398 3399 return status; 3400 } 3401 /** 3402 * e1000_raise_i2c_clk - Raises the I2C SCL clock 3403 * @hw: pointer to hardware structure 3404 * @i2cctl: Current value of I2CCTL register 3405 * 3406 * Raises the I2C clock line '0'->'1' 3407 **/ 3408 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3409 { 3410 DEBUGFUNC("e1000_raise_i2c_clk"); 3411 3412 *i2cctl |= E1000_I2C_CLK_OUT; 3413 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3414 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3415 E1000_WRITE_FLUSH(hw); 3416 3417 /* SCL rise time (1000ns) */ 3418 usec_delay(E1000_I2C_T_RISE); 3419 } 3420 3421 /** 3422 * e1000_lower_i2c_clk - Lowers the I2C SCL clock 3423 * @hw: pointer to hardware structure 3424 * @i2cctl: Current value of I2CCTL register 3425 * 3426 * Lowers the I2C clock line '1'->'0' 3427 **/ 3428 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3429 { 3430 3431 DEBUGFUNC("e1000_lower_i2c_clk"); 3432 3433 *i2cctl &= ~E1000_I2C_CLK_OUT; 3434 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3435 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3436 E1000_WRITE_FLUSH(hw); 3437 3438 /* SCL fall time (300ns) */ 3439 usec_delay(E1000_I2C_T_FALL); 3440 } 3441 3442 /** 3443 * e1000_set_i2c_data - Sets the I2C data bit 3444 * @hw: pointer to hardware structure 3445 * @i2cctl: Current value of I2CCTL register 3446 * @data: I2C data value (0 or 1) to set 3447 * 3448 * Sets the I2C data bit 3449 **/ 3450 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data) 3451 { 3452 s32 status = E1000_SUCCESS; 3453 3454 DEBUGFUNC("e1000_set_i2c_data"); 3455 3456 if (data) 3457 *i2cctl |= E1000_I2C_DATA_OUT; 3458 else 3459 *i2cctl &= ~E1000_I2C_DATA_OUT; 3460 3461 *i2cctl &= ~E1000_I2C_DATA_OE_N; 3462 *i2cctl |= E1000_I2C_CLK_OE_N; 3463 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3464 E1000_WRITE_FLUSH(hw); 3465 3466 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 3467 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA); 3468 3469 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3470 if (data != e1000_get_i2c_data(i2cctl)) { 3471 status = E1000_ERR_I2C; 3472 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 3473 } 3474 3475 return status; 3476 } 3477 3478 /** 3479 * e1000_get_i2c_data - Reads the I2C SDA data bit 3480 * @i2cctl: Current value of I2CCTL register 3481 * 3482 * Returns the I2C data bit value 3483 **/ 3484 static bool e1000_get_i2c_data(u32 *i2cctl) 3485 { 3486 bool data; 3487 3488 DEBUGFUNC("e1000_get_i2c_data"); 3489 3490 if (*i2cctl & E1000_I2C_DATA_IN) 3491 data = 1; 3492 else 3493 data = 0; 3494 3495 return data; 3496 } 3497 3498 /** 3499 * e1000_i2c_bus_clear - Clears the I2C bus 3500 * @hw: pointer to hardware structure 3501 * 3502 * Clears the I2C bus by sending nine clock pulses. 3503 * Used when data line is stuck low. 3504 **/ 3505 void e1000_i2c_bus_clear(struct e1000_hw *hw) 3506 { 3507 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3508 u32 i; 3509 3510 DEBUGFUNC("e1000_i2c_bus_clear"); 3511 3512 e1000_i2c_start(hw); 3513 3514 e1000_set_i2c_data(hw, &i2cctl, 1); 3515 3516 for (i = 0; i < 9; i++) { 3517 e1000_raise_i2c_clk(hw, &i2cctl); 3518 3519 /* Min high period of clock is 4us */ 3520 usec_delay(E1000_I2C_T_HIGH); 3521 3522 e1000_lower_i2c_clk(hw, &i2cctl); 3523 3524 /* Min low period of clock is 4.7us*/ 3525 usec_delay(E1000_I2C_T_LOW); 3526 } 3527 3528 e1000_i2c_start(hw); 3529 3530 /* Put the i2c bus back to default state */ 3531 e1000_i2c_stop(hw); 3532 } 3533 3534