1 /****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82575EB Gigabit Network Connection 37 * 82575EB Gigabit Backplane Connection 38 * 82575GB Gigabit Network Connection 39 * 82576 Gigabit Network Connection 40 * 82576 Quad Port Gigabit Mezzanine Adapter 41 * 82580 Gigabit Network Connection 42 * I350 Gigabit Network Connection 43 */ 44 45 #include "e1000_api.h" 46 #include "e1000_i210.h" 47 48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 51 static void e1000_release_phy_82575(struct e1000_hw *hw); 52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 53 static void e1000_release_nvm_82575(struct e1000_hw *hw); 54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 55 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 56 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 57 u16 *duplex); 58 static s32 e1000_init_hw_82575(struct e1000_hw *hw); 59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 61 u16 *data); 62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw); 64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 65 u32 offset, u16 *data); 66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 67 u32 offset, u16 data); 68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, 69 bool active); 70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, 71 bool active); 72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 73 bool active); 74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw); 77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw); 78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 80 u32 offset, u16 data); 81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 84 u16 *speed, u16 *duplex); 85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw); 91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); 97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); 98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, 99 u16 offset); 100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 101 u16 offset); 102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); 103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); 104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value); 105 static void e1000_clear_vfta_i350(struct e1000_hw *hw); 106 107 static void e1000_i2c_start(struct e1000_hw *hw); 108 static void e1000_i2c_stop(struct e1000_hw *hw); 109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data); 110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data); 111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw); 112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data); 113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data); 114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data); 117 static bool e1000_get_i2c_data(u32 *i2cctl); 118 119 static const u16 e1000_82580_rxpbs_table[] = { 120 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 121 #define E1000_82580_RXPBS_TABLE_SIZE \ 122 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) 123 124 125 /** 126 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 127 * @hw: pointer to the HW structure 128 * 129 * Called to determine if the I2C pins are being used for I2C or as an 130 * external MDIO interface since the two options are mutually exclusive. 131 **/ 132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 133 { 134 u32 reg = 0; 135 bool ext_mdio = FALSE; 136 137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 138 139 switch (hw->mac.type) { 140 case e1000_82575: 141 case e1000_82576: 142 reg = E1000_READ_REG(hw, E1000_MDIC); 143 ext_mdio = !!(reg & E1000_MDIC_DEST); 144 break; 145 case e1000_82580: 146 case e1000_i350: 147 reg = E1000_READ_REG(hw, E1000_MDICNFG); 148 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 149 break; 150 default: 151 break; 152 } 153 return ext_mdio; 154 } 155 156 /** 157 * e1000_init_phy_params_82575 - Init PHY func ptrs. 158 * @hw: pointer to the HW structure 159 **/ 160 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 161 { 162 struct e1000_phy_info *phy = &hw->phy; 163 s32 ret_val = E1000_SUCCESS; 164 u32 ctrl_ext; 165 166 DEBUGFUNC("e1000_init_phy_params_82575"); 167 168 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; 169 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; 170 171 if (hw->phy.media_type != e1000_media_type_copper) { 172 phy->type = e1000_phy_none; 173 goto out; 174 } 175 176 phy->ops.power_up = e1000_power_up_phy_copper; 177 phy->ops.power_down = e1000_power_down_phy_copper_82575; 178 179 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 180 phy->reset_delay_us = 100; 181 182 phy->ops.acquire = e1000_acquire_phy_82575; 183 phy->ops.check_reset_block = e1000_check_reset_block_generic; 184 phy->ops.commit = e1000_phy_sw_reset_generic; 185 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 186 phy->ops.release = e1000_release_phy_82575; 187 188 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 189 190 if (e1000_sgmii_active_82575(hw)) { 191 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 192 ctrl_ext |= E1000_CTRL_I2C_ENA; 193 } else { 194 phy->ops.reset = e1000_phy_hw_reset_generic; 195 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 196 } 197 198 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 199 e1000_reset_mdicnfg_82580(hw); 200 201 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 202 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 203 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 204 } else { 205 switch (hw->mac.type) { 206 case e1000_82580: 207 case e1000_i350: 208 phy->ops.read_reg = e1000_read_phy_reg_82580; 209 phy->ops.write_reg = e1000_write_phy_reg_82580; 210 break; 211 case e1000_i210: 212 case e1000_i211: 213 phy->ops.read_reg = e1000_read_phy_reg_gs40g; 214 phy->ops.write_reg = e1000_write_phy_reg_gs40g; 215 break; 216 default: 217 phy->ops.read_reg = e1000_read_phy_reg_igp; 218 phy->ops.write_reg = e1000_write_phy_reg_igp; 219 } 220 } 221 222 /* Set phy->phy_addr and phy->id. */ 223 ret_val = e1000_get_phy_id_82575(hw); 224 225 /* Verify phy id and set remaining function pointers */ 226 switch (phy->id) { 227 case I347AT4_E_PHY_ID: 228 case M88E1112_E_PHY_ID: 229 case M88E1340M_E_PHY_ID: 230 case M88E1111_I_PHY_ID: 231 phy->type = e1000_phy_m88; 232 phy->ops.check_polarity = e1000_check_polarity_m88; 233 phy->ops.get_info = e1000_get_phy_info_m88; 234 if (phy->id == I347AT4_E_PHY_ID || 235 phy->id == M88E1112_E_PHY_ID || 236 phy->id == M88E1340M_E_PHY_ID) 237 phy->ops.get_cable_length = 238 e1000_get_cable_length_m88_gen2; 239 else 240 phy->ops.get_cable_length = e1000_get_cable_length_m88; 241 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 242 break; 243 case IGP03E1000_E_PHY_ID: 244 case IGP04E1000_E_PHY_ID: 245 phy->type = e1000_phy_igp_3; 246 phy->ops.check_polarity = e1000_check_polarity_igp; 247 phy->ops.get_info = e1000_get_phy_info_igp; 248 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 249 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 250 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 251 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 252 break; 253 case I82580_I_PHY_ID: 254 case I350_I_PHY_ID: 255 phy->type = e1000_phy_82580; 256 phy->ops.check_polarity = e1000_check_polarity_82577; 257 phy->ops.force_speed_duplex = 258 e1000_phy_force_speed_duplex_82577; 259 phy->ops.get_cable_length = e1000_get_cable_length_82577; 260 phy->ops.get_info = e1000_get_phy_info_82577; 261 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 262 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 263 break; 264 case I210_I_PHY_ID: 265 phy->type = e1000_phy_i210; 266 phy->ops.check_polarity = e1000_check_polarity_m88; 267 phy->ops.get_info = e1000_get_phy_info_m88; 268 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 269 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 270 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 271 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 272 break; 273 default: 274 ret_val = -E1000_ERR_PHY; 275 goto out; 276 } 277 278 out: 279 return ret_val; 280 } 281 282 /** 283 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 284 * @hw: pointer to the HW structure 285 **/ 286 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 287 { 288 struct e1000_nvm_info *nvm = &hw->nvm; 289 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 290 u16 size; 291 292 DEBUGFUNC("e1000_init_nvm_params_82575"); 293 294 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 295 E1000_EECD_SIZE_EX_SHIFT); 296 /* 297 * Added to a constant, "size" becomes the left-shift value 298 * for setting word_size. 299 */ 300 size += NVM_WORD_SIZE_BASE_SHIFT; 301 302 /* Just in case size is out of range, cap it to the largest 303 * EEPROM size supported 304 */ 305 if (size > 15) 306 size = 15; 307 308 nvm->word_size = 1 << size; 309 if (hw->mac.type < e1000_i210) { 310 nvm->opcode_bits = 8; 311 nvm->delay_usec = 1; 312 313 switch (nvm->override) { 314 case e1000_nvm_override_spi_large: 315 nvm->page_size = 32; 316 nvm->address_bits = 16; 317 break; 318 case e1000_nvm_override_spi_small: 319 nvm->page_size = 8; 320 nvm->address_bits = 8; 321 break; 322 default: 323 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 324 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 325 16 : 8; 326 break; 327 } 328 if (nvm->word_size == (1 << 15)) 329 nvm->page_size = 128; 330 331 nvm->type = e1000_nvm_eeprom_spi; 332 } else { 333 nvm->type = e1000_nvm_flash_hw; 334 } 335 /* Function Pointers */ 336 nvm->ops.acquire = e1000_acquire_nvm_82575; 337 nvm->ops.release = e1000_release_nvm_82575; 338 if (nvm->word_size < (1 << 15)) 339 nvm->ops.read = e1000_read_nvm_eerd; 340 else 341 nvm->ops.read = e1000_read_nvm_spi; 342 343 nvm->ops.write = e1000_write_nvm_spi; 344 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 345 nvm->ops.update = e1000_update_nvm_checksum_generic; 346 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 347 348 /* override generic family function pointers for specific descendants */ 349 switch (hw->mac.type) { 350 case e1000_82580: 351 nvm->ops.validate = e1000_validate_nvm_checksum_82580; 352 nvm->ops.update = e1000_update_nvm_checksum_82580; 353 break; 354 case e1000_i350: 355 nvm->ops.validate = e1000_validate_nvm_checksum_i350; 356 nvm->ops.update = e1000_update_nvm_checksum_i350; 357 break; 358 default: 359 break; 360 } 361 362 return E1000_SUCCESS; 363 } 364 365 /** 366 * e1000_init_mac_params_82575 - Init MAC func ptrs. 367 * @hw: pointer to the HW structure 368 **/ 369 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 370 { 371 struct e1000_mac_info *mac = &hw->mac; 372 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 373 374 DEBUGFUNC("e1000_init_mac_params_82575"); 375 376 /* Derives media type */ 377 e1000_get_media_type_82575(hw); 378 /* Set mta register count */ 379 mac->mta_reg_count = 128; 380 /* Set uta register count */ 381 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 382 /* Set rar entry count */ 383 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 384 if (mac->type == e1000_82576) 385 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 386 if (mac->type == e1000_82580) 387 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 388 if (mac->type == e1000_i350) { 389 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 390 /* Enable EEE default settings for i350 */ 391 dev_spec->eee_disable = FALSE; 392 } 393 394 /* Set if part includes ASF firmware */ 395 mac->asf_firmware_present = TRUE; 396 /* FWSM register */ 397 mac->has_fwsm = TRUE; 398 /* ARC supported; valid only if manageability features are enabled. */ 399 mac->arc_subsystem_valid = 400 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK); 401 402 /* Function pointers */ 403 404 /* bus type/speed/width */ 405 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 406 /* reset */ 407 if (mac->type >= e1000_82580) 408 mac->ops.reset_hw = e1000_reset_hw_82580; 409 else 410 mac->ops.reset_hw = e1000_reset_hw_82575; 411 /* hw initialization */ 412 mac->ops.init_hw = e1000_init_hw_82575; 413 /* link setup */ 414 mac->ops.setup_link = e1000_setup_link_generic; 415 /* physical interface link setup */ 416 mac->ops.setup_physical_interface = 417 (hw->phy.media_type == e1000_media_type_copper) 418 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575; 419 /* physical interface shutdown */ 420 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 421 /* physical interface power up */ 422 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 423 /* check for link */ 424 mac->ops.check_for_link = e1000_check_for_link_82575; 425 /* read mac address */ 426 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 427 /* configure collision distance */ 428 mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 429 /* multicast address update */ 430 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 431 if (hw->mac.type == e1000_i350) { 432 /* writing VFTA */ 433 mac->ops.write_vfta = e1000_write_vfta_i350; 434 /* clearing VFTA */ 435 mac->ops.clear_vfta = e1000_clear_vfta_i350; 436 } else { 437 /* writing VFTA */ 438 mac->ops.write_vfta = e1000_write_vfta_generic; 439 /* clearing VFTA */ 440 mac->ops.clear_vfta = e1000_clear_vfta_generic; 441 } 442 /* ID LED init */ 443 mac->ops.id_led_init = e1000_id_led_init_generic; 444 /* blink LED */ 445 mac->ops.blink_led = e1000_blink_led_generic; 446 /* setup LED */ 447 mac->ops.setup_led = e1000_setup_led_generic; 448 /* cleanup LED */ 449 mac->ops.cleanup_led = e1000_cleanup_led_generic; 450 /* turn on/off LED */ 451 mac->ops.led_on = e1000_led_on_generic; 452 mac->ops.led_off = e1000_led_off_generic; 453 /* clear hardware counters */ 454 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 455 /* link info */ 456 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 457 /* acquire SW_FW sync */ 458 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575; 459 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575; 460 if (mac->type >= e1000_i210) { 461 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210; 462 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210; 463 } 464 465 /* set lan id for port to determine which phy lock to use */ 466 hw->mac.ops.set_lan_id(hw); 467 468 return E1000_SUCCESS; 469 } 470 471 /** 472 * e1000_init_function_pointers_82575 - Init func ptrs. 473 * @hw: pointer to the HW structure 474 * 475 * Called to initialize all function pointers and parameters. 476 **/ 477 void e1000_init_function_pointers_82575(struct e1000_hw *hw) 478 { 479 DEBUGFUNC("e1000_init_function_pointers_82575"); 480 481 hw->mac.ops.init_params = e1000_init_mac_params_82575; 482 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 483 hw->phy.ops.init_params = e1000_init_phy_params_82575; 484 hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 485 } 486 487 /** 488 * e1000_acquire_phy_82575 - Acquire rights to access PHY 489 * @hw: pointer to the HW structure 490 * 491 * Acquire access rights to the correct PHY. 492 **/ 493 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 494 { 495 u16 mask = E1000_SWFW_PHY0_SM; 496 497 DEBUGFUNC("e1000_acquire_phy_82575"); 498 499 if (hw->bus.func == E1000_FUNC_1) 500 mask = E1000_SWFW_PHY1_SM; 501 else if (hw->bus.func == E1000_FUNC_2) 502 mask = E1000_SWFW_PHY2_SM; 503 else if (hw->bus.func == E1000_FUNC_3) 504 mask = E1000_SWFW_PHY3_SM; 505 506 return hw->mac.ops.acquire_swfw_sync(hw, mask); 507 } 508 509 /** 510 * e1000_release_phy_82575 - Release rights to access PHY 511 * @hw: pointer to the HW structure 512 * 513 * A wrapper to release access rights to the correct PHY. 514 **/ 515 static void e1000_release_phy_82575(struct e1000_hw *hw) 516 { 517 u16 mask = E1000_SWFW_PHY0_SM; 518 519 DEBUGFUNC("e1000_release_phy_82575"); 520 521 if (hw->bus.func == E1000_FUNC_1) 522 mask = E1000_SWFW_PHY1_SM; 523 else if (hw->bus.func == E1000_FUNC_2) 524 mask = E1000_SWFW_PHY2_SM; 525 else if (hw->bus.func == E1000_FUNC_3) 526 mask = E1000_SWFW_PHY3_SM; 527 528 hw->mac.ops.release_swfw_sync(hw, mask); 529 } 530 531 /** 532 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 533 * @hw: pointer to the HW structure 534 * @offset: register offset to be read 535 * @data: pointer to the read data 536 * 537 * Reads the PHY register at offset using the serial gigabit media independent 538 * interface and stores the retrieved information in data. 539 **/ 540 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 541 u16 *data) 542 { 543 s32 ret_val = -E1000_ERR_PARAM; 544 545 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 546 547 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 548 DEBUGOUT1("PHY Address %u is out of range\n", offset); 549 goto out; 550 } 551 552 ret_val = hw->phy.ops.acquire(hw); 553 if (ret_val) 554 goto out; 555 556 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 557 558 hw->phy.ops.release(hw); 559 560 out: 561 return ret_val; 562 } 563 564 /** 565 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 566 * @hw: pointer to the HW structure 567 * @offset: register offset to write to 568 * @data: data to write at register offset 569 * 570 * Writes the data to PHY register at the offset using the serial gigabit 571 * media independent interface. 572 **/ 573 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 574 u16 data) 575 { 576 s32 ret_val = -E1000_ERR_PARAM; 577 578 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 579 580 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 581 DEBUGOUT1("PHY Address %d is out of range\n", offset); 582 goto out; 583 } 584 585 ret_val = hw->phy.ops.acquire(hw); 586 if (ret_val) 587 goto out; 588 589 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 590 591 hw->phy.ops.release(hw); 592 593 out: 594 return ret_val; 595 } 596 597 /** 598 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 599 * @hw: pointer to the HW structure 600 * 601 * Retrieves the PHY address and ID for both PHY's which do and do not use 602 * sgmi interface. 603 **/ 604 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 605 { 606 struct e1000_phy_info *phy = &hw->phy; 607 s32 ret_val = E1000_SUCCESS; 608 u16 phy_id; 609 u32 ctrl_ext; 610 u32 mdic; 611 612 DEBUGFUNC("e1000_get_phy_id_82575"); 613 614 /* 615 * For SGMII PHYs, we try the list of possible addresses until 616 * we find one that works. For non-SGMII PHYs 617 * (e.g. integrated copper PHYs), an address of 1 should 618 * work. The result of this function should mean phy->phy_addr 619 * and phy->id are set correctly. 620 */ 621 if (!e1000_sgmii_active_82575(hw)) { 622 phy->addr = 1; 623 ret_val = e1000_get_phy_id(hw); 624 goto out; 625 } 626 627 if (e1000_sgmii_uses_mdio_82575(hw)) { 628 switch (hw->mac.type) { 629 case e1000_82575: 630 case e1000_82576: 631 mdic = E1000_READ_REG(hw, E1000_MDIC); 632 mdic &= E1000_MDIC_PHY_MASK; 633 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 634 break; 635 case e1000_82580: 636 case e1000_i350: 637 mdic = E1000_READ_REG(hw, E1000_MDICNFG); 638 mdic &= E1000_MDICNFG_PHY_MASK; 639 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 640 break; 641 default: 642 ret_val = -E1000_ERR_PHY; 643 goto out; 644 break; 645 } 646 ret_val = e1000_get_phy_id(hw); 647 goto out; 648 } 649 650 /* Power on sgmii phy if it is disabled */ 651 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 652 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 653 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 654 E1000_WRITE_FLUSH(hw); 655 msec_delay(300); 656 657 /* 658 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 659 * Therefore, we need to test 1-7 660 */ 661 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 662 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 663 if (ret_val == E1000_SUCCESS) { 664 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 665 phy_id, phy->addr); 666 /* 667 * At the time of this writing, The M88 part is 668 * the only supported SGMII PHY product. 669 */ 670 if (phy_id == M88_VENDOR) 671 break; 672 } else { 673 DEBUGOUT1("PHY address %u was unreadable\n", 674 phy->addr); 675 } 676 } 677 678 /* A valid PHY type couldn't be found. */ 679 if (phy->addr == 8) { 680 phy->addr = 0; 681 ret_val = -E1000_ERR_PHY; 682 } else { 683 ret_val = e1000_get_phy_id(hw); 684 } 685 686 /* restore previous sfp cage power state */ 687 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 688 689 out: 690 return ret_val; 691 } 692 693 /** 694 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 695 * @hw: pointer to the HW structure 696 * 697 * Resets the PHY using the serial gigabit media independent interface. 698 **/ 699 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 700 { 701 s32 ret_val = E1000_SUCCESS; 702 703 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 704 705 /* 706 * This isn't a TRUE "hard" reset, but is the only reset 707 * available to us at this time. 708 */ 709 710 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 711 712 if (!(hw->phy.ops.write_reg)) 713 goto out; 714 715 /* 716 * SFP documentation requires the following to configure the SPF module 717 * to work on SGMII. No further documentation is given. 718 */ 719 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 720 if (ret_val) 721 goto out; 722 723 ret_val = hw->phy.ops.commit(hw); 724 725 out: 726 return ret_val; 727 } 728 729 /** 730 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 731 * @hw: pointer to the HW structure 732 * @active: TRUE to enable LPLU, FALSE to disable 733 * 734 * Sets the LPLU D0 state according to the active flag. When 735 * activating LPLU this function also disables smart speed 736 * and vice versa. LPLU will not be activated unless the 737 * device autonegotiation advertisement meets standards of 738 * either 10 or 10/100 or 10/100/1000 at all duplexes. 739 * This is a function pointer entry point only called by 740 * PHY setup routines. 741 **/ 742 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 743 { 744 struct e1000_phy_info *phy = &hw->phy; 745 s32 ret_val = E1000_SUCCESS; 746 u16 data; 747 748 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 749 750 if (!(hw->phy.ops.read_reg)) 751 goto out; 752 753 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 754 if (ret_val) 755 goto out; 756 757 if (active) { 758 data |= IGP02E1000_PM_D0_LPLU; 759 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 760 data); 761 if (ret_val) 762 goto out; 763 764 /* When LPLU is enabled, we should disable SmartSpeed */ 765 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 766 &data); 767 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 768 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 769 data); 770 if (ret_val) 771 goto out; 772 } else { 773 data &= ~IGP02E1000_PM_D0_LPLU; 774 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 775 data); 776 /* 777 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 778 * during Dx states where the power conservation is most 779 * important. During driver activity we should enable 780 * SmartSpeed, so performance is maintained. 781 */ 782 if (phy->smart_speed == e1000_smart_speed_on) { 783 ret_val = phy->ops.read_reg(hw, 784 IGP01E1000_PHY_PORT_CONFIG, 785 &data); 786 if (ret_val) 787 goto out; 788 789 data |= IGP01E1000_PSCFR_SMART_SPEED; 790 ret_val = phy->ops.write_reg(hw, 791 IGP01E1000_PHY_PORT_CONFIG, 792 data); 793 if (ret_val) 794 goto out; 795 } else if (phy->smart_speed == e1000_smart_speed_off) { 796 ret_val = phy->ops.read_reg(hw, 797 IGP01E1000_PHY_PORT_CONFIG, 798 &data); 799 if (ret_val) 800 goto out; 801 802 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 803 ret_val = phy->ops.write_reg(hw, 804 IGP01E1000_PHY_PORT_CONFIG, 805 data); 806 if (ret_val) 807 goto out; 808 } 809 } 810 811 out: 812 return ret_val; 813 } 814 815 /** 816 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 817 * @hw: pointer to the HW structure 818 * @active: TRUE to enable LPLU, FALSE to disable 819 * 820 * Sets the LPLU D0 state according to the active flag. When 821 * activating LPLU this function also disables smart speed 822 * and vice versa. LPLU will not be activated unless the 823 * device autonegotiation advertisement meets standards of 824 * either 10 or 10/100 or 10/100/1000 at all duplexes. 825 * This is a function pointer entry point only called by 826 * PHY setup routines. 827 **/ 828 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 829 { 830 struct e1000_phy_info *phy = &hw->phy; 831 s32 ret_val = E1000_SUCCESS; 832 u32 data; 833 834 DEBUGFUNC("e1000_set_d0_lplu_state_82580"); 835 836 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 837 838 if (active) { 839 data |= E1000_82580_PM_D0_LPLU; 840 841 /* When LPLU is enabled, we should disable SmartSpeed */ 842 data &= ~E1000_82580_PM_SPD; 843 } else { 844 data &= ~E1000_82580_PM_D0_LPLU; 845 846 /* 847 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 848 * during Dx states where the power conservation is most 849 * important. During driver activity we should enable 850 * SmartSpeed, so performance is maintained. 851 */ 852 if (phy->smart_speed == e1000_smart_speed_on) 853 data |= E1000_82580_PM_SPD; 854 else if (phy->smart_speed == e1000_smart_speed_off) 855 data &= ~E1000_82580_PM_SPD; 856 } 857 858 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 859 return ret_val; 860 } 861 862 /** 863 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 864 * @hw: pointer to the HW structure 865 * @active: boolean used to enable/disable lplu 866 * 867 * Success returns 0, Failure returns 1 868 * 869 * The low power link up (lplu) state is set to the power management level D3 870 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 871 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 872 * is used during Dx states where the power conservation is most important. 873 * During driver activity, SmartSpeed should be enabled so performance is 874 * maintained. 875 **/ 876 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 877 { 878 struct e1000_phy_info *phy = &hw->phy; 879 s32 ret_val = E1000_SUCCESS; 880 u32 data; 881 882 DEBUGFUNC("e1000_set_d3_lplu_state_82580"); 883 884 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 885 886 if (!active) { 887 data &= ~E1000_82580_PM_D3_LPLU; 888 /* 889 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 890 * during Dx states where the power conservation is most 891 * important. During driver activity we should enable 892 * SmartSpeed, so performance is maintained. 893 */ 894 if (phy->smart_speed == e1000_smart_speed_on) 895 data |= E1000_82580_PM_SPD; 896 else if (phy->smart_speed == e1000_smart_speed_off) 897 data &= ~E1000_82580_PM_SPD; 898 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 899 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 900 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 901 data |= E1000_82580_PM_D3_LPLU; 902 /* When LPLU is enabled, we should disable SmartSpeed */ 903 data &= ~E1000_82580_PM_SPD; 904 } 905 906 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 907 return ret_val; 908 } 909 910 /** 911 * e1000_acquire_nvm_82575 - Request for access to EEPROM 912 * @hw: pointer to the HW structure 913 * 914 * Acquire the necessary semaphores for exclusive access to the EEPROM. 915 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 916 * Return successful if access grant bit set, else clear the request for 917 * EEPROM access and return -E1000_ERR_NVM (-1). 918 **/ 919 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 920 { 921 s32 ret_val; 922 923 DEBUGFUNC("e1000_acquire_nvm_82575"); 924 925 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 926 if (ret_val) 927 goto out; 928 929 /* 930 * Check if there is some access 931 * error this access may hook on 932 */ 933 if (hw->mac.type == e1000_i350) { 934 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 935 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT | 936 E1000_EECD_TIMEOUT)) { 937 /* Clear all access error flags */ 938 E1000_WRITE_REG(hw, E1000_EECD, eecd | 939 E1000_EECD_ERROR_CLR); 940 DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 941 } 942 } 943 if (hw->mac.type == e1000_82580) { 944 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 945 if (eecd & E1000_EECD_BLOCKED) { 946 /* Clear access error flag */ 947 E1000_WRITE_REG(hw, E1000_EECD, eecd | 948 E1000_EECD_BLOCKED); 949 DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 950 } 951 } 952 953 954 ret_val = e1000_acquire_nvm_generic(hw); 955 if (ret_val) 956 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 957 958 out: 959 return ret_val; 960 } 961 962 /** 963 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 964 * @hw: pointer to the HW structure 965 * 966 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 967 * then release the semaphores acquired. 968 **/ 969 static void e1000_release_nvm_82575(struct e1000_hw *hw) 970 { 971 DEBUGFUNC("e1000_release_nvm_82575"); 972 973 e1000_release_nvm_generic(hw); 974 975 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 976 } 977 978 /** 979 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 980 * @hw: pointer to the HW structure 981 * @mask: specifies which semaphore to acquire 982 * 983 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 984 * will also specify which port we're acquiring the lock for. 985 **/ 986 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 987 { 988 u32 swfw_sync; 989 u32 swmask = mask; 990 u32 fwmask = mask << 16; 991 s32 ret_val = E1000_SUCCESS; 992 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 993 994 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 995 996 while (i < timeout) { 997 if (e1000_get_hw_semaphore_generic(hw)) { 998 ret_val = -E1000_ERR_SWFW_SYNC; 999 goto out; 1000 } 1001 1002 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1003 if (!(swfw_sync & (fwmask | swmask))) 1004 break; 1005 1006 /* 1007 * Firmware currently using resource (fwmask) 1008 * or other software thread using resource (swmask) 1009 */ 1010 e1000_put_hw_semaphore_generic(hw); 1011 msec_delay_irq(5); 1012 i++; 1013 } 1014 1015 if (i == timeout) { 1016 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1017 ret_val = -E1000_ERR_SWFW_SYNC; 1018 goto out; 1019 } 1020 1021 swfw_sync |= swmask; 1022 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1023 1024 e1000_put_hw_semaphore_generic(hw); 1025 1026 out: 1027 return ret_val; 1028 } 1029 1030 /** 1031 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 1032 * @hw: pointer to the HW structure 1033 * @mask: specifies which semaphore to acquire 1034 * 1035 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1036 * will also specify which port we're releasing the lock for. 1037 **/ 1038 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1039 { 1040 u32 swfw_sync; 1041 1042 DEBUGFUNC("e1000_release_swfw_sync_82575"); 1043 1044 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 1045 ; /* Empty */ 1046 1047 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1048 swfw_sync &= ~mask; 1049 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1050 1051 e1000_put_hw_semaphore_generic(hw); 1052 } 1053 1054 /** 1055 * e1000_get_cfg_done_82575 - Read config done bit 1056 * @hw: pointer to the HW structure 1057 * 1058 * Read the management control register for the config done bit for 1059 * completion status. NOTE: silicon which is EEPROM-less will fail trying 1060 * to read the config done bit, so an error is *ONLY* logged and returns 1061 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 1062 * would not be able to be reset or change link. 1063 **/ 1064 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 1065 { 1066 s32 timeout = PHY_CFG_TIMEOUT; 1067 s32 ret_val = E1000_SUCCESS; 1068 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1069 1070 DEBUGFUNC("e1000_get_cfg_done_82575"); 1071 1072 if (hw->bus.func == E1000_FUNC_1) 1073 mask = E1000_NVM_CFG_DONE_PORT_1; 1074 else if (hw->bus.func == E1000_FUNC_2) 1075 mask = E1000_NVM_CFG_DONE_PORT_2; 1076 else if (hw->bus.func == E1000_FUNC_3) 1077 mask = E1000_NVM_CFG_DONE_PORT_3; 1078 while (timeout) { 1079 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 1080 break; 1081 msec_delay(1); 1082 timeout--; 1083 } 1084 if (!timeout) 1085 DEBUGOUT("MNG configuration cycle has not completed.\n"); 1086 1087 /* If EEPROM is not marked present, init the PHY manually */ 1088 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 1089 (hw->phy.type == e1000_phy_igp_3)) 1090 e1000_phy_init_script_igp3(hw); 1091 1092 return ret_val; 1093 } 1094 1095 /** 1096 * e1000_get_link_up_info_82575 - Get link speed/duplex info 1097 * @hw: pointer to the HW structure 1098 * @speed: stores the current speed 1099 * @duplex: stores the current duplex 1100 * 1101 * This is a wrapper function, if using the serial gigabit media independent 1102 * interface, use PCS to retrieve the link speed and duplex information. 1103 * Otherwise, use the generic function to get the link speed and duplex info. 1104 **/ 1105 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1106 u16 *duplex) 1107 { 1108 s32 ret_val; 1109 1110 DEBUGFUNC("e1000_get_link_up_info_82575"); 1111 1112 if (hw->phy.media_type != e1000_media_type_copper) 1113 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 1114 duplex); 1115 else 1116 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 1117 duplex); 1118 1119 return ret_val; 1120 } 1121 1122 /** 1123 * e1000_check_for_link_82575 - Check for link 1124 * @hw: pointer to the HW structure 1125 * 1126 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1127 * use the generic interface for determining link. 1128 **/ 1129 static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 1130 { 1131 s32 ret_val; 1132 u16 speed, duplex; 1133 1134 DEBUGFUNC("e1000_check_for_link_82575"); 1135 1136 if (hw->phy.media_type != e1000_media_type_copper) { 1137 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 1138 &duplex); 1139 /* 1140 * Use this flag to determine if link needs to be checked or 1141 * not. If we have link clear the flag so that we do not 1142 * continue to check for link. 1143 */ 1144 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1145 1146 } else { 1147 ret_val = e1000_check_for_copper_link_generic(hw); 1148 } 1149 1150 return ret_val; 1151 } 1152 1153 /** 1154 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1155 * @hw: pointer to the HW structure 1156 **/ 1157 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 1158 { 1159 u32 reg; 1160 1161 DEBUGFUNC("e1000_power_up_serdes_link_82575"); 1162 1163 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1164 !e1000_sgmii_active_82575(hw)) 1165 return; 1166 1167 /* Enable PCS to turn on link */ 1168 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1169 reg |= E1000_PCS_CFG_PCS_EN; 1170 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1171 1172 /* Power up the laser */ 1173 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1174 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1175 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1176 1177 /* flush the write to verify completion */ 1178 E1000_WRITE_FLUSH(hw); 1179 msec_delay(1); 1180 } 1181 1182 /** 1183 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1184 * @hw: pointer to the HW structure 1185 * @speed: stores the current speed 1186 * @duplex: stores the current duplex 1187 * 1188 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1189 * duplex, then store the values in the pointers provided. 1190 **/ 1191 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 1192 u16 *speed, u16 *duplex) 1193 { 1194 struct e1000_mac_info *mac = &hw->mac; 1195 u32 pcs; 1196 1197 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 1198 1199 /* 1200 * Read the PCS Status register for link state. For non-copper mode, 1201 * the status register is not accurate. The PCS status register is 1202 * used instead. 1203 */ 1204 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1205 1206 /* 1207 * The link up bit determines when link is up on autoneg. 1208 */ 1209 if (pcs & E1000_PCS_LSTS_LINK_OK) { 1210 mac->serdes_has_link = TRUE; 1211 1212 /* Detect and store PCS speed */ 1213 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1214 *speed = SPEED_1000; 1215 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1216 *speed = SPEED_100; 1217 else 1218 *speed = SPEED_10; 1219 1220 /* Detect and store PCS duplex */ 1221 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1222 *duplex = FULL_DUPLEX; 1223 else 1224 *duplex = HALF_DUPLEX; 1225 } else { 1226 mac->serdes_has_link = FALSE; 1227 *speed = 0; 1228 *duplex = 0; 1229 } 1230 1231 return E1000_SUCCESS; 1232 } 1233 1234 /** 1235 * e1000_shutdown_serdes_link_82575 - Remove link during power down 1236 * @hw: pointer to the HW structure 1237 * 1238 * In the case of serdes shut down sfp and PCS on driver unload 1239 * when management pass thru is not enabled. 1240 **/ 1241 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1242 { 1243 u32 reg; 1244 1245 DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1246 1247 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1248 !e1000_sgmii_active_82575(hw)) 1249 return; 1250 1251 if (!e1000_enable_mng_pass_thru(hw)) { 1252 /* Disable PCS to turn off link */ 1253 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1254 reg &= ~E1000_PCS_CFG_PCS_EN; 1255 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1256 1257 /* shutdown the laser */ 1258 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1259 reg |= E1000_CTRL_EXT_SDP3_DATA; 1260 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1261 1262 /* flush the write to verify completion */ 1263 E1000_WRITE_FLUSH(hw); 1264 msec_delay(1); 1265 } 1266 1267 return; 1268 } 1269 1270 /** 1271 * e1000_reset_hw_82575 - Reset hardware 1272 * @hw: pointer to the HW structure 1273 * 1274 * This resets the hardware into a known state. 1275 **/ 1276 static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1277 { 1278 u32 ctrl; 1279 s32 ret_val; 1280 1281 DEBUGFUNC("e1000_reset_hw_82575"); 1282 1283 /* 1284 * Prevent the PCI-E bus from sticking if there is no TLP connection 1285 * on the last TLP read/write transaction when MAC is reset. 1286 */ 1287 ret_val = e1000_disable_pcie_master_generic(hw); 1288 if (ret_val) 1289 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1290 1291 /* set the completion timeout for interface */ 1292 ret_val = e1000_set_pcie_completion_timeout(hw); 1293 if (ret_val) 1294 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1295 1296 DEBUGOUT("Masking off all interrupts\n"); 1297 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1298 1299 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1300 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1301 E1000_WRITE_FLUSH(hw); 1302 1303 msec_delay(10); 1304 1305 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1306 1307 DEBUGOUT("Issuing a global reset to MAC\n"); 1308 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1309 1310 ret_val = e1000_get_auto_rd_done_generic(hw); 1311 if (ret_val) { 1312 /* 1313 * When auto config read does not complete, do not 1314 * return with an error. This can happen in situations 1315 * where there is no eeprom and prevents getting link. 1316 */ 1317 DEBUGOUT("Auto Read Done did not complete\n"); 1318 } 1319 1320 /* If EEPROM is not present, run manual init scripts */ 1321 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 1322 e1000_reset_init_script_82575(hw); 1323 1324 /* Clear any pending interrupt events. */ 1325 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1326 E1000_READ_REG(hw, E1000_ICR); 1327 1328 /* Install any alternate MAC address into RAR0 */ 1329 ret_val = e1000_check_alt_mac_addr_generic(hw); 1330 1331 return ret_val; 1332 } 1333 1334 /** 1335 * e1000_init_hw_82575 - Initialize hardware 1336 * @hw: pointer to the HW structure 1337 * 1338 * This inits the hardware readying it for operation. 1339 **/ 1340 static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1341 { 1342 struct e1000_mac_info *mac = &hw->mac; 1343 s32 ret_val; 1344 u16 i, rar_count = mac->rar_entry_count; 1345 1346 DEBUGFUNC("e1000_init_hw_82575"); 1347 1348 /* Initialize identification LED */ 1349 ret_val = mac->ops.id_led_init(hw); 1350 if (ret_val) { 1351 DEBUGOUT("Error initializing identification LED\n"); 1352 /* This is not fatal and we should not stop init due to this */ 1353 } 1354 1355 /* Disabling VLAN filtering */ 1356 DEBUGOUT("Initializing the IEEE VLAN\n"); 1357 mac->ops.clear_vfta(hw); 1358 1359 /* Setup the receive address */ 1360 e1000_init_rx_addrs_generic(hw, rar_count); 1361 1362 /* Zero out the Multicast HASH table */ 1363 DEBUGOUT("Zeroing the MTA\n"); 1364 for (i = 0; i < mac->mta_reg_count; i++) 1365 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1366 1367 /* Zero out the Unicast HASH table */ 1368 DEBUGOUT("Zeroing the UTA\n"); 1369 for (i = 0; i < mac->uta_reg_count; i++) 1370 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1371 1372 /* Setup link and flow control */ 1373 ret_val = mac->ops.setup_link(hw); 1374 1375 /* Set the default MTU size */ 1376 hw->dev_spec._82575.mtu = 1500; 1377 1378 /* 1379 * Clear all of the statistics registers (clear on read). It is 1380 * important that we do this after we have tried to establish link 1381 * because the symbol error count will increment wildly if there 1382 * is no link. 1383 */ 1384 e1000_clear_hw_cntrs_82575(hw); 1385 1386 return ret_val; 1387 } 1388 1389 /** 1390 * e1000_setup_copper_link_82575 - Configure copper link settings 1391 * @hw: pointer to the HW structure 1392 * 1393 * Configures the link for auto-neg or forced speed and duplex. Then we check 1394 * for link, once link is established calls to configure collision distance 1395 * and flow control are called. 1396 **/ 1397 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1398 { 1399 u32 ctrl; 1400 s32 ret_val; 1401 1402 DEBUGFUNC("e1000_setup_copper_link_82575"); 1403 1404 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1405 ctrl |= E1000_CTRL_SLU; 1406 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1407 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1408 1409 ret_val = e1000_setup_serdes_link_82575(hw); 1410 if (ret_val) 1411 goto out; 1412 1413 if (e1000_sgmii_active_82575(hw)) { 1414 /* allow time for SFP cage time to power up phy */ 1415 msec_delay(300); 1416 1417 ret_val = hw->phy.ops.reset(hw); 1418 if (ret_val) { 1419 DEBUGOUT("Error resetting the PHY.\n"); 1420 goto out; 1421 } 1422 } 1423 switch (hw->phy.type) { 1424 case e1000_phy_i210: 1425 case e1000_phy_m88: 1426 if (hw->phy.id == I347AT4_E_PHY_ID || 1427 hw->phy.id == M88E1112_E_PHY_ID || 1428 hw->phy.id == M88E1340M_E_PHY_ID) 1429 ret_val = e1000_copper_link_setup_m88_gen2(hw); 1430 else 1431 ret_val = e1000_copper_link_setup_m88(hw); 1432 break; 1433 case e1000_phy_igp_3: 1434 ret_val = e1000_copper_link_setup_igp(hw); 1435 break; 1436 case e1000_phy_82580: 1437 ret_val = e1000_copper_link_setup_82577(hw); 1438 break; 1439 default: 1440 ret_val = -E1000_ERR_PHY; 1441 break; 1442 } 1443 1444 if (ret_val) 1445 goto out; 1446 1447 ret_val = e1000_setup_copper_link_generic(hw); 1448 out: 1449 return ret_val; 1450 } 1451 1452 /** 1453 * e1000_setup_serdes_link_82575 - Setup link for serdes 1454 * @hw: pointer to the HW structure 1455 * 1456 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1457 * used on copper connections where the serialized gigabit media independent 1458 * interface (sgmii), or serdes fiber is being used. Configures the link 1459 * for auto-negotiation or forces speed/duplex. 1460 **/ 1461 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1462 { 1463 u32 ctrl_ext, ctrl_reg, reg; 1464 bool pcs_autoneg; 1465 s32 ret_val = E1000_SUCCESS; 1466 u16 data; 1467 1468 DEBUGFUNC("e1000_setup_serdes_link_82575"); 1469 1470 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1471 !e1000_sgmii_active_82575(hw)) 1472 return ret_val; 1473 1474 /* 1475 * On the 82575, SerDes loopback mode persists until it is 1476 * explicitly turned off or a power cycle is performed. A read to 1477 * the register does not indicate its status. Therefore, we ensure 1478 * loopback mode is disabled during initialization. 1479 */ 1480 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1481 1482 /* power on the sfp cage if present */ 1483 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1484 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1485 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1486 1487 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1488 ctrl_reg |= E1000_CTRL_SLU; 1489 1490 /* set both sw defined pins on 82575/82576*/ 1491 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1492 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1493 1494 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1495 1496 /* default pcs_autoneg to the same setting as mac autoneg */ 1497 pcs_autoneg = hw->mac.autoneg; 1498 1499 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1500 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1501 /* sgmii mode lets the phy handle forcing speed/duplex */ 1502 pcs_autoneg = TRUE; 1503 /* autoneg time out should be disabled for SGMII mode */ 1504 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1505 break; 1506 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1507 /* disable PCS autoneg and support parallel detect only */ 1508 pcs_autoneg = FALSE; 1509 /* fall through to default case */ 1510 default: 1511 if (hw->mac.type == e1000_82575 || 1512 hw->mac.type == e1000_82576) { 1513 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1514 if (ret_val) { 1515 DEBUGOUT("NVM Read Error\n"); 1516 return ret_val; 1517 } 1518 1519 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1520 pcs_autoneg = FALSE; 1521 } 1522 1523 /* 1524 * non-SGMII modes only supports a speed of 1000/Full for the 1525 * link so it is best to just force the MAC and let the pcs 1526 * link either autoneg or be forced to 1000/Full 1527 */ 1528 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1529 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1530 1531 /* set speed of 1000/Full if speed/duplex is forced */ 1532 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1533 break; 1534 } 1535 1536 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1537 1538 /* 1539 * New SerDes mode allows for forcing speed or autonegotiating speed 1540 * at 1gb. Autoneg should be default set by most drivers. This is the 1541 * mode that will be compatible with older link partners and switches. 1542 * However, both are supported by the hardware and some drivers/tools. 1543 */ 1544 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1545 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1546 1547 /* 1548 * We force flow control to prevent the CTRL register values from being 1549 * overwritten by the autonegotiated flow control values 1550 */ 1551 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1552 1553 if (pcs_autoneg) { 1554 /* Set PCS register for autoneg */ 1555 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1556 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1557 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1558 } else { 1559 /* Set PCS register for forced link */ 1560 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1561 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1562 } 1563 1564 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1565 1566 if (!e1000_sgmii_active_82575(hw)) 1567 e1000_force_mac_fc_generic(hw); 1568 1569 return ret_val; 1570 } 1571 1572 /** 1573 * e1000_get_media_type_82575 - derives current media type. 1574 * @hw: pointer to the HW structure 1575 * 1576 * The media type is chosen reflecting few settings. 1577 * The following are taken into account: 1578 * - link mode set in the current port Init Control Word #3 1579 * - current link mode settings in CSR register 1580 * - MDIO vs. I2C PHY control interface chosen 1581 * - SFP module media type 1582 **/ 1583 static s32 e1000_get_media_type_82575(struct e1000_hw *hw) 1584 { 1585 u32 lan_id = 0; 1586 s32 ret_val = E1000_ERR_CONFIG; 1587 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1588 u32 ctrl_ext = 0; 1589 u32 current_link_mode = 0; 1590 u16 init_ctrl_wd_3 = 0; 1591 u8 init_ctrl_wd_3_offset = 0; 1592 u8 init_ctrl_wd_3_bit_offset = 0; 1593 1594 /* Set internal phy as default */ 1595 dev_spec->sgmii_active = FALSE; 1596 dev_spec->module_plugged = FALSE; 1597 1598 /* 1599 * Check if NVM access method is attached already. 1600 * If it is then Init Control Word #3 is considered 1601 * otherwise runtime CSR register content is taken. 1602 */ 1603 1604 /* Get CSR setting */ 1605 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1606 1607 /* Get link mode setting */ 1608 if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) { 1609 /* Take link mode from EEPROM */ 1610 1611 /* 1612 * Get LAN port ID to derive its 1613 * adequate Init Control Word #3 1614 */ 1615 lan_id = ((E1000_READ_REG(hw, E1000_STATUS) & 1616 E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET); 1617 /* 1618 * Derive Init Control Word #3 offset 1619 * and mask to pick up link mode setting. 1620 */ 1621 if (hw->mac.type < e1000_82580) { 1622 init_ctrl_wd_3_offset = lan_id ? 1623 NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B; 1624 init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET; 1625 } else { 1626 init_ctrl_wd_3_offset = 1627 NVM_82580_LAN_FUNC_OFFSET(lan_id) + 1628 NVM_INIT_CONTROL3_PORT_A; 1629 init_ctrl_wd_3_bit_offset = 1630 NVM_WORD24_82580_LNK_MODE_OFFSET; 1631 } 1632 /* Read Init Control Word #3*/ 1633 hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3); 1634 1635 /* 1636 * Align link mode bits to 1637 * their CTRL_EXT location. 1638 */ 1639 current_link_mode = init_ctrl_wd_3; 1640 current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET - 1641 init_ctrl_wd_3_bit_offset); 1642 current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK; 1643 1644 /* 1645 * Switch to CSR for all but internal PHY. 1646 */ 1647 if (current_link_mode != E1000_CTRL_EXT_LINK_MODE_GMII) 1648 /* Take link mode from CSR */ 1649 current_link_mode = ctrl_ext & 1650 E1000_CTRL_EXT_LINK_MODE_MASK; 1651 } else { 1652 /* Take link mode from CSR */ 1653 current_link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 1654 } 1655 1656 switch (current_link_mode) { 1657 1658 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1659 hw->phy.media_type = e1000_media_type_internal_serdes; 1660 current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX; 1661 break; 1662 case E1000_CTRL_EXT_LINK_MODE_GMII: 1663 hw->phy.media_type = e1000_media_type_copper; 1664 current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII; 1665 break; 1666 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1667 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1668 /* Get phy control interface type set (MDIO vs. I2C)*/ 1669 if (e1000_sgmii_uses_mdio_82575(hw)) { 1670 hw->phy.media_type = e1000_media_type_copper; 1671 dev_spec->sgmii_active = TRUE; 1672 current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII; 1673 } else { 1674 ret_val = e1000_set_sfp_media_type_82575(hw); 1675 if (ret_val != E1000_SUCCESS) 1676 goto out; 1677 if (hw->phy.media_type == 1678 e1000_media_type_internal_serdes) { 1679 current_link_mode = 1680 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1681 } else if (hw->phy.media_type == 1682 e1000_media_type_copper) { 1683 current_link_mode = 1684 E1000_CTRL_EXT_LINK_MODE_SGMII; 1685 } 1686 } 1687 break; 1688 default: 1689 DEBUGOUT("Link mode mask doesn't fit bit field size\n"); 1690 goto out; 1691 } 1692 /* 1693 * Do not change current link mode setting 1694 * if media type is fibre or has not been 1695 * recognized. 1696 */ 1697 if ((hw->phy.media_type != e1000_media_type_unknown) && 1698 (hw->phy.media_type != e1000_media_type_fiber)) { 1699 /* Update link mode */ 1700 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1701 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | 1702 current_link_mode); 1703 } 1704 1705 ret_val = E1000_SUCCESS; 1706 out: 1707 /* 1708 * If media type was not identified then return media type 1709 * defined by the CTRL_EXT settings. 1710 */ 1711 if (hw->phy.media_type == e1000_media_type_unknown) { 1712 if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) 1713 hw->phy.media_type = e1000_media_type_copper; 1714 else 1715 hw->phy.media_type = e1000_media_type_internal_serdes; 1716 } 1717 1718 return ret_val; 1719 } 1720 1721 /** 1722 * e1000_set_sfp_media_type_82575 - derives SFP module media type. 1723 * @hw: pointer to the HW structure 1724 * 1725 * The media type is chosen based on SFP module. 1726 * compatibility flags retrieved from SFP ID EEPROM. 1727 **/ 1728 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) 1729 { 1730 s32 ret_val = E1000_ERR_CONFIG; 1731 u32 ctrl_ext = 0; 1732 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1733 struct sfp_e1000_flags eth_flags = {0}; 1734 u8 tranceiver_type = 0; 1735 1736 /* Turn I2C interface ON */ 1737 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1738 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 1739 1740 /* Read SFP module data */ 1741 ret_val = e1000_read_sfp_data_byte(hw, 1742 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 1743 &tranceiver_type); 1744 if (ret_val != E1000_SUCCESS) 1745 goto out; 1746 ret_val = e1000_read_sfp_data_byte(hw, 1747 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 1748 (u8 *)ð_flags); 1749 if (ret_val != E1000_SUCCESS) 1750 goto out; 1751 /* 1752 * Check if there is some SFP 1753 * module plugged and powered 1754 */ 1755 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 1756 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 1757 dev_spec->module_plugged = TRUE; 1758 if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) { 1759 hw->phy.media_type = e1000_media_type_internal_serdes; 1760 } else if (eth_flags.e1000_base_t) { 1761 dev_spec->sgmii_active = TRUE; 1762 hw->phy.media_type = e1000_media_type_copper; 1763 } else { 1764 hw->phy.media_type = e1000_media_type_unknown; 1765 DEBUGOUT("PHY module has not been recognized\n"); 1766 goto out; 1767 } 1768 } else { 1769 hw->phy.media_type = e1000_media_type_unknown; 1770 } 1771 ret_val = E1000_SUCCESS; 1772 out: 1773 /* Restore I2C interface setting */ 1774 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1775 return ret_val; 1776 } 1777 1778 /** 1779 * e1000_valid_led_default_82575 - Verify a valid default LED config 1780 * @hw: pointer to the HW structure 1781 * @data: pointer to the NVM (EEPROM) 1782 * 1783 * Read the EEPROM for the current default LED configuration. If the 1784 * LED configuration is not valid, set to a valid LED configuration. 1785 **/ 1786 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1787 { 1788 s32 ret_val; 1789 1790 DEBUGFUNC("e1000_valid_led_default_82575"); 1791 1792 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1793 if (ret_val) { 1794 DEBUGOUT("NVM Read Error\n"); 1795 goto out; 1796 } 1797 1798 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1799 switch (hw->phy.media_type) { 1800 case e1000_media_type_internal_serdes: 1801 *data = ID_LED_DEFAULT_82575_SERDES; 1802 break; 1803 case e1000_media_type_copper: 1804 default: 1805 *data = ID_LED_DEFAULT; 1806 break; 1807 } 1808 } 1809 out: 1810 return ret_val; 1811 } 1812 1813 /** 1814 * e1000_sgmii_active_82575 - Return sgmii state 1815 * @hw: pointer to the HW structure 1816 * 1817 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1818 * which can be enabled for use in the embedded applications. Simply 1819 * return the current state of the sgmii interface. 1820 **/ 1821 static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1822 { 1823 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1824 return dev_spec->sgmii_active; 1825 } 1826 1827 /** 1828 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1829 * @hw: pointer to the HW structure 1830 * 1831 * Inits recommended HW defaults after a reset when there is no EEPROM 1832 * detected. This is only for the 82575. 1833 **/ 1834 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw) 1835 { 1836 DEBUGFUNC("e1000_reset_init_script_82575"); 1837 1838 if (hw->mac.type == e1000_82575) { 1839 DEBUGOUT("Running reset init script for 82575\n"); 1840 /* SerDes configuration via SERDESCTRL */ 1841 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1842 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1843 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1844 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1845 1846 /* CCM configuration via CCMCTL register */ 1847 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1848 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1849 1850 /* PCIe lanes configuration */ 1851 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1852 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1853 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1854 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1855 1856 /* PCIe PLL Configuration */ 1857 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1858 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1859 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1860 } 1861 1862 return E1000_SUCCESS; 1863 } 1864 1865 /** 1866 * e1000_read_mac_addr_82575 - Read device MAC address 1867 * @hw: pointer to the HW structure 1868 **/ 1869 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1870 { 1871 s32 ret_val = E1000_SUCCESS; 1872 1873 DEBUGFUNC("e1000_read_mac_addr_82575"); 1874 1875 /* 1876 * If there's an alternate MAC address place it in RAR0 1877 * so that it will override the Si installed default perm 1878 * address. 1879 */ 1880 ret_val = e1000_check_alt_mac_addr_generic(hw); 1881 if (ret_val) 1882 goto out; 1883 1884 ret_val = e1000_read_mac_addr_generic(hw); 1885 1886 out: 1887 return ret_val; 1888 } 1889 1890 /** 1891 * e1000_config_collision_dist_82575 - Configure collision distance 1892 * @hw: pointer to the HW structure 1893 * 1894 * Configures the collision distance to the default value and is used 1895 * during link setup. 1896 **/ 1897 static void e1000_config_collision_dist_82575(struct e1000_hw *hw) 1898 { 1899 u32 tctl_ext; 1900 1901 DEBUGFUNC("e1000_config_collision_dist_82575"); 1902 1903 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 1904 1905 tctl_ext &= ~E1000_TCTL_EXT_COLD; 1906 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 1907 1908 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 1909 E1000_WRITE_FLUSH(hw); 1910 } 1911 1912 /** 1913 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1914 * @hw: pointer to the HW structure 1915 * 1916 * In the case of a PHY power down to save power, or to turn off link during a 1917 * driver unload, or wake on lan is not enabled, remove the link. 1918 **/ 1919 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1920 { 1921 struct e1000_phy_info *phy = &hw->phy; 1922 1923 if (!(phy->ops.check_reset_block)) 1924 return; 1925 1926 /* If the management interface is not enabled, then power down */ 1927 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 1928 e1000_power_down_phy_copper(hw); 1929 1930 return; 1931 } 1932 1933 /** 1934 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1935 * @hw: pointer to the HW structure 1936 * 1937 * Clears the hardware counters by reading the counter registers. 1938 **/ 1939 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1940 { 1941 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1942 1943 e1000_clear_hw_cntrs_base_generic(hw); 1944 1945 E1000_READ_REG(hw, E1000_PRC64); 1946 E1000_READ_REG(hw, E1000_PRC127); 1947 E1000_READ_REG(hw, E1000_PRC255); 1948 E1000_READ_REG(hw, E1000_PRC511); 1949 E1000_READ_REG(hw, E1000_PRC1023); 1950 E1000_READ_REG(hw, E1000_PRC1522); 1951 E1000_READ_REG(hw, E1000_PTC64); 1952 E1000_READ_REG(hw, E1000_PTC127); 1953 E1000_READ_REG(hw, E1000_PTC255); 1954 E1000_READ_REG(hw, E1000_PTC511); 1955 E1000_READ_REG(hw, E1000_PTC1023); 1956 E1000_READ_REG(hw, E1000_PTC1522); 1957 1958 E1000_READ_REG(hw, E1000_ALGNERRC); 1959 E1000_READ_REG(hw, E1000_RXERRC); 1960 E1000_READ_REG(hw, E1000_TNCRS); 1961 E1000_READ_REG(hw, E1000_CEXTERR); 1962 E1000_READ_REG(hw, E1000_TSCTC); 1963 E1000_READ_REG(hw, E1000_TSCTFC); 1964 1965 E1000_READ_REG(hw, E1000_MGTPRC); 1966 E1000_READ_REG(hw, E1000_MGTPDC); 1967 E1000_READ_REG(hw, E1000_MGTPTC); 1968 1969 E1000_READ_REG(hw, E1000_IAC); 1970 E1000_READ_REG(hw, E1000_ICRXOC); 1971 1972 E1000_READ_REG(hw, E1000_ICRXPTC); 1973 E1000_READ_REG(hw, E1000_ICRXATC); 1974 E1000_READ_REG(hw, E1000_ICTXPTC); 1975 E1000_READ_REG(hw, E1000_ICTXATC); 1976 E1000_READ_REG(hw, E1000_ICTXQEC); 1977 E1000_READ_REG(hw, E1000_ICTXQMTC); 1978 E1000_READ_REG(hw, E1000_ICRXDMTC); 1979 1980 E1000_READ_REG(hw, E1000_CBTMPC); 1981 E1000_READ_REG(hw, E1000_HTDPMC); 1982 E1000_READ_REG(hw, E1000_CBRMPC); 1983 E1000_READ_REG(hw, E1000_RPTHC); 1984 E1000_READ_REG(hw, E1000_HGPTC); 1985 E1000_READ_REG(hw, E1000_HTCBDPC); 1986 E1000_READ_REG(hw, E1000_HGORCL); 1987 E1000_READ_REG(hw, E1000_HGORCH); 1988 E1000_READ_REG(hw, E1000_HGOTCL); 1989 E1000_READ_REG(hw, E1000_HGOTCH); 1990 E1000_READ_REG(hw, E1000_LENERRS); 1991 1992 /* This register should not be read in copper configurations */ 1993 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 1994 e1000_sgmii_active_82575(hw)) 1995 E1000_READ_REG(hw, E1000_SCVPC); 1996 } 1997 1998 /** 1999 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable 2000 * @hw: pointer to the HW structure 2001 * 2002 * After rx enable if managability is enabled then there is likely some 2003 * bad data at the start of the fifo and possibly in the DMA fifo. This 2004 * function clears the fifos and flushes any packets that came in as rx was 2005 * being enabled. 2006 **/ 2007 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 2008 { 2009 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 2010 int i, ms_wait; 2011 2012 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 2013 if (hw->mac.type != e1000_82575 || 2014 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 2015 return; 2016 2017 /* Disable all Rx queues */ 2018 for (i = 0; i < 4; i++) { 2019 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 2020 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 2021 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 2022 } 2023 /* Poll all queues to verify they have shut down */ 2024 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 2025 msec_delay(1); 2026 rx_enabled = 0; 2027 for (i = 0; i < 4; i++) 2028 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 2029 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 2030 break; 2031 } 2032 2033 if (ms_wait == 10) 2034 DEBUGOUT("Queue disable timed out after 10ms\n"); 2035 2036 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 2037 * incoming packets are rejected. Set enable and wait 2ms so that 2038 * any packet that was coming in as RCTL.EN was set is flushed 2039 */ 2040 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2041 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 2042 2043 rlpml = E1000_READ_REG(hw, E1000_RLPML); 2044 E1000_WRITE_REG(hw, E1000_RLPML, 0); 2045 2046 rctl = E1000_READ_REG(hw, E1000_RCTL); 2047 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 2048 temp_rctl |= E1000_RCTL_LPE; 2049 2050 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 2051 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 2052 E1000_WRITE_FLUSH(hw); 2053 msec_delay(2); 2054 2055 /* Enable Rx queues that were previously enabled and restore our 2056 * previous state 2057 */ 2058 for (i = 0; i < 4; i++) 2059 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 2060 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2061 E1000_WRITE_FLUSH(hw); 2062 2063 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 2064 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2065 2066 /* Flush receive errors generated by workaround */ 2067 E1000_READ_REG(hw, E1000_ROC); 2068 E1000_READ_REG(hw, E1000_RNBC); 2069 E1000_READ_REG(hw, E1000_MPC); 2070 } 2071 2072 /** 2073 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 2074 * @hw: pointer to the HW structure 2075 * 2076 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2077 * however the hardware default for these parts is 500us to 1ms which is less 2078 * than the 10ms recommended by the pci-e spec. To address this we need to 2079 * increase the value to either 10ms to 200ms for capability version 1 config, 2080 * or 16ms to 55ms for version 2. 2081 **/ 2082 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 2083 { 2084 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 2085 s32 ret_val = E1000_SUCCESS; 2086 u16 pcie_devctl2; 2087 2088 /* only take action if timeout value is defaulted to 0 */ 2089 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2090 goto out; 2091 2092 /* 2093 * if capababilities version is type 1 we can write the 2094 * timeout of 10ms to 200ms through the GCR register 2095 */ 2096 if (!(gcr & E1000_GCR_CAP_VER2)) { 2097 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2098 goto out; 2099 } 2100 2101 /* 2102 * for version 2 capabilities we need to write the config space 2103 * directly in order to set the completion timeout value for 2104 * 16ms to 55ms 2105 */ 2106 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2107 &pcie_devctl2); 2108 if (ret_val) 2109 goto out; 2110 2111 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2112 2113 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2114 &pcie_devctl2); 2115 out: 2116 /* disable completion timeout resend */ 2117 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2118 2119 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2120 return ret_val; 2121 } 2122 2123 /** 2124 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2125 * @hw: pointer to the hardware struct 2126 * @enable: state to enter, either enabled or disabled 2127 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2128 * 2129 * enables/disables L2 switch anti-spoofing functionality. 2130 **/ 2131 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2132 { 2133 u32 dtxswc; 2134 2135 switch (hw->mac.type) { 2136 case e1000_82576: 2137 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2138 if (enable) { 2139 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2140 E1000_DTXSWC_VLAN_SPOOF_MASK); 2141 /* The PF can spoof - it has to in order to 2142 * support emulation mode NICs */ 2143 dtxswc ^= (1 << pf | 1 << (pf + 2144 E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 2145 } else { 2146 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2147 E1000_DTXSWC_VLAN_SPOOF_MASK); 2148 } 2149 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2150 break; 2151 case e1000_i350: 2152 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2153 if (enable) { 2154 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2155 E1000_DTXSWC_VLAN_SPOOF_MASK); 2156 /* The PF can spoof - it has to in order to 2157 * support emulation mode NICs 2158 */ 2159 dtxswc ^= (1 << pf | 1 << (pf + 2160 E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 2161 } else { 2162 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2163 E1000_DTXSWC_VLAN_SPOOF_MASK); 2164 } 2165 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2166 default: 2167 break; 2168 } 2169 } 2170 2171 /** 2172 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 2173 * @hw: pointer to the hardware struct 2174 * @enable: state to enter, either enabled or disabled 2175 * 2176 * enables/disables L2 switch loopback functionality. 2177 **/ 2178 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2179 { 2180 u32 dtxswc; 2181 2182 switch (hw->mac.type) { 2183 case e1000_82576: 2184 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2185 if (enable) 2186 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2187 else 2188 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2189 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2190 break; 2191 case e1000_i350: 2192 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2193 if (enable) 2194 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2195 else 2196 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2197 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2198 break; 2199 default: 2200 /* Currently no other hardware supports loopback */ 2201 break; 2202 } 2203 2204 2205 } 2206 2207 /** 2208 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 2209 * @hw: pointer to the hardware struct 2210 * @enable: state to enter, either enabled or disabled 2211 * 2212 * enables/disables replication of packets across multiple pools. 2213 **/ 2214 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2215 { 2216 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 2217 2218 if (enable) 2219 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2220 else 2221 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2222 2223 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 2224 } 2225 2226 /** 2227 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 2228 * @hw: pointer to the HW structure 2229 * @offset: register offset to be read 2230 * @data: pointer to the read data 2231 * 2232 * Reads the MDI control register in the PHY at offset and stores the 2233 * information read to data. 2234 **/ 2235 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2236 { 2237 s32 ret_val; 2238 2239 DEBUGFUNC("e1000_read_phy_reg_82580"); 2240 2241 ret_val = hw->phy.ops.acquire(hw); 2242 if (ret_val) 2243 goto out; 2244 2245 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 2246 2247 hw->phy.ops.release(hw); 2248 2249 out: 2250 return ret_val; 2251 } 2252 2253 /** 2254 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 2255 * @hw: pointer to the HW structure 2256 * @offset: register offset to write to 2257 * @data: data to write to register at offset 2258 * 2259 * Writes data to MDI control register in the PHY at offset. 2260 **/ 2261 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2262 { 2263 s32 ret_val; 2264 2265 DEBUGFUNC("e1000_write_phy_reg_82580"); 2266 2267 ret_val = hw->phy.ops.acquire(hw); 2268 if (ret_val) 2269 goto out; 2270 2271 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 2272 2273 hw->phy.ops.release(hw); 2274 2275 out: 2276 return ret_val; 2277 } 2278 2279 /** 2280 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2281 * @hw: pointer to the HW structure 2282 * 2283 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2284 * the values found in the EEPROM. This addresses an issue in which these 2285 * bits are not restored from EEPROM after reset. 2286 **/ 2287 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 2288 { 2289 s32 ret_val = E1000_SUCCESS; 2290 u32 mdicnfg; 2291 u16 nvm_data = 0; 2292 2293 DEBUGFUNC("e1000_reset_mdicnfg_82580"); 2294 2295 if (hw->mac.type != e1000_82580) 2296 goto out; 2297 if (!e1000_sgmii_active_82575(hw)) 2298 goto out; 2299 2300 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2301 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2302 &nvm_data); 2303 if (ret_val) { 2304 DEBUGOUT("NVM Read Error\n"); 2305 goto out; 2306 } 2307 2308 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 2309 if (nvm_data & NVM_WORD24_EXT_MDIO) 2310 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2311 if (nvm_data & NVM_WORD24_COM_MDIO) 2312 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2313 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 2314 out: 2315 return ret_val; 2316 } 2317 2318 /** 2319 * e1000_reset_hw_82580 - Reset hardware 2320 * @hw: pointer to the HW structure 2321 * 2322 * This resets function or entire device (all ports, etc.) 2323 * to a known state. 2324 **/ 2325 static s32 e1000_reset_hw_82580(struct e1000_hw *hw) 2326 { 2327 s32 ret_val = E1000_SUCCESS; 2328 /* BH SW mailbox bit in SW_FW_SYNC */ 2329 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2330 u32 ctrl; 2331 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2332 2333 DEBUGFUNC("e1000_reset_hw_82580"); 2334 2335 hw->dev_spec._82575.global_device_reset = FALSE; 2336 2337 /* Get current control state. */ 2338 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2339 2340 /* 2341 * Prevent the PCI-E bus from sticking if there is no TLP connection 2342 * on the last TLP read/write transaction when MAC is reset. 2343 */ 2344 ret_val = e1000_disable_pcie_master_generic(hw); 2345 if (ret_val) 2346 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2347 2348 DEBUGOUT("Masking off all interrupts\n"); 2349 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2350 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2351 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2352 E1000_WRITE_FLUSH(hw); 2353 2354 msec_delay(10); 2355 2356 /* Determine whether or not a global dev reset is requested */ 2357 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw, 2358 swmbsw_mask)) 2359 global_device_reset = FALSE; 2360 2361 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) & 2362 E1000_STAT_DEV_RST_SET)) 2363 ctrl |= E1000_CTRL_DEV_RST; 2364 else 2365 ctrl |= E1000_CTRL_RST; 2366 2367 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2368 E1000_WRITE_FLUSH(hw); 2369 2370 /* Add delay to insure DEV_RST has time to complete */ 2371 if (global_device_reset) 2372 msec_delay(5); 2373 2374 ret_val = e1000_get_auto_rd_done_generic(hw); 2375 if (ret_val) { 2376 /* 2377 * When auto config read does not complete, do not 2378 * return with an error. This can happen in situations 2379 * where there is no eeprom and prevents getting link. 2380 */ 2381 DEBUGOUT("Auto Read Done did not complete\n"); 2382 } 2383 2384 /* If EEPROM is not present, run manual init scripts */ 2385 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 2386 e1000_reset_init_script_82575(hw); 2387 2388 /* clear global device reset status bit */ 2389 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 2390 2391 /* Clear any pending interrupt events. */ 2392 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2393 E1000_READ_REG(hw, E1000_ICR); 2394 2395 ret_val = e1000_reset_mdicnfg_82580(hw); 2396 if (ret_val) 2397 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 2398 2399 /* Install any alternate MAC address into RAR0 */ 2400 ret_val = e1000_check_alt_mac_addr_generic(hw); 2401 2402 /* Release semaphore */ 2403 if (global_device_reset) 2404 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2405 2406 return ret_val; 2407 } 2408 2409 /** 2410 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size 2411 * @data: data received by reading RXPBS register 2412 * 2413 * The 82580 uses a table based approach for packet buffer allocation sizes. 2414 * This function converts the retrieved value into the correct table value 2415 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2416 * 0x0 36 72 144 1 2 4 8 16 2417 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2418 */ 2419 u16 e1000_rxpbs_adjust_82580(u32 data) 2420 { 2421 u16 ret_val = 0; 2422 2423 if (data < E1000_82580_RXPBS_TABLE_SIZE) 2424 ret_val = e1000_82580_rxpbs_table[data]; 2425 2426 return ret_val; 2427 } 2428 2429 /** 2430 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM 2431 * checksum 2432 * @hw: pointer to the HW structure 2433 * @offset: offset in words of the checksum protected region 2434 * 2435 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2436 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2437 **/ 2438 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2439 { 2440 s32 ret_val = E1000_SUCCESS; 2441 u16 checksum = 0; 2442 u16 i, nvm_data; 2443 2444 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); 2445 2446 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2447 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2448 if (ret_val) { 2449 DEBUGOUT("NVM Read Error\n"); 2450 goto out; 2451 } 2452 checksum += nvm_data; 2453 } 2454 2455 if (checksum != (u16) NVM_SUM) { 2456 DEBUGOUT("NVM Checksum Invalid\n"); 2457 ret_val = -E1000_ERR_NVM; 2458 goto out; 2459 } 2460 2461 out: 2462 return ret_val; 2463 } 2464 2465 /** 2466 * e1000_update_nvm_checksum_with_offset - Update EEPROM 2467 * checksum 2468 * @hw: pointer to the HW structure 2469 * @offset: offset in words of the checksum protected region 2470 * 2471 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2472 * up to the checksum. Then calculates the EEPROM checksum and writes the 2473 * value to the EEPROM. 2474 **/ 2475 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2476 { 2477 s32 ret_val; 2478 u16 checksum = 0; 2479 u16 i, nvm_data; 2480 2481 DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); 2482 2483 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2484 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2485 if (ret_val) { 2486 DEBUGOUT("NVM Read Error while updating checksum.\n"); 2487 goto out; 2488 } 2489 checksum += nvm_data; 2490 } 2491 checksum = (u16) NVM_SUM - checksum; 2492 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2493 &checksum); 2494 if (ret_val) 2495 DEBUGOUT("NVM Write Error while updating checksum.\n"); 2496 2497 out: 2498 return ret_val; 2499 } 2500 2501 /** 2502 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum 2503 * @hw: pointer to the HW structure 2504 * 2505 * Calculates the EEPROM section checksum by reading/adding each word of 2506 * the EEPROM and then verifies that the sum of the EEPROM is 2507 * equal to 0xBABA. 2508 **/ 2509 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) 2510 { 2511 s32 ret_val = E1000_SUCCESS; 2512 u16 eeprom_regions_count = 1; 2513 u16 j, nvm_data; 2514 u16 nvm_offset; 2515 2516 DEBUGFUNC("e1000_validate_nvm_checksum_82580"); 2517 2518 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2519 if (ret_val) { 2520 DEBUGOUT("NVM Read Error\n"); 2521 goto out; 2522 } 2523 2524 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2525 /* if chekcsums compatibility bit is set validate checksums 2526 * for all 4 ports. */ 2527 eeprom_regions_count = 4; 2528 } 2529 2530 for (j = 0; j < eeprom_regions_count; j++) { 2531 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2532 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2533 nvm_offset); 2534 if (ret_val != E1000_SUCCESS) 2535 goto out; 2536 } 2537 2538 out: 2539 return ret_val; 2540 } 2541 2542 /** 2543 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum 2544 * @hw: pointer to the HW structure 2545 * 2546 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2547 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2548 * checksum and writes the value to the EEPROM. 2549 **/ 2550 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) 2551 { 2552 s32 ret_val; 2553 u16 j, nvm_data; 2554 u16 nvm_offset; 2555 2556 DEBUGFUNC("e1000_update_nvm_checksum_82580"); 2557 2558 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2559 if (ret_val) { 2560 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n"); 2561 goto out; 2562 } 2563 2564 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) { 2565 /* set compatibility bit to validate checksums appropriately */ 2566 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2567 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2568 &nvm_data); 2569 if (ret_val) { 2570 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n"); 2571 goto out; 2572 } 2573 } 2574 2575 for (j = 0; j < 4; j++) { 2576 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2577 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2578 if (ret_val) 2579 goto out; 2580 } 2581 2582 out: 2583 return ret_val; 2584 } 2585 2586 /** 2587 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum 2588 * @hw: pointer to the HW structure 2589 * 2590 * Calculates the EEPROM section checksum by reading/adding each word of 2591 * the EEPROM and then verifies that the sum of the EEPROM is 2592 * equal to 0xBABA. 2593 **/ 2594 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) 2595 { 2596 s32 ret_val = E1000_SUCCESS; 2597 u16 j; 2598 u16 nvm_offset; 2599 2600 DEBUGFUNC("e1000_validate_nvm_checksum_i350"); 2601 2602 for (j = 0; j < 4; j++) { 2603 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2604 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2605 nvm_offset); 2606 if (ret_val != E1000_SUCCESS) 2607 goto out; 2608 } 2609 2610 out: 2611 return ret_val; 2612 } 2613 2614 /** 2615 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum 2616 * @hw: pointer to the HW structure 2617 * 2618 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2619 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2620 * checksum and writes the value to the EEPROM. 2621 **/ 2622 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) 2623 { 2624 s32 ret_val = E1000_SUCCESS; 2625 u16 j; 2626 u16 nvm_offset; 2627 2628 DEBUGFUNC("e1000_update_nvm_checksum_i350"); 2629 2630 for (j = 0; j < 4; j++) { 2631 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2632 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2633 if (ret_val != E1000_SUCCESS) 2634 goto out; 2635 } 2636 2637 out: 2638 return ret_val; 2639 } 2640 2641 /** 2642 * e1000_set_eee_i350 - Enable/disable EEE support 2643 * @hw: pointer to the HW structure 2644 * 2645 * Enable/disable EEE based on setting in dev_spec structure. 2646 * 2647 **/ 2648 s32 e1000_set_eee_i350(struct e1000_hw *hw) 2649 { 2650 s32 ret_val = E1000_SUCCESS; 2651 u32 ipcnfg, eeer; 2652 2653 DEBUGFUNC("e1000_set_eee_i350"); 2654 2655 if ((hw->mac.type < e1000_i350) || 2656 (hw->phy.media_type != e1000_media_type_copper)) 2657 goto out; 2658 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); 2659 eeer = E1000_READ_REG(hw, E1000_EEER); 2660 2661 /* enable or disable per user setting */ 2662 if (!(hw->dev_spec._82575.eee_disable)) { 2663 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2664 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2665 E1000_EEER_LPI_FC); 2666 2667 } else { 2668 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2669 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2670 E1000_EEER_LPI_FC); 2671 } 2672 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 2673 E1000_WRITE_REG(hw, E1000_EEER, eeer); 2674 E1000_READ_REG(hw, E1000_IPCNFG); 2675 E1000_READ_REG(hw, E1000_EEER); 2676 out: 2677 2678 return ret_val; 2679 } 2680 2681 /* Due to a hw errata, if the host tries to configure the VFTA register 2682 * while performing queries from the BMC or DMA, then the VFTA in some 2683 * cases won't be written. 2684 */ 2685 2686 /** 2687 * e1000_clear_vfta_i350 - Clear VLAN filter table 2688 * @hw: pointer to the HW structure 2689 * 2690 * Clears the register array which contains the VLAN filter table by 2691 * setting all the values to 0. 2692 **/ 2693 void e1000_clear_vfta_i350(struct e1000_hw *hw) 2694 { 2695 u32 offset; 2696 int i; 2697 2698 DEBUGFUNC("e1000_clear_vfta_350"); 2699 2700 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 2701 for (i = 0; i < 10; i++) 2702 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 2703 2704 E1000_WRITE_FLUSH(hw); 2705 } 2706 } 2707 2708 /** 2709 * e1000_write_vfta_i350 - Write value to VLAN filter table 2710 * @hw: pointer to the HW structure 2711 * @offset: register offset in VLAN filter table 2712 * @value: register value written to VLAN filter table 2713 * 2714 * Writes value at the given offset in the register array which stores 2715 * the VLAN filter table. 2716 **/ 2717 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 2718 { 2719 int i; 2720 2721 DEBUGFUNC("e1000_write_vfta_350"); 2722 2723 for (i = 0; i < 10; i++) 2724 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 2725 2726 E1000_WRITE_FLUSH(hw); 2727 } 2728 2729 2730 /** 2731 * e1000_set_i2c_bb - Enable I2C bit-bang 2732 * @hw: pointer to the HW structure 2733 * 2734 * Enable I2C bit-bang interface 2735 * 2736 **/ 2737 s32 e1000_set_i2c_bb(struct e1000_hw *hw) 2738 { 2739 s32 ret_val = E1000_SUCCESS; 2740 u32 ctrl_ext, i2cparams; 2741 2742 DEBUGFUNC("e1000_set_i2c_bb"); 2743 2744 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2745 ctrl_ext |= E1000_CTRL_I2C_ENA; 2746 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2747 E1000_WRITE_FLUSH(hw); 2748 2749 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS); 2750 i2cparams |= E1000_I2CBB_EN; 2751 i2cparams |= E1000_I2C_DATA_OE_N; 2752 i2cparams |= E1000_I2C_CLK_OE_N; 2753 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams); 2754 E1000_WRITE_FLUSH(hw); 2755 2756 return ret_val; 2757 } 2758 2759 /** 2760 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C 2761 * @hw: pointer to hardware structure 2762 * @byte_offset: byte offset to read 2763 * @dev_addr: device address 2764 * @data: value read 2765 * 2766 * Performs byte read operation over I2C interface at 2767 * a specified device address. 2768 **/ 2769 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 2770 u8 dev_addr, u8 *data) 2771 { 2772 s32 status = E1000_SUCCESS; 2773 u32 max_retry = 10; 2774 u32 retry = 1; 2775 u16 swfw_mask = 0; 2776 2777 bool nack = TRUE; 2778 2779 DEBUGFUNC("e1000_read_i2c_byte_generic"); 2780 2781 swfw_mask = E1000_SWFW_PHY0_SM; 2782 2783 do { 2784 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 2785 != E1000_SUCCESS) { 2786 status = E1000_ERR_SWFW_SYNC; 2787 goto read_byte_out; 2788 } 2789 2790 e1000_i2c_start(hw); 2791 2792 /* Device Address and write indication */ 2793 status = e1000_clock_out_i2c_byte(hw, dev_addr); 2794 if (status != E1000_SUCCESS) 2795 goto fail; 2796 2797 status = e1000_get_i2c_ack(hw); 2798 if (status != E1000_SUCCESS) 2799 goto fail; 2800 2801 status = e1000_clock_out_i2c_byte(hw, byte_offset); 2802 if (status != E1000_SUCCESS) 2803 goto fail; 2804 2805 status = e1000_get_i2c_ack(hw); 2806 if (status != E1000_SUCCESS) 2807 goto fail; 2808 2809 e1000_i2c_start(hw); 2810 2811 /* Device Address and read indication */ 2812 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2813 if (status != E1000_SUCCESS) 2814 goto fail; 2815 2816 status = e1000_get_i2c_ack(hw); 2817 if (status != E1000_SUCCESS) 2818 goto fail; 2819 2820 status = e1000_clock_in_i2c_byte(hw, data); 2821 if (status != E1000_SUCCESS) 2822 goto fail; 2823 2824 status = e1000_clock_out_i2c_bit(hw, nack); 2825 if (status != E1000_SUCCESS) 2826 goto fail; 2827 2828 e1000_i2c_stop(hw); 2829 break; 2830 2831 fail: 2832 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2833 msec_delay(100); 2834 e1000_i2c_bus_clear(hw); 2835 retry++; 2836 if (retry < max_retry) 2837 DEBUGOUT("I2C byte read error - Retrying.\n"); 2838 else 2839 DEBUGOUT("I2C byte read error.\n"); 2840 2841 } while (retry < max_retry); 2842 2843 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2844 2845 read_byte_out: 2846 2847 return status; 2848 } 2849 2850 /** 2851 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C 2852 * @hw: pointer to hardware structure 2853 * @byte_offset: byte offset to write 2854 * @dev_addr: device address 2855 * @data: value to write 2856 * 2857 * Performs byte write operation over I2C interface at 2858 * a specified device address. 2859 **/ 2860 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 2861 u8 dev_addr, u8 data) 2862 { 2863 s32 status = E1000_SUCCESS; 2864 u32 max_retry = 1; 2865 u32 retry = 0; 2866 u16 swfw_mask = 0; 2867 2868 DEBUGFUNC("e1000_write_i2c_byte_generic"); 2869 2870 swfw_mask = E1000_SWFW_PHY0_SM; 2871 2872 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) { 2873 status = E1000_ERR_SWFW_SYNC; 2874 goto write_byte_out; 2875 } 2876 2877 do { 2878 e1000_i2c_start(hw); 2879 2880 status = e1000_clock_out_i2c_byte(hw, dev_addr); 2881 if (status != E1000_SUCCESS) 2882 goto fail; 2883 2884 status = e1000_get_i2c_ack(hw); 2885 if (status != E1000_SUCCESS) 2886 goto fail; 2887 2888 status = e1000_clock_out_i2c_byte(hw, byte_offset); 2889 if (status != E1000_SUCCESS) 2890 goto fail; 2891 2892 status = e1000_get_i2c_ack(hw); 2893 if (status != E1000_SUCCESS) 2894 goto fail; 2895 2896 status = e1000_clock_out_i2c_byte(hw, data); 2897 if (status != E1000_SUCCESS) 2898 goto fail; 2899 2900 status = e1000_get_i2c_ack(hw); 2901 if (status != E1000_SUCCESS) 2902 goto fail; 2903 2904 e1000_i2c_stop(hw); 2905 break; 2906 2907 fail: 2908 e1000_i2c_bus_clear(hw); 2909 retry++; 2910 if (retry < max_retry) 2911 DEBUGOUT("I2C byte write error - Retrying.\n"); 2912 else 2913 DEBUGOUT("I2C byte write error.\n"); 2914 } while (retry < max_retry); 2915 2916 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2917 2918 write_byte_out: 2919 2920 return status; 2921 } 2922 2923 /** 2924 * e1000_i2c_start - Sets I2C start condition 2925 * @hw: pointer to hardware structure 2926 * 2927 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2928 **/ 2929 static void e1000_i2c_start(struct e1000_hw *hw) 2930 { 2931 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 2932 2933 DEBUGFUNC("e1000_i2c_start"); 2934 2935 /* Start condition must begin with data and clock high */ 2936 e1000_set_i2c_data(hw, &i2cctl, 1); 2937 e1000_raise_i2c_clk(hw, &i2cctl); 2938 2939 /* Setup time for start condition (4.7us) */ 2940 usec_delay(E1000_I2C_T_SU_STA); 2941 2942 e1000_set_i2c_data(hw, &i2cctl, 0); 2943 2944 /* Hold time for start condition (4us) */ 2945 usec_delay(E1000_I2C_T_HD_STA); 2946 2947 e1000_lower_i2c_clk(hw, &i2cctl); 2948 2949 /* Minimum low period of clock is 4.7 us */ 2950 usec_delay(E1000_I2C_T_LOW); 2951 2952 } 2953 2954 /** 2955 * e1000_i2c_stop - Sets I2C stop condition 2956 * @hw: pointer to hardware structure 2957 * 2958 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2959 **/ 2960 static void e1000_i2c_stop(struct e1000_hw *hw) 2961 { 2962 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 2963 2964 DEBUGFUNC("e1000_i2c_stop"); 2965 2966 /* Stop condition must begin with data low and clock high */ 2967 e1000_set_i2c_data(hw, &i2cctl, 0); 2968 e1000_raise_i2c_clk(hw, &i2cctl); 2969 2970 /* Setup time for stop condition (4us) */ 2971 usec_delay(E1000_I2C_T_SU_STO); 2972 2973 e1000_set_i2c_data(hw, &i2cctl, 1); 2974 2975 /* bus free time between stop and start (4.7us)*/ 2976 usec_delay(E1000_I2C_T_BUF); 2977 } 2978 2979 /** 2980 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C 2981 * @hw: pointer to hardware structure 2982 * @data: data byte to clock in 2983 * 2984 * Clocks in one byte data via I2C data/clock 2985 **/ 2986 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data) 2987 { 2988 s32 i; 2989 bool bit = 0; 2990 2991 DEBUGFUNC("e1000_clock_in_i2c_byte"); 2992 2993 *data = 0; 2994 for (i = 7; i >= 0; i--) { 2995 e1000_clock_in_i2c_bit(hw, &bit); 2996 *data |= bit << i; 2997 } 2998 2999 return E1000_SUCCESS; 3000 } 3001 3002 /** 3003 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C 3004 * @hw: pointer to hardware structure 3005 * @data: data byte clocked out 3006 * 3007 * Clocks out one byte data via I2C data/clock 3008 **/ 3009 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data) 3010 { 3011 s32 status = E1000_SUCCESS; 3012 s32 i; 3013 u32 i2cctl; 3014 bool bit = 0; 3015 3016 DEBUGFUNC("e1000_clock_out_i2c_byte"); 3017 3018 for (i = 7; i >= 0; i--) { 3019 bit = (data >> i) & 0x1; 3020 status = e1000_clock_out_i2c_bit(hw, bit); 3021 3022 if (status != E1000_SUCCESS) 3023 break; 3024 } 3025 3026 /* Release SDA line (set high) */ 3027 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3028 3029 i2cctl |= E1000_I2C_DATA_OE_N; 3030 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl); 3031 E1000_WRITE_FLUSH(hw); 3032 3033 return status; 3034 } 3035 3036 /** 3037 * e1000_get_i2c_ack - Polls for I2C ACK 3038 * @hw: pointer to hardware structure 3039 * 3040 * Clocks in/out one bit via I2C data/clock 3041 **/ 3042 static s32 e1000_get_i2c_ack(struct e1000_hw *hw) 3043 { 3044 s32 status = E1000_SUCCESS; 3045 u32 i = 0; 3046 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3047 u32 timeout = 10; 3048 bool ack = TRUE; 3049 3050 DEBUGFUNC("e1000_get_i2c_ack"); 3051 3052 e1000_raise_i2c_clk(hw, &i2cctl); 3053 3054 /* Minimum high period of clock is 4us */ 3055 usec_delay(E1000_I2C_T_HIGH); 3056 3057 /* Wait until SCL returns high */ 3058 for (i = 0; i < timeout; i++) { 3059 usec_delay(1); 3060 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3061 if (i2cctl & E1000_I2C_CLK_IN) 3062 break; 3063 } 3064 if (!(i2cctl & E1000_I2C_CLK_IN)) 3065 return E1000_ERR_I2C; 3066 3067 ack = e1000_get_i2c_data(&i2cctl); 3068 if (ack) { 3069 DEBUGOUT("I2C ack was not received.\n"); 3070 status = E1000_ERR_I2C; 3071 } 3072 3073 e1000_lower_i2c_clk(hw, &i2cctl); 3074 3075 /* Minimum low period of clock is 4.7 us */ 3076 usec_delay(E1000_I2C_T_LOW); 3077 3078 return status; 3079 } 3080 3081 /** 3082 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 3083 * @hw: pointer to hardware structure 3084 * @data: read data value 3085 * 3086 * Clocks in one bit via I2C data/clock 3087 **/ 3088 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data) 3089 { 3090 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3091 3092 DEBUGFUNC("e1000_clock_in_i2c_bit"); 3093 3094 e1000_raise_i2c_clk(hw, &i2cctl); 3095 3096 /* Minimum high period of clock is 4us */ 3097 usec_delay(E1000_I2C_T_HIGH); 3098 3099 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3100 *data = e1000_get_i2c_data(&i2cctl); 3101 3102 e1000_lower_i2c_clk(hw, &i2cctl); 3103 3104 /* Minimum low period of clock is 4.7 us */ 3105 usec_delay(E1000_I2C_T_LOW); 3106 3107 return E1000_SUCCESS; 3108 } 3109 3110 /** 3111 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 3112 * @hw: pointer to hardware structure 3113 * @data: data value to write 3114 * 3115 * Clocks out one bit via I2C data/clock 3116 **/ 3117 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data) 3118 { 3119 s32 status; 3120 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3121 3122 DEBUGFUNC("e1000_clock_out_i2c_bit"); 3123 3124 status = e1000_set_i2c_data(hw, &i2cctl, data); 3125 if (status == E1000_SUCCESS) { 3126 e1000_raise_i2c_clk(hw, &i2cctl); 3127 3128 /* Minimum high period of clock is 4us */ 3129 usec_delay(E1000_I2C_T_HIGH); 3130 3131 e1000_lower_i2c_clk(hw, &i2cctl); 3132 3133 /* Minimum low period of clock is 4.7 us. 3134 * This also takes care of the data hold time. 3135 */ 3136 usec_delay(E1000_I2C_T_LOW); 3137 } else { 3138 status = E1000_ERR_I2C; 3139 DEBUGOUT1("I2C data was not set to %X\n", data); 3140 } 3141 3142 return status; 3143 } 3144 /** 3145 * e1000_raise_i2c_clk - Raises the I2C SCL clock 3146 * @hw: pointer to hardware structure 3147 * @i2cctl: Current value of I2CCTL register 3148 * 3149 * Raises the I2C clock line '0'->'1' 3150 **/ 3151 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3152 { 3153 DEBUGFUNC("e1000_raise_i2c_clk"); 3154 3155 *i2cctl |= E1000_I2C_CLK_OUT; 3156 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3157 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3158 E1000_WRITE_FLUSH(hw); 3159 3160 /* SCL rise time (1000ns) */ 3161 usec_delay(E1000_I2C_T_RISE); 3162 } 3163 3164 /** 3165 * e1000_lower_i2c_clk - Lowers the I2C SCL clock 3166 * @hw: pointer to hardware structure 3167 * @i2cctl: Current value of I2CCTL register 3168 * 3169 * Lowers the I2C clock line '1'->'0' 3170 **/ 3171 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3172 { 3173 3174 DEBUGFUNC("e1000_lower_i2c_clk"); 3175 3176 *i2cctl &= ~E1000_I2C_CLK_OUT; 3177 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3178 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3179 E1000_WRITE_FLUSH(hw); 3180 3181 /* SCL fall time (300ns) */ 3182 usec_delay(E1000_I2C_T_FALL); 3183 } 3184 3185 /** 3186 * e1000_set_i2c_data - Sets the I2C data bit 3187 * @hw: pointer to hardware structure 3188 * @i2cctl: Current value of I2CCTL register 3189 * @data: I2C data value (0 or 1) to set 3190 * 3191 * Sets the I2C data bit 3192 **/ 3193 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data) 3194 { 3195 s32 status = E1000_SUCCESS; 3196 3197 DEBUGFUNC("e1000_set_i2c_data"); 3198 3199 if (data) 3200 *i2cctl |= E1000_I2C_DATA_OUT; 3201 else 3202 *i2cctl &= ~E1000_I2C_DATA_OUT; 3203 3204 *i2cctl &= ~E1000_I2C_DATA_OE_N; 3205 *i2cctl |= E1000_I2C_CLK_OE_N; 3206 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3207 E1000_WRITE_FLUSH(hw); 3208 3209 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 3210 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA); 3211 3212 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3213 if (data != e1000_get_i2c_data(i2cctl)) { 3214 status = E1000_ERR_I2C; 3215 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 3216 } 3217 3218 return status; 3219 } 3220 3221 /** 3222 * e1000_get_i2c_data - Reads the I2C SDA data bit 3223 * @hw: pointer to hardware structure 3224 * @i2cctl: Current value of I2CCTL register 3225 * 3226 * Returns the I2C data bit value 3227 **/ 3228 static bool e1000_get_i2c_data(u32 *i2cctl) 3229 { 3230 bool data; 3231 3232 DEBUGFUNC("e1000_get_i2c_data"); 3233 3234 if (*i2cctl & E1000_I2C_DATA_IN) 3235 data = 1; 3236 else 3237 data = 0; 3238 3239 return data; 3240 } 3241 3242 /** 3243 * e1000_i2c_bus_clear - Clears the I2C bus 3244 * @hw: pointer to hardware structure 3245 * 3246 * Clears the I2C bus by sending nine clock pulses. 3247 * Used when data line is stuck low. 3248 **/ 3249 void e1000_i2c_bus_clear(struct e1000_hw *hw) 3250 { 3251 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3252 u32 i; 3253 3254 DEBUGFUNC("e1000_i2c_bus_clear"); 3255 3256 e1000_i2c_start(hw); 3257 3258 e1000_set_i2c_data(hw, &i2cctl, 1); 3259 3260 for (i = 0; i < 9; i++) { 3261 e1000_raise_i2c_clk(hw, &i2cctl); 3262 3263 /* Min high period of clock is 4us */ 3264 usec_delay(E1000_I2C_T_HIGH); 3265 3266 e1000_lower_i2c_clk(hw, &i2cctl); 3267 3268 /* Min low period of clock is 4.7us*/ 3269 usec_delay(E1000_I2C_T_LOW); 3270 } 3271 3272 e1000_i2c_start(hw); 3273 3274 /* Put the i2c bus back to default state */ 3275 e1000_i2c_stop(hw); 3276 } 3277 3278