1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82571EB Gigabit Ethernet Controller 37 * 82571EB Gigabit Ethernet Controller (Copper) 38 * 82571EB Gigabit Ethernet Controller (Fiber) 39 * 82571EB Dual Port Gigabit Mezzanine Adapter 40 * 82571EB Quad Port Gigabit Mezzanine Adapter 41 * 82571PT Gigabit PT Quad Port Server ExpressModule 42 * 82572EI Gigabit Ethernet Controller (Copper) 43 * 82572EI Gigabit Ethernet Controller (Fiber) 44 * 82572EI Gigabit Ethernet Controller 45 * 82573V Gigabit Ethernet Controller (Copper) 46 * 82573E Gigabit Ethernet Controller (Copper) 47 * 82573L Gigabit Ethernet Controller 48 * 82574L Gigabit Network Connection 49 * 82583V Gigabit Network Connection 50 */ 51 52 #include "e1000_api.h" 53 54 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 55 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 56 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 57 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 58 static void e1000_release_nvm_82571(struct e1000_hw *hw); 59 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 60 u16 words, u16 *data); 61 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 62 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 63 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 64 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 65 bool active); 66 static s32 e1000_reset_hw_82571(struct e1000_hw *hw); 67 static s32 e1000_init_hw_82571(struct e1000_hw *hw); 68 static void e1000_clear_vfta_82571(struct e1000_hw *hw); 69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 70 static s32 e1000_led_on_82574(struct e1000_hw *hw); 71 static s32 e1000_setup_link_82571(struct e1000_hw *hw); 72 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 73 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 74 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 75 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 76 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 77 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 78 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 79 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 80 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 81 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 82 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 83 u16 words, u16 *data); 84 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 85 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 86 87 /** 88 * e1000_init_phy_params_82571 - Init PHY func ptrs. 89 * @hw: pointer to the HW structure 90 **/ 91 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 92 { 93 struct e1000_phy_info *phy = &hw->phy; 94 s32 ret_val = E1000_SUCCESS; 95 96 DEBUGFUNC("e1000_init_phy_params_82571"); 97 98 if (hw->phy.media_type != e1000_media_type_copper) { 99 phy->type = e1000_phy_none; 100 goto out; 101 } 102 103 phy->addr = 1; 104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 105 phy->reset_delay_us = 100; 106 107 phy->ops.acquire = e1000_get_hw_semaphore_82571; 108 phy->ops.check_reset_block = e1000_check_reset_block_generic; 109 phy->ops.release = e1000_put_hw_semaphore_82571; 110 phy->ops.reset = e1000_phy_hw_reset_generic; 111 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 112 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 113 phy->ops.power_up = e1000_power_up_phy_copper; 114 phy->ops.power_down = e1000_power_down_phy_copper_82571; 115 116 switch (hw->mac.type) { 117 case e1000_82571: 118 case e1000_82572: 119 phy->type = e1000_phy_igp_2; 120 phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 121 phy->ops.get_info = e1000_get_phy_info_igp; 122 phy->ops.check_polarity = e1000_check_polarity_igp; 123 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 124 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 125 phy->ops.read_reg = e1000_read_phy_reg_igp; 126 phy->ops.write_reg = e1000_write_phy_reg_igp; 127 128 /* This uses above function pointers */ 129 ret_val = e1000_get_phy_id_82571(hw); 130 131 /* Verify PHY ID */ 132 if (phy->id != IGP01E1000_I_PHY_ID) { 133 ret_val = -E1000_ERR_PHY; 134 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 135 goto out; 136 } 137 break; 138 case e1000_82573: 139 phy->type = e1000_phy_m88; 140 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 141 phy->ops.get_info = e1000_get_phy_info_m88; 142 phy->ops.check_polarity = e1000_check_polarity_m88; 143 phy->ops.commit = e1000_phy_sw_reset_generic; 144 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 145 phy->ops.get_cable_length = e1000_get_cable_length_m88; 146 phy->ops.read_reg = e1000_read_phy_reg_m88; 147 phy->ops.write_reg = e1000_write_phy_reg_m88; 148 149 /* This uses above function pointers */ 150 ret_val = e1000_get_phy_id_82571(hw); 151 152 /* Verify PHY ID */ 153 if (phy->id != M88E1111_I_PHY_ID) { 154 ret_val = -E1000_ERR_PHY; 155 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 156 goto out; 157 } 158 break; 159 case e1000_82574: 160 case e1000_82583: 161 phy->type = e1000_phy_bm; 162 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 163 phy->ops.get_info = e1000_get_phy_info_m88; 164 phy->ops.check_polarity = e1000_check_polarity_m88; 165 phy->ops.commit = e1000_phy_sw_reset_generic; 166 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 167 phy->ops.get_cable_length = e1000_get_cable_length_m88; 168 phy->ops.read_reg = e1000_read_phy_reg_bm2; 169 phy->ops.write_reg = e1000_write_phy_reg_bm2; 170 171 /* This uses above function pointers */ 172 ret_val = e1000_get_phy_id_82571(hw); 173 /* Verify PHY ID */ 174 if (phy->id != BME1000_E_PHY_ID_R2) { 175 ret_val = -E1000_ERR_PHY; 176 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 177 goto out; 178 } 179 break; 180 default: 181 ret_val = -E1000_ERR_PHY; 182 goto out; 183 break; 184 } 185 186 out: 187 return ret_val; 188 } 189 190 /** 191 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 192 * @hw: pointer to the HW structure 193 **/ 194 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 195 { 196 struct e1000_nvm_info *nvm = &hw->nvm; 197 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 198 u16 size; 199 200 DEBUGFUNC("e1000_init_nvm_params_82571"); 201 202 nvm->opcode_bits = 8; 203 nvm->delay_usec = 1; 204 switch (nvm->override) { 205 case e1000_nvm_override_spi_large: 206 nvm->page_size = 32; 207 nvm->address_bits = 16; 208 break; 209 case e1000_nvm_override_spi_small: 210 nvm->page_size = 8; 211 nvm->address_bits = 8; 212 break; 213 default: 214 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 215 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 216 break; 217 } 218 219 switch (hw->mac.type) { 220 case e1000_82573: 221 case e1000_82574: 222 case e1000_82583: 223 if (((eecd >> 15) & 0x3) == 0x3) { 224 nvm->type = e1000_nvm_flash_hw; 225 nvm->word_size = 2048; 226 /* 227 * Autonomous Flash update bit must be cleared due 228 * to Flash update issue. 229 */ 230 eecd &= ~E1000_EECD_AUPDEN; 231 E1000_WRITE_REG(hw, E1000_EECD, eecd); 232 break; 233 } 234 /* Fall Through */ 235 default: 236 nvm->type = e1000_nvm_eeprom_spi; 237 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 238 E1000_EECD_SIZE_EX_SHIFT); 239 /* 240 * Added to a constant, "size" becomes the left-shift value 241 * for setting word_size. 242 */ 243 size += NVM_WORD_SIZE_BASE_SHIFT; 244 245 /* EEPROM access above 16k is unsupported */ 246 if (size > 14) 247 size = 14; 248 nvm->word_size = 1 << size; 249 break; 250 } 251 252 /* Function Pointers */ 253 nvm->ops.acquire = e1000_acquire_nvm_82571; 254 nvm->ops.read = e1000_read_nvm_eerd; 255 nvm->ops.release = e1000_release_nvm_82571; 256 nvm->ops.update = e1000_update_nvm_checksum_82571; 257 nvm->ops.validate = e1000_validate_nvm_checksum_82571; 258 nvm->ops.valid_led_default = e1000_valid_led_default_82571; 259 nvm->ops.write = e1000_write_nvm_82571; 260 261 return E1000_SUCCESS; 262 } 263 264 /** 265 * e1000_init_mac_params_82571 - Init MAC func ptrs. 266 * @hw: pointer to the HW structure 267 **/ 268 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 269 { 270 struct e1000_mac_info *mac = &hw->mac; 271 u32 swsm = 0; 272 u32 swsm2 = 0; 273 bool force_clear_smbi = FALSE; 274 275 DEBUGFUNC("e1000_init_mac_params_82571"); 276 277 /* Set media type and media-dependent function pointers */ 278 switch (hw->device_id) { 279 case E1000_DEV_ID_82571EB_FIBER: 280 case E1000_DEV_ID_82572EI_FIBER: 281 case E1000_DEV_ID_82571EB_QUAD_FIBER: 282 hw->phy.media_type = e1000_media_type_fiber; 283 mac->ops.setup_physical_interface = 284 e1000_setup_fiber_serdes_link_82571; 285 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 286 mac->ops.get_link_up_info = 287 e1000_get_speed_and_duplex_fiber_serdes_generic; 288 break; 289 case E1000_DEV_ID_82571EB_SERDES: 290 case E1000_DEV_ID_82571EB_SERDES_DUAL: 291 case E1000_DEV_ID_82571EB_SERDES_QUAD: 292 case E1000_DEV_ID_82572EI_SERDES: 293 hw->phy.media_type = e1000_media_type_internal_serdes; 294 mac->ops.setup_physical_interface = 295 e1000_setup_fiber_serdes_link_82571; 296 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 297 mac->ops.get_link_up_info = 298 e1000_get_speed_and_duplex_fiber_serdes_generic; 299 break; 300 default: 301 hw->phy.media_type = e1000_media_type_copper; 302 mac->ops.setup_physical_interface = 303 e1000_setup_copper_link_82571; 304 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 305 mac->ops.get_link_up_info = 306 e1000_get_speed_and_duplex_copper_generic; 307 break; 308 } 309 310 /* Set mta register count */ 311 mac->mta_reg_count = 128; 312 /* Set rar entry count */ 313 mac->rar_entry_count = E1000_RAR_ENTRIES; 314 /* Set if part includes ASF firmware */ 315 mac->asf_firmware_present = TRUE; 316 /* Set if manageability features are enabled. */ 317 mac->arc_subsystem_valid = 318 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 319 ? TRUE : FALSE; 320 /* Adaptive IFS supported */ 321 mac->adaptive_ifs = TRUE; 322 323 /* Function pointers */ 324 325 /* bus type/speed/width */ 326 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 327 /* reset */ 328 mac->ops.reset_hw = e1000_reset_hw_82571; 329 /* hw initialization */ 330 mac->ops.init_hw = e1000_init_hw_82571; 331 /* link setup */ 332 mac->ops.setup_link = e1000_setup_link_82571; 333 /* multicast address update */ 334 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 335 /* writing VFTA */ 336 mac->ops.write_vfta = e1000_write_vfta_generic; 337 /* clearing VFTA */ 338 mac->ops.clear_vfta = e1000_clear_vfta_82571; 339 /* setting MTA */ 340 mac->ops.mta_set = e1000_mta_set_generic; 341 /* read mac address */ 342 mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 343 /* ID LED init */ 344 mac->ops.id_led_init = e1000_id_led_init_generic; 345 /* blink LED */ 346 mac->ops.blink_led = e1000_blink_led_generic; 347 /* setup LED */ 348 mac->ops.setup_led = e1000_setup_led_generic; 349 /* cleanup LED */ 350 mac->ops.cleanup_led = e1000_cleanup_led_generic; 351 /* turn off LED */ 352 mac->ops.led_off = e1000_led_off_generic; 353 /* clear hardware counters */ 354 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 355 356 /* MAC-specific function pointers */ 357 switch (hw->mac.type) { 358 case e1000_82573: 359 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 360 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 361 mac->ops.led_on = e1000_led_on_generic; 362 break; 363 case e1000_82574: 364 case e1000_82583: 365 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 366 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 367 mac->ops.led_on = e1000_led_on_82574; 368 break; 369 default: 370 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 371 mac->ops.led_on = e1000_led_on_generic; 372 break; 373 } 374 375 /* 376 * Ensure that the inter-port SWSM.SMBI lock bit is clear before 377 * first NVM or PHY acess. This should be done for single-port 378 * devices, and for one port only on dual-port devices so that 379 * for those devices we can still use the SMBI lock to synchronize 380 * inter-port accesses to the PHY & NVM. 381 */ 382 switch (hw->mac.type) { 383 case e1000_82571: 384 case e1000_82572: 385 swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 386 387 if (!(swsm2 & E1000_SWSM2_LOCK)) { 388 /* Only do this for the first interface on this card */ 389 E1000_WRITE_REG(hw, E1000_SWSM2, 390 swsm2 | E1000_SWSM2_LOCK); 391 force_clear_smbi = TRUE; 392 } else 393 force_clear_smbi = FALSE; 394 break; 395 default: 396 force_clear_smbi = TRUE; 397 break; 398 } 399 400 if (force_clear_smbi) { 401 /* Make sure SWSM.SMBI is clear */ 402 swsm = E1000_READ_REG(hw, E1000_SWSM); 403 if (swsm & E1000_SWSM_SMBI) { 404 /* This bit should not be set on a first interface, and 405 * indicates that the bootagent or EFI code has 406 * improperly left this bit enabled 407 */ 408 DEBUGOUT("Please update your 82571 Bootagent\n"); 409 } 410 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 411 } 412 413 /* 414 * Initialze device specific counter of SMBI acquisition 415 * timeouts. 416 */ 417 hw->dev_spec._82571.smb_counter = 0; 418 419 return E1000_SUCCESS; 420 } 421 422 /** 423 * e1000_init_function_pointers_82571 - Init func ptrs. 424 * @hw: pointer to the HW structure 425 * 426 * Called to initialize all function pointers and parameters. 427 **/ 428 void e1000_init_function_pointers_82571(struct e1000_hw *hw) 429 { 430 DEBUGFUNC("e1000_init_function_pointers_82571"); 431 432 hw->mac.ops.init_params = e1000_init_mac_params_82571; 433 hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 434 hw->phy.ops.init_params = e1000_init_phy_params_82571; 435 } 436 437 /** 438 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 439 * @hw: pointer to the HW structure 440 * 441 * Reads the PHY registers and stores the PHY ID and possibly the PHY 442 * revision in the hardware structure. 443 **/ 444 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 445 { 446 struct e1000_phy_info *phy = &hw->phy; 447 s32 ret_val = E1000_SUCCESS; 448 u16 phy_id = 0; 449 450 DEBUGFUNC("e1000_get_phy_id_82571"); 451 452 switch (hw->mac.type) { 453 case e1000_82571: 454 case e1000_82572: 455 /* 456 * The 82571 firmware may still be configuring the PHY. 457 * In this case, we cannot access the PHY until the 458 * configuration is done. So we explicitly set the 459 * PHY ID. 460 */ 461 phy->id = IGP01E1000_I_PHY_ID; 462 break; 463 case e1000_82573: 464 ret_val = e1000_get_phy_id(hw); 465 break; 466 case e1000_82574: 467 case e1000_82583: 468 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 469 if (ret_val) 470 goto out; 471 472 phy->id = (u32)(phy_id << 16); 473 usec_delay(20); 474 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 475 if (ret_val) 476 goto out; 477 478 phy->id |= (u32)(phy_id); 479 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 480 break; 481 default: 482 ret_val = -E1000_ERR_PHY; 483 break; 484 } 485 out: 486 return ret_val; 487 } 488 489 /** 490 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 491 * @hw: pointer to the HW structure 492 * 493 * Acquire the HW semaphore to access the PHY or NVM 494 **/ 495 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 496 { 497 u32 swsm; 498 s32 ret_val = E1000_SUCCESS; 499 s32 sw_timeout = hw->nvm.word_size + 1; 500 s32 fw_timeout = hw->nvm.word_size + 1; 501 s32 i = 0; 502 503 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 504 505 /* 506 * If we have timedout 3 times on trying to acquire 507 * the inter-port SMBI semaphore, there is old code 508 * operating on the other port, and it is not 509 * releasing SMBI. Modify the number of times that 510 * we try for the semaphore to interwork with this 511 * older code. 512 */ 513 if (hw->dev_spec._82571.smb_counter > 2) 514 sw_timeout = 1; 515 516 /* Get the SW semaphore */ 517 while (i < sw_timeout) { 518 swsm = E1000_READ_REG(hw, E1000_SWSM); 519 if (!(swsm & E1000_SWSM_SMBI)) 520 break; 521 522 usec_delay(50); 523 i++; 524 } 525 526 if (i == sw_timeout) { 527 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 528 hw->dev_spec._82571.smb_counter++; 529 } 530 /* Get the FW semaphore. */ 531 for (i = 0; i < fw_timeout; i++) { 532 swsm = E1000_READ_REG(hw, E1000_SWSM); 533 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 534 535 /* Semaphore acquired if bit latched */ 536 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 537 break; 538 539 usec_delay(50); 540 } 541 542 if (i == fw_timeout) { 543 /* Release semaphores */ 544 e1000_put_hw_semaphore_82571(hw); 545 DEBUGOUT("Driver can't access the NVM\n"); 546 ret_val = -E1000_ERR_NVM; 547 goto out; 548 } 549 550 out: 551 return ret_val; 552 } 553 554 /** 555 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 556 * @hw: pointer to the HW structure 557 * 558 * Release hardware semaphore used to access the PHY or NVM 559 **/ 560 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 561 { 562 u32 swsm; 563 564 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 565 566 swsm = E1000_READ_REG(hw, E1000_SWSM); 567 568 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 569 570 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 571 } 572 573 /** 574 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 575 * @hw: pointer to the HW structure 576 * 577 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 578 * Then for non-82573 hardware, set the EEPROM access request bit and wait 579 * for EEPROM access grant bit. If the access grant bit is not set, release 580 * hardware semaphore. 581 **/ 582 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 583 { 584 s32 ret_val; 585 586 DEBUGFUNC("e1000_acquire_nvm_82571"); 587 588 ret_val = e1000_get_hw_semaphore_82571(hw); 589 if (ret_val) 590 goto out; 591 592 switch (hw->mac.type) { 593 case e1000_82573: 594 case e1000_82574: 595 case e1000_82583: 596 break; 597 default: 598 ret_val = e1000_acquire_nvm_generic(hw); 599 break; 600 } 601 602 if (ret_val) 603 e1000_put_hw_semaphore_82571(hw); 604 605 out: 606 return ret_val; 607 } 608 609 /** 610 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 611 * @hw: pointer to the HW structure 612 * 613 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 614 **/ 615 static void e1000_release_nvm_82571(struct e1000_hw *hw) 616 { 617 DEBUGFUNC("e1000_release_nvm_82571"); 618 619 e1000_release_nvm_generic(hw); 620 e1000_put_hw_semaphore_82571(hw); 621 } 622 623 /** 624 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 625 * @hw: pointer to the HW structure 626 * @offset: offset within the EEPROM to be written to 627 * @words: number of words to write 628 * @data: 16 bit word(s) to be written to the EEPROM 629 * 630 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 631 * 632 * If e1000_update_nvm_checksum is not called after this function, the 633 * EEPROM will most likely contain an invalid checksum. 634 **/ 635 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 636 u16 *data) 637 { 638 s32 ret_val = E1000_SUCCESS; 639 640 DEBUGFUNC("e1000_write_nvm_82571"); 641 642 switch (hw->mac.type) { 643 case e1000_82573: 644 case e1000_82574: 645 case e1000_82583: 646 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 647 break; 648 case e1000_82571: 649 case e1000_82572: 650 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 651 break; 652 default: 653 ret_val = -E1000_ERR_NVM; 654 break; 655 } 656 657 return ret_val; 658 } 659 660 /** 661 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 662 * @hw: pointer to the HW structure 663 * 664 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 665 * up to the checksum. Then calculates the EEPROM checksum and writes the 666 * value to the EEPROM. 667 **/ 668 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 669 { 670 u32 eecd; 671 s32 ret_val; 672 u16 i; 673 674 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 675 676 ret_val = e1000_update_nvm_checksum_generic(hw); 677 if (ret_val) 678 goto out; 679 680 /* 681 * If our nvm is an EEPROM, then we're done 682 * otherwise, commit the checksum to the flash NVM. 683 */ 684 if (hw->nvm.type != e1000_nvm_flash_hw) 685 goto out; 686 687 /* Check for pending operations. */ 688 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 689 msec_delay(1); 690 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 691 break; 692 } 693 694 if (i == E1000_FLASH_UPDATES) { 695 ret_val = -E1000_ERR_NVM; 696 goto out; 697 } 698 699 /* Reset the firmware if using STM opcode. */ 700 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 701 /* 702 * The enabling of and the actual reset must be done 703 * in two write cycles. 704 */ 705 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 706 E1000_WRITE_FLUSH(hw); 707 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 708 } 709 710 /* Commit the write to flash */ 711 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 712 E1000_WRITE_REG(hw, E1000_EECD, eecd); 713 714 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 715 msec_delay(1); 716 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 717 break; 718 } 719 720 if (i == E1000_FLASH_UPDATES) { 721 ret_val = -E1000_ERR_NVM; 722 goto out; 723 } 724 725 out: 726 return ret_val; 727 } 728 729 /** 730 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 731 * @hw: pointer to the HW structure 732 * 733 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 734 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 735 **/ 736 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 737 { 738 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 739 740 if (hw->nvm.type == e1000_nvm_flash_hw) 741 e1000_fix_nvm_checksum_82571(hw); 742 743 return e1000_validate_nvm_checksum_generic(hw); 744 } 745 746 /** 747 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 748 * @hw: pointer to the HW structure 749 * @offset: offset within the EEPROM to be written to 750 * @words: number of words to write 751 * @data: 16 bit word(s) to be written to the EEPROM 752 * 753 * After checking for invalid values, poll the EEPROM to ensure the previous 754 * command has completed before trying to write the next word. After write 755 * poll for completion. 756 * 757 * If e1000_update_nvm_checksum is not called after this function, the 758 * EEPROM will most likely contain an invalid checksum. 759 **/ 760 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 761 u16 words, u16 *data) 762 { 763 struct e1000_nvm_info *nvm = &hw->nvm; 764 u32 i, eewr = 0; 765 s32 ret_val = 0; 766 767 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 768 769 /* 770 * A check for invalid values: offset too large, too many words, 771 * and not enough words. 772 */ 773 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 774 (words == 0)) { 775 DEBUGOUT("nvm parameter(s) out of bounds\n"); 776 ret_val = -E1000_ERR_NVM; 777 goto out; 778 } 779 780 for (i = 0; i < words; i++) { 781 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 782 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 783 E1000_NVM_RW_REG_START; 784 785 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 786 if (ret_val) 787 break; 788 789 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 790 791 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 792 if (ret_val) 793 break; 794 } 795 796 out: 797 return ret_val; 798 } 799 800 /** 801 * e1000_get_cfg_done_82571 - Poll for configuration done 802 * @hw: pointer to the HW structure 803 * 804 * Reads the management control register for the config done bit to be set. 805 **/ 806 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 807 { 808 s32 timeout = PHY_CFG_TIMEOUT; 809 s32 ret_val = E1000_SUCCESS; 810 811 DEBUGFUNC("e1000_get_cfg_done_82571"); 812 813 while (timeout) { 814 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & 815 E1000_NVM_CFG_DONE_PORT_0) 816 break; 817 msec_delay(1); 818 timeout--; 819 } 820 if (!timeout) { 821 DEBUGOUT("MNG configuration cycle has not completed.\n"); 822 ret_val = -E1000_ERR_RESET; 823 goto out; 824 } 825 826 out: 827 return ret_val; 828 } 829 830 /** 831 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 832 * @hw: pointer to the HW structure 833 * @active: TRUE to enable LPLU, FALSE to disable 834 * 835 * Sets the LPLU D0 state according to the active flag. When activating LPLU 836 * this function also disables smart speed and vice versa. LPLU will not be 837 * activated unless the device autonegotiation advertisement meets standards 838 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 839 * pointer entry point only called by PHY setup routines. 840 **/ 841 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 842 { 843 struct e1000_phy_info *phy = &hw->phy; 844 s32 ret_val = E1000_SUCCESS; 845 u16 data; 846 847 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 848 849 if (!(phy->ops.read_reg)) 850 goto out; 851 852 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 853 if (ret_val) 854 goto out; 855 856 if (active) { 857 data |= IGP02E1000_PM_D0_LPLU; 858 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 859 data); 860 if (ret_val) 861 goto out; 862 863 /* When LPLU is enabled, we should disable SmartSpeed */ 864 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 865 &data); 866 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 867 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 868 data); 869 if (ret_val) 870 goto out; 871 } else { 872 data &= ~IGP02E1000_PM_D0_LPLU; 873 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 874 data); 875 /* 876 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 877 * during Dx states where the power conservation is most 878 * important. During driver activity we should enable 879 * SmartSpeed, so performance is maintained. 880 */ 881 if (phy->smart_speed == e1000_smart_speed_on) { 882 ret_val = phy->ops.read_reg(hw, 883 IGP01E1000_PHY_PORT_CONFIG, 884 &data); 885 if (ret_val) 886 goto out; 887 888 data |= IGP01E1000_PSCFR_SMART_SPEED; 889 ret_val = phy->ops.write_reg(hw, 890 IGP01E1000_PHY_PORT_CONFIG, 891 data); 892 if (ret_val) 893 goto out; 894 } else if (phy->smart_speed == e1000_smart_speed_off) { 895 ret_val = phy->ops.read_reg(hw, 896 IGP01E1000_PHY_PORT_CONFIG, 897 &data); 898 if (ret_val) 899 goto out; 900 901 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 902 ret_val = phy->ops.write_reg(hw, 903 IGP01E1000_PHY_PORT_CONFIG, 904 data); 905 if (ret_val) 906 goto out; 907 } 908 } 909 910 out: 911 return ret_val; 912 } 913 914 /** 915 * e1000_reset_hw_82571 - Reset hardware 916 * @hw: pointer to the HW structure 917 * 918 * This resets the hardware into a known state. 919 **/ 920 static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 921 { 922 u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 923 s32 ret_val; 924 u16 i = 0; 925 926 DEBUGFUNC("e1000_reset_hw_82571"); 927 928 /* 929 * Prevent the PCI-E bus from sticking if there is no TLP connection 930 * on the last TLP read/write transaction when MAC is reset. 931 */ 932 ret_val = e1000_disable_pcie_master_generic(hw); 933 if (ret_val) 934 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 935 936 DEBUGOUT("Masking off all interrupts\n"); 937 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 938 939 E1000_WRITE_REG(hw, E1000_RCTL, 0); 940 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 941 E1000_WRITE_FLUSH(hw); 942 943 msec_delay(10); 944 945 /* 946 * Must acquire the MDIO ownership before MAC reset. 947 * Ownership defaults to firmware after a reset. 948 */ 949 switch (hw->mac.type) { 950 case e1000_82573: 951 case e1000_82574: 952 case e1000_82583: 953 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 954 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 955 956 do { 957 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 958 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 959 960 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 961 break; 962 963 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 964 965 msec_delay(2); 966 i++; 967 } while (i < MDIO_OWNERSHIP_TIMEOUT); 968 break; 969 default: 970 break; 971 } 972 973 ctrl = E1000_READ_REG(hw, E1000_CTRL); 974 975 DEBUGOUT("Issuing a global reset to MAC\n"); 976 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 977 978 if (hw->nvm.type == e1000_nvm_flash_hw) { 979 usec_delay(10); 980 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 981 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 982 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 983 E1000_WRITE_FLUSH(hw); 984 } 985 986 ret_val = e1000_get_auto_rd_done_generic(hw); 987 if (ret_val) 988 /* We don't want to continue accessing MAC registers. */ 989 goto out; 990 991 /* 992 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 993 * Need to wait for Phy configuration completion before accessing 994 * NVM and Phy. 995 */ 996 997 switch (hw->mac.type) { 998 case e1000_82573: 999 case e1000_82574: 1000 case e1000_82583: 1001 msec_delay(25); 1002 break; 1003 default: 1004 break; 1005 } 1006 1007 /* Clear any pending interrupt events. */ 1008 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1009 icr = E1000_READ_REG(hw, E1000_ICR); 1010 1011 /* Install any alternate MAC address into RAR0 */ 1012 ret_val = e1000_check_alt_mac_addr_generic(hw); 1013 if (ret_val) 1014 goto out; 1015 1016 e1000_set_laa_state_82571(hw, TRUE); 1017 1018 /* Reinitialize the 82571 serdes link state machine */ 1019 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1020 hw->mac.serdes_link_state = e1000_serdes_link_down; 1021 1022 out: 1023 return ret_val; 1024 } 1025 1026 /** 1027 * e1000_init_hw_82571 - Initialize hardware 1028 * @hw: pointer to the HW structure 1029 * 1030 * This inits the hardware readying it for operation. 1031 **/ 1032 static s32 e1000_init_hw_82571(struct e1000_hw *hw) 1033 { 1034 struct e1000_mac_info *mac = &hw->mac; 1035 u32 reg_data; 1036 s32 ret_val; 1037 u16 i, rar_count = mac->rar_entry_count; 1038 1039 DEBUGFUNC("e1000_init_hw_82571"); 1040 1041 e1000_initialize_hw_bits_82571(hw); 1042 1043 /* Initialize identification LED */ 1044 ret_val = mac->ops.id_led_init(hw); 1045 if (ret_val) 1046 DEBUGOUT("Error initializing identification LED\n"); 1047 /* This is not fatal and we should not stop init due to this */ 1048 1049 /* Disabling VLAN filtering */ 1050 DEBUGOUT("Initializing the IEEE VLAN\n"); 1051 mac->ops.clear_vfta(hw); 1052 1053 /* Setup the receive address. */ 1054 /* 1055 * If, however, a locally administered address was assigned to the 1056 * 82571, we must reserve a RAR for it to work around an issue where 1057 * resetting one port will reload the MAC on the other port. 1058 */ 1059 if (e1000_get_laa_state_82571(hw)) 1060 rar_count--; 1061 e1000_init_rx_addrs_generic(hw, rar_count); 1062 1063 /* Zero out the Multicast HASH table */ 1064 DEBUGOUT("Zeroing the MTA\n"); 1065 for (i = 0; i < mac->mta_reg_count; i++) 1066 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1067 1068 /* Setup link and flow control */ 1069 ret_val = mac->ops.setup_link(hw); 1070 1071 /* Set the transmit descriptor write-back policy */ 1072 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1073 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1074 E1000_TXDCTL_FULL_TX_DESC_WB | 1075 E1000_TXDCTL_COUNT_DESC; 1076 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1077 1078 /* ...for both queues. */ 1079 switch (mac->type) { 1080 case e1000_82573: 1081 case e1000_82574: 1082 case e1000_82583: 1083 e1000_enable_tx_pkt_filtering_generic(hw); 1084 reg_data = E1000_READ_REG(hw, E1000_GCR); 1085 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1086 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1087 break; 1088 default: 1089 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1090 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1091 E1000_TXDCTL_FULL_TX_DESC_WB | 1092 E1000_TXDCTL_COUNT_DESC; 1093 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1094 break; 1095 } 1096 1097 /* 1098 * Clear all of the statistics registers (clear on read). It is 1099 * important that we do this after we have tried to establish link 1100 * because the symbol error count will increment wildly if there 1101 * is no link. 1102 */ 1103 e1000_clear_hw_cntrs_82571(hw); 1104 1105 return ret_val; 1106 } 1107 1108 /** 1109 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1110 * @hw: pointer to the HW structure 1111 * 1112 * Initializes required hardware-dependent bits needed for normal operation. 1113 **/ 1114 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1115 { 1116 u32 reg; 1117 1118 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1119 1120 /* Transmit Descriptor Control 0 */ 1121 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1122 reg |= (1 << 22); 1123 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1124 1125 /* Transmit Descriptor Control 1 */ 1126 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1127 reg |= (1 << 22); 1128 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1129 1130 /* Transmit Arbitration Control 0 */ 1131 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1132 reg &= ~(0xF << 27); /* 30:27 */ 1133 switch (hw->mac.type) { 1134 case e1000_82571: 1135 case e1000_82572: 1136 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1137 break; 1138 default: 1139 break; 1140 } 1141 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1142 1143 /* Transmit Arbitration Control 1 */ 1144 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1145 switch (hw->mac.type) { 1146 case e1000_82571: 1147 case e1000_82572: 1148 reg &= ~((1 << 29) | (1 << 30)); 1149 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1150 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1151 reg &= ~(1 << 28); 1152 else 1153 reg |= (1 << 28); 1154 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1155 break; 1156 default: 1157 break; 1158 } 1159 1160 /* Device Control */ 1161 switch (hw->mac.type) { 1162 case e1000_82573: 1163 case e1000_82574: 1164 case e1000_82583: 1165 reg = E1000_READ_REG(hw, E1000_CTRL); 1166 reg &= ~(1 << 29); 1167 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1168 break; 1169 default: 1170 break; 1171 } 1172 1173 /* Extended Device Control */ 1174 switch (hw->mac.type) { 1175 case e1000_82573: 1176 case e1000_82574: 1177 case e1000_82583: 1178 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1179 reg &= ~(1 << 23); 1180 reg |= (1 << 22); 1181 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1182 break; 1183 default: 1184 break; 1185 } 1186 1187 if (hw->mac.type == e1000_82571) { 1188 reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1189 reg |= E1000_PBA_ECC_CORR_EN; 1190 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1191 } 1192 1193 /* 1194 * Workaround for hardware errata. 1195 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1196 */ 1197 if ((hw->mac.type == e1000_82571) || 1198 (hw->mac.type == e1000_82572)) { 1199 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1200 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1201 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1202 } 1203 1204 /* PCI-Ex Control Registers */ 1205 switch (hw->mac.type) { 1206 case e1000_82574: 1207 case e1000_82583: 1208 reg = E1000_READ_REG(hw, E1000_GCR); 1209 reg |= (1 << 22); 1210 E1000_WRITE_REG(hw, E1000_GCR, reg); 1211 1212 /* 1213 * Workaround for hardware errata. 1214 * apply workaround for hardware errata documented in errata 1215 * docs Fixes issue where some error prone or unreliable PCIe 1216 * completions are occurring, particularly with ASPM enabled. 1217 * Without fix, issue can cause tx timeouts. 1218 */ 1219 reg = E1000_READ_REG(hw, E1000_GCR2); 1220 reg |= 1; 1221 E1000_WRITE_REG(hw, E1000_GCR2, reg); 1222 break; 1223 default: 1224 break; 1225 } 1226 1227 return; 1228 } 1229 1230 /** 1231 * e1000_clear_vfta_82571 - Clear VLAN filter table 1232 * @hw: pointer to the HW structure 1233 * 1234 * Clears the register array which contains the VLAN filter table by 1235 * setting all the values to 0. 1236 **/ 1237 static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1238 { 1239 u32 offset; 1240 u32 vfta_value = 0; 1241 u32 vfta_offset = 0; 1242 u32 vfta_bit_in_reg = 0; 1243 1244 DEBUGFUNC("e1000_clear_vfta_82571"); 1245 1246 switch (hw->mac.type) { 1247 case e1000_82573: 1248 case e1000_82574: 1249 case e1000_82583: 1250 if (hw->mng_cookie.vlan_id != 0) { 1251 /* 1252 * The VFTA is a 4096b bit-field, each identifying 1253 * a single VLAN ID. The following operations 1254 * determine which 32b entry (i.e. offset) into the 1255 * array we want to set the VLAN ID (i.e. bit) of 1256 * the manageability unit. 1257 */ 1258 vfta_offset = (hw->mng_cookie.vlan_id >> 1259 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 1260 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1261 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1262 } 1263 break; 1264 default: 1265 break; 1266 } 1267 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1268 /* 1269 * If the offset we want to clear is the same offset of the 1270 * manageability VLAN ID, then clear all bits except that of 1271 * the manageability unit. 1272 */ 1273 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1274 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1275 E1000_WRITE_FLUSH(hw); 1276 } 1277 } 1278 1279 /** 1280 * e1000_check_mng_mode_82574 - Check manageability is enabled 1281 * @hw: pointer to the HW structure 1282 * 1283 * Reads the NVM Initialization Control Word 2 and returns TRUE 1284 * (>0) if any manageability is enabled, else FALSE (0). 1285 **/ 1286 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1287 { 1288 u16 data; 1289 1290 DEBUGFUNC("e1000_check_mng_mode_82574"); 1291 1292 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1293 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1294 } 1295 1296 /** 1297 * e1000_led_on_82574 - Turn LED on 1298 * @hw: pointer to the HW structure 1299 * 1300 * Turn LED on. 1301 **/ 1302 static s32 e1000_led_on_82574(struct e1000_hw *hw) 1303 { 1304 u32 ctrl; 1305 u32 i; 1306 1307 DEBUGFUNC("e1000_led_on_82574"); 1308 1309 ctrl = hw->mac.ledctl_mode2; 1310 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1311 /* 1312 * If no link, then turn LED on by setting the invert bit 1313 * for each LED that's "on" (0x0E) in ledctl_mode2. 1314 */ 1315 for (i = 0; i < 4; i++) 1316 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1317 E1000_LEDCTL_MODE_LED_ON) 1318 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1319 } 1320 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1321 1322 return E1000_SUCCESS; 1323 } 1324 1325 1326 /** 1327 * e1000_setup_link_82571 - Setup flow control and link settings 1328 * @hw: pointer to the HW structure 1329 * 1330 * Determines which flow control settings to use, then configures flow 1331 * control. Calls the appropriate media-specific link configuration 1332 * function. Assuming the adapter has a valid link partner, a valid link 1333 * should be established. Assumes the hardware has previously been reset 1334 * and the transmitter and receiver are not enabled. 1335 **/ 1336 static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1337 { 1338 DEBUGFUNC("e1000_setup_link_82571"); 1339 1340 /* 1341 * 82573 does not have a word in the NVM to determine 1342 * the default flow control setting, so we explicitly 1343 * set it to full. 1344 */ 1345 switch (hw->mac.type) { 1346 case e1000_82573: 1347 case e1000_82574: 1348 case e1000_82583: 1349 if (hw->fc.requested_mode == e1000_fc_default) 1350 hw->fc.requested_mode = e1000_fc_full; 1351 break; 1352 default: 1353 break; 1354 } 1355 return e1000_setup_link_generic(hw); 1356 } 1357 1358 /** 1359 * e1000_setup_copper_link_82571 - Configure copper link settings 1360 * @hw: pointer to the HW structure 1361 * 1362 * Configures the link for auto-neg or forced speed and duplex. Then we check 1363 * for link, once link is established calls to configure collision distance 1364 * and flow control are called. 1365 **/ 1366 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1367 { 1368 u32 ctrl; 1369 s32 ret_val; 1370 1371 DEBUGFUNC("e1000_setup_copper_link_82571"); 1372 1373 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1374 ctrl |= E1000_CTRL_SLU; 1375 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1376 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1377 1378 switch (hw->phy.type) { 1379 case e1000_phy_m88: 1380 case e1000_phy_bm: 1381 ret_val = e1000_copper_link_setup_m88(hw); 1382 break; 1383 case e1000_phy_igp_2: 1384 ret_val = e1000_copper_link_setup_igp(hw); 1385 break; 1386 default: 1387 ret_val = -E1000_ERR_PHY; 1388 break; 1389 } 1390 1391 if (ret_val) 1392 goto out; 1393 1394 ret_val = e1000_setup_copper_link_generic(hw); 1395 1396 out: 1397 return ret_val; 1398 } 1399 1400 /** 1401 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1402 * @hw: pointer to the HW structure 1403 * 1404 * Configures collision distance and flow control for fiber and serdes links. 1405 * Upon successful setup, poll for link. 1406 **/ 1407 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1408 { 1409 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1410 1411 switch (hw->mac.type) { 1412 case e1000_82571: 1413 case e1000_82572: 1414 /* 1415 * If SerDes loopback mode is entered, there is no form 1416 * of reset to take the adapter out of that mode. So we 1417 * have to explicitly take the adapter out of loopback 1418 * mode. This prevents drivers from twiddling their thumbs 1419 * if another tool failed to take it out of loopback mode. 1420 */ 1421 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1422 break; 1423 default: 1424 break; 1425 } 1426 1427 return e1000_setup_fiber_serdes_link_generic(hw); 1428 } 1429 1430 /** 1431 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1432 * @hw: pointer to the HW structure 1433 * 1434 * Reports the link state as up or down. 1435 * 1436 * If autonegotiation is supported by the link partner, the link state is 1437 * determined by the result of autonegotiation. This is the most likely case. 1438 * If autonegotiation is not supported by the link partner, and the link 1439 * has a valid signal, force the link up. 1440 * 1441 * The link state is represented internally here by 4 states: 1442 * 1443 * 1) down 1444 * 2) autoneg_progress 1445 * 3) autoneg_complete (the link sucessfully autonegotiated) 1446 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1447 * 1448 **/ 1449 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1450 { 1451 struct e1000_mac_info *mac = &hw->mac; 1452 u32 rxcw; 1453 u32 ctrl; 1454 u32 status; 1455 s32 ret_val = E1000_SUCCESS; 1456 1457 DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1458 1459 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1460 status = E1000_READ_REG(hw, E1000_STATUS); 1461 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1462 1463 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1464 1465 /* Receiver is synchronized with no invalid bits. */ 1466 switch (mac->serdes_link_state) { 1467 case e1000_serdes_link_autoneg_complete: 1468 if (!(status & E1000_STATUS_LU)) { 1469 /* 1470 * We have lost link, retry autoneg before 1471 * reporting link failure 1472 */ 1473 mac->serdes_link_state = 1474 e1000_serdes_link_autoneg_progress; 1475 mac->serdes_has_link = FALSE; 1476 DEBUGOUT("AN_UP -> AN_PROG\n"); 1477 } 1478 break; 1479 1480 case e1000_serdes_link_forced_up: 1481 /* 1482 * If we are receiving /C/ ordered sets, re-enable 1483 * auto-negotiation in the TXCW register and disable 1484 * forced link in the Device Control register in an 1485 * attempt to auto-negotiate with our link partner. 1486 */ 1487 if (rxcw & E1000_RXCW_C) { 1488 /* Enable autoneg, and unforce link up */ 1489 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1490 E1000_WRITE_REG(hw, E1000_CTRL, 1491 (ctrl & ~E1000_CTRL_SLU)); 1492 mac->serdes_link_state = 1493 e1000_serdes_link_autoneg_progress; 1494 mac->serdes_has_link = FALSE; 1495 DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1496 } 1497 break; 1498 1499 case e1000_serdes_link_autoneg_progress: 1500 if (rxcw & E1000_RXCW_C) { 1501 /* 1502 * We received /C/ ordered sets, meaning the 1503 * link partner has autonegotiated, and we can 1504 * trust the Link Up (LU) status bit. 1505 */ 1506 if (status & E1000_STATUS_LU) { 1507 mac->serdes_link_state = 1508 e1000_serdes_link_autoneg_complete; 1509 DEBUGOUT("AN_PROG -> AN_UP\n"); 1510 mac->serdes_has_link = TRUE; 1511 } else { 1512 /* Autoneg completed, but failed. */ 1513 mac->serdes_link_state = 1514 e1000_serdes_link_down; 1515 DEBUGOUT("AN_PROG -> DOWN\n"); 1516 } 1517 } else { 1518 /* 1519 * The link partner did not autoneg. 1520 * Force link up and full duplex, and change 1521 * state to forced. 1522 */ 1523 E1000_WRITE_REG(hw, E1000_TXCW, 1524 (mac->txcw & ~E1000_TXCW_ANE)); 1525 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1526 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1527 1528 /* Configure Flow Control after link up. */ 1529 ret_val = 1530 e1000_config_fc_after_link_up_generic(hw); 1531 if (ret_val) { 1532 DEBUGOUT("Error config flow control\n"); 1533 break; 1534 } 1535 mac->serdes_link_state = 1536 e1000_serdes_link_forced_up; 1537 mac->serdes_has_link = TRUE; 1538 DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1539 } 1540 break; 1541 1542 case e1000_serdes_link_down: 1543 default: 1544 /* 1545 * The link was down but the receiver has now gained 1546 * valid sync, so lets see if we can bring the link 1547 * up. 1548 */ 1549 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1550 E1000_WRITE_REG(hw, E1000_CTRL, 1551 (ctrl & ~E1000_CTRL_SLU)); 1552 mac->serdes_link_state = 1553 e1000_serdes_link_autoneg_progress; 1554 DEBUGOUT("DOWN -> AN_PROG\n"); 1555 break; 1556 } 1557 } else { 1558 if (!(rxcw & E1000_RXCW_SYNCH)) { 1559 mac->serdes_has_link = FALSE; 1560 mac->serdes_link_state = e1000_serdes_link_down; 1561 DEBUGOUT("ANYSTATE -> DOWN\n"); 1562 } else { 1563 /* 1564 * We have sync, and can tolerate one invalid (IV) 1565 * codeword before declaring link down, so reread 1566 * to look again. 1567 */ 1568 usec_delay(10); 1569 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1570 if (rxcw & E1000_RXCW_IV) { 1571 mac->serdes_link_state = e1000_serdes_link_down; 1572 mac->serdes_has_link = FALSE; 1573 DEBUGOUT("ANYSTATE -> DOWN\n"); 1574 } 1575 } 1576 } 1577 1578 return ret_val; 1579 } 1580 1581 /** 1582 * e1000_valid_led_default_82571 - Verify a valid default LED config 1583 * @hw: pointer to the HW structure 1584 * @data: pointer to the NVM (EEPROM) 1585 * 1586 * Read the EEPROM for the current default LED configuration. If the 1587 * LED configuration is not valid, set to a valid LED configuration. 1588 **/ 1589 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1590 { 1591 s32 ret_val; 1592 1593 DEBUGFUNC("e1000_valid_led_default_82571"); 1594 1595 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1596 if (ret_val) { 1597 DEBUGOUT("NVM Read Error\n"); 1598 goto out; 1599 } 1600 1601 switch (hw->mac.type) { 1602 case e1000_82573: 1603 case e1000_82574: 1604 case e1000_82583: 1605 if (*data == ID_LED_RESERVED_F746) 1606 *data = ID_LED_DEFAULT_82573; 1607 break; 1608 default: 1609 if (*data == ID_LED_RESERVED_0000 || 1610 *data == ID_LED_RESERVED_FFFF) 1611 *data = ID_LED_DEFAULT; 1612 break; 1613 } 1614 1615 out: 1616 return ret_val; 1617 } 1618 1619 /** 1620 * e1000_get_laa_state_82571 - Get locally administered address state 1621 * @hw: pointer to the HW structure 1622 * 1623 * Retrieve and return the current locally administered address state. 1624 **/ 1625 bool e1000_get_laa_state_82571(struct e1000_hw *hw) 1626 { 1627 DEBUGFUNC("e1000_get_laa_state_82571"); 1628 1629 if (hw->mac.type != e1000_82571) 1630 return FALSE; 1631 1632 return hw->dev_spec._82571.laa_is_present; 1633 } 1634 1635 /** 1636 * e1000_set_laa_state_82571 - Set locally administered address state 1637 * @hw: pointer to the HW structure 1638 * @state: enable/disable locally administered address 1639 * 1640 * Enable/Disable the current locally administered address state. 1641 **/ 1642 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1643 { 1644 DEBUGFUNC("e1000_set_laa_state_82571"); 1645 1646 if (hw->mac.type != e1000_82571) 1647 return; 1648 1649 hw->dev_spec._82571.laa_is_present = state; 1650 1651 /* If workaround is activated... */ 1652 if (state) 1653 /* 1654 * Hold a copy of the LAA in RAR[14] This is done so that 1655 * between the time RAR[0] gets clobbered and the time it 1656 * gets fixed, the actual LAA is in one of the RARs and no 1657 * incoming packets directed to this port are dropped. 1658 * Eventually the LAA will be in RAR[0] and RAR[14]. 1659 */ 1660 e1000_rar_set_generic(hw, hw->mac.addr, 1661 hw->mac.rar_entry_count - 1); 1662 return; 1663 } 1664 1665 /** 1666 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1667 * @hw: pointer to the HW structure 1668 * 1669 * Verifies that the EEPROM has completed the update. After updating the 1670 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1671 * the checksum fix is not implemented, we need to set the bit and update 1672 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1673 * we need to return bad checksum. 1674 **/ 1675 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1676 { 1677 struct e1000_nvm_info *nvm = &hw->nvm; 1678 s32 ret_val = E1000_SUCCESS; 1679 u16 data; 1680 1681 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1682 1683 if (nvm->type != e1000_nvm_flash_hw) 1684 goto out; 1685 1686 /* 1687 * Check bit 4 of word 10h. If it is 0, firmware is done updating 1688 * 10h-12h. Checksum may need to be fixed. 1689 */ 1690 ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1691 if (ret_val) 1692 goto out; 1693 1694 if (!(data & 0x10)) { 1695 /* 1696 * Read 0x23 and check bit 15. This bit is a 1 1697 * when the checksum has already been fixed. If 1698 * the checksum is still wrong and this bit is a 1699 * 1, we need to return bad checksum. Otherwise, 1700 * we need to set this bit to a 1 and update the 1701 * checksum. 1702 */ 1703 ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1704 if (ret_val) 1705 goto out; 1706 1707 if (!(data & 0x8000)) { 1708 data |= 0x8000; 1709 ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1710 if (ret_val) 1711 goto out; 1712 ret_val = nvm->ops.update(hw); 1713 } 1714 } 1715 1716 out: 1717 return ret_val; 1718 } 1719 1720 1721 /** 1722 * e1000_read_mac_addr_82571 - Read device MAC address 1723 * @hw: pointer to the HW structure 1724 **/ 1725 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1726 { 1727 s32 ret_val = E1000_SUCCESS; 1728 1729 DEBUGFUNC("e1000_read_mac_addr_82571"); 1730 1731 /* 1732 * If there's an alternate MAC address place it in RAR0 1733 * so that it will override the Si installed default perm 1734 * address. 1735 */ 1736 ret_val = e1000_check_alt_mac_addr_generic(hw); 1737 if (ret_val) 1738 goto out; 1739 1740 ret_val = e1000_read_mac_addr_generic(hw); 1741 1742 out: 1743 return ret_val; 1744 } 1745 1746 /** 1747 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1748 * @hw: pointer to the HW structure 1749 * 1750 * In the case of a PHY power down to save power, or to turn off link during a 1751 * driver unload, or wake on lan is not enabled, remove the link. 1752 **/ 1753 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1754 { 1755 struct e1000_phy_info *phy = &hw->phy; 1756 struct e1000_mac_info *mac = &hw->mac; 1757 1758 if (!(phy->ops.check_reset_block)) 1759 return; 1760 1761 /* If the management interface is not enabled, then power down */ 1762 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1763 e1000_power_down_phy_copper(hw); 1764 1765 return; 1766 } 1767 1768 /** 1769 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1770 * @hw: pointer to the HW structure 1771 * 1772 * Clears the hardware counters by reading the counter registers. 1773 **/ 1774 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1775 { 1776 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1777 1778 e1000_clear_hw_cntrs_base_generic(hw); 1779 1780 E1000_READ_REG(hw, E1000_PRC64); 1781 E1000_READ_REG(hw, E1000_PRC127); 1782 E1000_READ_REG(hw, E1000_PRC255); 1783 E1000_READ_REG(hw, E1000_PRC511); 1784 E1000_READ_REG(hw, E1000_PRC1023); 1785 E1000_READ_REG(hw, E1000_PRC1522); 1786 E1000_READ_REG(hw, E1000_PTC64); 1787 E1000_READ_REG(hw, E1000_PTC127); 1788 E1000_READ_REG(hw, E1000_PTC255); 1789 E1000_READ_REG(hw, E1000_PTC511); 1790 E1000_READ_REG(hw, E1000_PTC1023); 1791 E1000_READ_REG(hw, E1000_PTC1522); 1792 1793 E1000_READ_REG(hw, E1000_ALGNERRC); 1794 E1000_READ_REG(hw, E1000_RXERRC); 1795 E1000_READ_REG(hw, E1000_TNCRS); 1796 E1000_READ_REG(hw, E1000_CEXTERR); 1797 E1000_READ_REG(hw, E1000_TSCTC); 1798 E1000_READ_REG(hw, E1000_TSCTFC); 1799 1800 E1000_READ_REG(hw, E1000_MGTPRC); 1801 E1000_READ_REG(hw, E1000_MGTPDC); 1802 E1000_READ_REG(hw, E1000_MGTPTC); 1803 1804 E1000_READ_REG(hw, E1000_IAC); 1805 E1000_READ_REG(hw, E1000_ICRXOC); 1806 1807 E1000_READ_REG(hw, E1000_ICRXPTC); 1808 E1000_READ_REG(hw, E1000_ICRXATC); 1809 E1000_READ_REG(hw, E1000_ICTXPTC); 1810 E1000_READ_REG(hw, E1000_ICTXATC); 1811 E1000_READ_REG(hw, E1000_ICTXQEC); 1812 E1000_READ_REG(hw, E1000_ICTXQMTC); 1813 E1000_READ_REG(hw, E1000_ICRXDMTC); 1814 } 1815