1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82543GC Gigabit Ethernet Controller (Fiber) 37 * 82543GC Gigabit Ethernet Controller (Copper) 38 * 82544EI Gigabit Ethernet Controller (Copper) 39 * 82544EI Gigabit Ethernet Controller (Fiber) 40 * 82544GC Gigabit Ethernet Controller (Copper) 41 * 82544GC Gigabit Ethernet Controller (LOM) 42 */ 43 44 #include "e1000_api.h" 45 46 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 47 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 48 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 49 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 50 u16 *data); 51 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 52 u16 data); 53 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 54 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 55 static s32 e1000_reset_hw_82543(struct e1000_hw *hw); 56 static s32 e1000_init_hw_82543(struct e1000_hw *hw); 57 static s32 e1000_setup_link_82543(struct e1000_hw *hw); 58 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 59 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 60 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 61 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 62 static s32 e1000_led_on_82543(struct e1000_hw *hw); 63 static s32 e1000_led_off_82543(struct e1000_hw *hw); 64 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 65 u32 value); 66 static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); 67 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 68 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 69 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 70 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 71 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 72 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 73 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 74 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 75 u16 count); 76 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 77 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 78 static s32 e1000_read_mac_addr_82543(struct e1000_hw *hw); 79 80 81 /** 82 * e1000_init_phy_params_82543 - Init PHY func ptrs. 83 * @hw: pointer to the HW structure 84 **/ 85 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 86 { 87 struct e1000_phy_info *phy = &hw->phy; 88 s32 ret_val = E1000_SUCCESS; 89 90 DEBUGFUNC("e1000_init_phy_params_82543"); 91 92 if (hw->phy.media_type != e1000_media_type_copper) { 93 phy->type = e1000_phy_none; 94 goto out; 95 } else { 96 phy->ops.power_up = e1000_power_up_phy_copper; 97 phy->ops.power_down = e1000_power_down_phy_copper; 98 } 99 100 phy->addr = 1; 101 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 102 phy->reset_delay_us = 10000; 103 phy->type = e1000_phy_m88; 104 105 /* Function Pointers */ 106 phy->ops.check_polarity = e1000_check_polarity_m88; 107 phy->ops.commit = e1000_phy_sw_reset_generic; 108 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543; 109 phy->ops.get_cable_length = e1000_get_cable_length_m88; 110 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 111 phy->ops.read_reg = (hw->mac.type == e1000_82543) 112 ? e1000_read_phy_reg_82543 113 : e1000_read_phy_reg_m88; 114 phy->ops.reset = (hw->mac.type == e1000_82543) 115 ? e1000_phy_hw_reset_82543 116 : e1000_phy_hw_reset_generic; 117 phy->ops.write_reg = (hw->mac.type == e1000_82543) 118 ? e1000_write_phy_reg_82543 119 : e1000_write_phy_reg_m88; 120 phy->ops.get_info = e1000_get_phy_info_m88; 121 122 /* 123 * The external PHY of the 82543 can be in a funky state. 124 * Resetting helps us read the PHY registers for acquiring 125 * the PHY ID. 126 */ 127 if (!e1000_init_phy_disabled_82543(hw)) { 128 ret_val = phy->ops.reset(hw); 129 if (ret_val) { 130 DEBUGOUT("Resetting PHY during init failed.\n"); 131 goto out; 132 } 133 msec_delay(20); 134 } 135 136 ret_val = e1000_get_phy_id(hw); 137 if (ret_val) 138 goto out; 139 140 /* Verify phy id */ 141 switch (hw->mac.type) { 142 case e1000_82543: 143 if (phy->id != M88E1000_E_PHY_ID) { 144 ret_val = -E1000_ERR_PHY; 145 goto out; 146 } 147 break; 148 case e1000_82544: 149 if (phy->id != M88E1000_I_PHY_ID) { 150 ret_val = -E1000_ERR_PHY; 151 goto out; 152 } 153 break; 154 default: 155 ret_val = -E1000_ERR_PHY; 156 goto out; 157 break; 158 } 159 160 out: 161 return ret_val; 162 } 163 164 /** 165 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 166 * @hw: pointer to the HW structure 167 **/ 168 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 169 { 170 struct e1000_nvm_info *nvm = &hw->nvm; 171 172 DEBUGFUNC("e1000_init_nvm_params_82543"); 173 174 nvm->type = e1000_nvm_eeprom_microwire; 175 nvm->word_size = 64; 176 nvm->delay_usec = 50; 177 nvm->address_bits = 6; 178 nvm->opcode_bits = 3; 179 180 /* Function Pointers */ 181 nvm->ops.read = e1000_read_nvm_microwire; 182 nvm->ops.update = e1000_update_nvm_checksum_generic; 183 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 184 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 185 nvm->ops.write = e1000_write_nvm_microwire; 186 187 return E1000_SUCCESS; 188 } 189 190 /** 191 * e1000_init_mac_params_82543 - Init MAC func ptrs. 192 * @hw: pointer to the HW structure 193 **/ 194 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 195 { 196 struct e1000_mac_info *mac = &hw->mac; 197 198 DEBUGFUNC("e1000_init_mac_params_82543"); 199 200 /* Set media type */ 201 switch (hw->device_id) { 202 case E1000_DEV_ID_82543GC_FIBER: 203 case E1000_DEV_ID_82544EI_FIBER: 204 hw->phy.media_type = e1000_media_type_fiber; 205 break; 206 default: 207 hw->phy.media_type = e1000_media_type_copper; 208 break; 209 } 210 211 /* Set mta register count */ 212 mac->mta_reg_count = 128; 213 /* Set rar entry count */ 214 mac->rar_entry_count = E1000_RAR_ENTRIES; 215 216 /* Function pointers */ 217 218 /* bus type/speed/width */ 219 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 220 /* function id */ 221 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 222 /* reset */ 223 mac->ops.reset_hw = e1000_reset_hw_82543; 224 /* hw initialization */ 225 mac->ops.init_hw = e1000_init_hw_82543; 226 /* link setup */ 227 mac->ops.setup_link = e1000_setup_link_82543; 228 /* physical interface setup */ 229 mac->ops.setup_physical_interface = 230 (hw->phy.media_type == e1000_media_type_copper) 231 ? e1000_setup_copper_link_82543 232 : e1000_setup_fiber_link_82543; 233 /* check for link */ 234 mac->ops.check_for_link = 235 (hw->phy.media_type == e1000_media_type_copper) 236 ? e1000_check_for_copper_link_82543 237 : e1000_check_for_fiber_link_82543; 238 /* link info */ 239 mac->ops.get_link_up_info = 240 (hw->phy.media_type == e1000_media_type_copper) 241 ? e1000_get_speed_and_duplex_copper_generic 242 : e1000_get_speed_and_duplex_fiber_serdes_generic; 243 /* multicast address update */ 244 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 245 /* writing VFTA */ 246 mac->ops.write_vfta = e1000_write_vfta_82543; 247 /* clearing VFTA */ 248 mac->ops.clear_vfta = e1000_clear_vfta_generic; 249 /* setting MTA */ 250 mac->ops.mta_set = e1000_mta_set_82543; 251 /* read mac address */ 252 mac->ops.read_mac_addr = e1000_read_mac_addr_82543; 253 /* turn on/off LED */ 254 mac->ops.led_on = e1000_led_on_82543; 255 mac->ops.led_off = e1000_led_off_82543; 256 /* clear hardware counters */ 257 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 258 259 /* Set tbi compatibility */ 260 if ((hw->mac.type != e1000_82543) || 261 (hw->phy.media_type == e1000_media_type_fiber)) 262 e1000_set_tbi_compatibility_82543(hw, FALSE); 263 264 return E1000_SUCCESS; 265 } 266 267 /** 268 * e1000_init_function_pointers_82543 - Init func ptrs. 269 * @hw: pointer to the HW structure 270 * 271 * Called to initialize all function pointers and parameters. 272 **/ 273 void e1000_init_function_pointers_82543(struct e1000_hw *hw) 274 { 275 DEBUGFUNC("e1000_init_function_pointers_82543"); 276 277 hw->mac.ops.init_params = e1000_init_mac_params_82543; 278 hw->nvm.ops.init_params = e1000_init_nvm_params_82543; 279 hw->phy.ops.init_params = e1000_init_phy_params_82543; 280 } 281 282 /** 283 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 284 * @hw: pointer to the HW structure 285 * 286 * Returns the current status of 10-bit Interface (TBI) compatibility 287 * (enabled/disabled). 288 **/ 289 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 290 { 291 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 292 bool state = FALSE; 293 294 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 295 296 if (hw->mac.type != e1000_82543) { 297 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 298 goto out; 299 } 300 301 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 302 ? TRUE : FALSE; 303 304 out: 305 return state; 306 } 307 308 /** 309 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 310 * @hw: pointer to the HW structure 311 * @state: enable/disable TBI compatibility 312 * 313 * Enables or disabled 10-bit Interface (TBI) compatibility. 314 **/ 315 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 316 { 317 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 318 319 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 320 321 if (hw->mac.type != e1000_82543) { 322 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 323 goto out; 324 } 325 326 if (state) 327 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 328 else 329 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 330 331 out: 332 return; 333 } 334 335 /** 336 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 337 * @hw: pointer to the HW structure 338 * 339 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) 340 * (enabled/disabled). 341 **/ 342 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 343 { 344 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 345 bool state = FALSE; 346 347 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 348 349 if (hw->mac.type != e1000_82543) { 350 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 351 goto out; 352 } 353 354 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 355 ? TRUE : FALSE; 356 357 out: 358 return state; 359 } 360 361 /** 362 * e1000_set_tbi_sbp_82543 - Set TBI SBP 363 * @hw: pointer to the HW structure 364 * @state: enable/disable TBI store bad packet 365 * 366 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 367 **/ 368 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 369 { 370 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 371 372 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 373 374 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 375 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 376 else 377 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 378 379 return; 380 } 381 382 /** 383 * e1000_init_phy_disabled_82543 - Returns init PHY status 384 * @hw: pointer to the HW structure 385 * 386 * Returns the current status of whether PHY initialization is disabled. 387 * True if PHY initialization is disabled else FALSE. 388 **/ 389 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 390 { 391 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 392 bool ret_val; 393 394 DEBUGFUNC("e1000_init_phy_disabled_82543"); 395 396 if (hw->mac.type != e1000_82543) { 397 ret_val = FALSE; 398 goto out; 399 } 400 401 ret_val = dev_spec->init_phy_disabled; 402 403 out: 404 return ret_val; 405 } 406 407 /** 408 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 409 * @hw: pointer to the HW structure 410 * @stats: Struct containing statistic register values 411 * @frame_len: The length of the frame in question 412 * @mac_addr: The Ethernet destination address of the frame in question 413 * @max_frame_size: The maximum frame size 414 * 415 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 416 **/ 417 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 418 struct e1000_hw_stats *stats, u32 frame_len, 419 u8 *mac_addr, u32 max_frame_size) 420 { 421 if (!(e1000_tbi_sbp_enabled_82543(hw))) 422 goto out; 423 424 /* First adjust the frame length. */ 425 frame_len--; 426 /* 427 * We need to adjust the statistics counters, since the hardware 428 * counters overcount this packet as a CRC error and undercount 429 * the packet as a good packet 430 */ 431 /* This packet should not be counted as a CRC error. */ 432 stats->crcerrs--; 433 /* This packet does count as a Good Packet Received. */ 434 stats->gprc++; 435 436 /* Adjust the Good Octets received counters */ 437 stats->gorc += frame_len; 438 439 /* 440 * Is this a broadcast or multicast? Check broadcast first, 441 * since the test for a multicast frame will test positive on 442 * a broadcast frame. 443 */ 444 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 445 /* Broadcast packet */ 446 stats->bprc++; 447 else if (*mac_addr & 0x01) 448 /* Multicast packet */ 449 stats->mprc++; 450 451 /* 452 * In this case, the hardware has overcounted the number of 453 * oversize frames. 454 */ 455 if ((frame_len == max_frame_size) && (stats->roc > 0)) 456 stats->roc--; 457 458 /* 459 * Adjust the bin counters when the extra byte put the frame in the 460 * wrong bin. Remember that the frame_len was adjusted above. 461 */ 462 if (frame_len == 64) { 463 stats->prc64++; 464 stats->prc127--; 465 } else if (frame_len == 127) { 466 stats->prc127++; 467 stats->prc255--; 468 } else if (frame_len == 255) { 469 stats->prc255++; 470 stats->prc511--; 471 } else if (frame_len == 511) { 472 stats->prc511++; 473 stats->prc1023--; 474 } else if (frame_len == 1023) { 475 stats->prc1023++; 476 stats->prc1522--; 477 } else if (frame_len == 1522) { 478 stats->prc1522++; 479 } 480 481 out: 482 return; 483 } 484 485 /** 486 * e1000_read_phy_reg_82543 - Read PHY register 487 * @hw: pointer to the HW structure 488 * @offset: register offset to be read 489 * @data: pointer to the read data 490 * 491 * Reads the PHY at offset and stores the information read to data. 492 **/ 493 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 494 { 495 u32 mdic; 496 s32 ret_val = E1000_SUCCESS; 497 498 DEBUGFUNC("e1000_read_phy_reg_82543"); 499 500 if (offset > MAX_PHY_REG_ADDRESS) { 501 DEBUGOUT1("PHY Address %d is out of range\n", offset); 502 ret_val = -E1000_ERR_PARAM; 503 goto out; 504 } 505 506 /* 507 * We must first send a preamble through the MDIO pin to signal the 508 * beginning of an MII instruction. This is done by sending 32 509 * consecutive "1" bits. 510 */ 511 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 512 513 /* 514 * Now combine the next few fields that are required for a read 515 * operation. We use this method instead of calling the 516 * e1000_shift_out_mdi_bits routine five different times. The format 517 * of an MII read instruction consists of a shift out of 14 bits and 518 * is defined as follows: 519 * <Preamble><SOF><Op Code><Phy Addr><Offset> 520 * followed by a shift in of 18 bits. This first two bits shifted in 521 * are TurnAround bits used to avoid contention on the MDIO pin when a 522 * READ operation is performed. These two bits are thrown away 523 * followed by a shift in of 16 bits which contains the desired data. 524 */ 525 mdic = (offset | (hw->phy.addr << 5) | 526 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 527 528 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 529 530 /* 531 * Now that we've shifted out the read command to the MII, we need to 532 * "shift in" the 16-bit value (18 total bits) of the requested PHY 533 * register address. 534 */ 535 *data = e1000_shift_in_mdi_bits_82543(hw); 536 537 out: 538 return ret_val; 539 } 540 541 /** 542 * e1000_write_phy_reg_82543 - Write PHY register 543 * @hw: pointer to the HW structure 544 * @offset: register offset to be written 545 * @data: pointer to the data to be written at offset 546 * 547 * Writes data to the PHY at offset. 548 **/ 549 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 550 { 551 u32 mdic; 552 s32 ret_val = E1000_SUCCESS; 553 554 DEBUGFUNC("e1000_write_phy_reg_82543"); 555 556 if (offset > MAX_PHY_REG_ADDRESS) { 557 DEBUGOUT1("PHY Address %d is out of range\n", offset); 558 ret_val = -E1000_ERR_PARAM; 559 goto out; 560 } 561 562 /* 563 * We'll need to use the SW defined pins to shift the write command 564 * out to the PHY. We first send a preamble to the PHY to signal the 565 * beginning of the MII instruction. This is done by sending 32 566 * consecutive "1" bits. 567 */ 568 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 569 570 /* 571 * Now combine the remaining required fields that will indicate a 572 * write operation. We use this method instead of calling the 573 * e1000_shift_out_mdi_bits routine for each field in the command. The 574 * format of a MII write instruction is as follows: 575 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 576 */ 577 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 578 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 579 mdic <<= 16; 580 mdic |= (u32) data; 581 582 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 583 584 out: 585 return ret_val; 586 } 587 588 /** 589 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 590 * @hw: pointer to the HW structure 591 * @ctrl: pointer to the control register 592 * 593 * Raise the management data input clock by setting the MDC bit in the control 594 * register. 595 **/ 596 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 597 { 598 /* 599 * Raise the clock input to the Management Data Clock (by setting the 600 * MDC bit), and then delay a sufficient amount of time. 601 */ 602 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 603 E1000_WRITE_FLUSH(hw); 604 usec_delay(10); 605 } 606 607 /** 608 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 609 * @hw: pointer to the HW structure 610 * @ctrl: pointer to the control register 611 * 612 * Lower the management data input clock by clearing the MDC bit in the 613 * control register. 614 **/ 615 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 616 { 617 /* 618 * Lower the clock input to the Management Data Clock (by clearing the 619 * MDC bit), and then delay a sufficient amount of time. 620 */ 621 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 622 E1000_WRITE_FLUSH(hw); 623 usec_delay(10); 624 } 625 626 /** 627 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 628 * @hw: pointer to the HW structure 629 * @data: data to send to the PHY 630 * @count: number of bits to shift out 631 * 632 * We need to shift 'count' bits out to the PHY. So, the value in the 633 * "data" parameter will be shifted out to the PHY one bit at a time. 634 * In order to do this, "data" must be broken down into bits. 635 **/ 636 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 637 u16 count) 638 { 639 u32 ctrl, mask; 640 641 /* 642 * We need to shift "count" number of bits out to the PHY. So, the 643 * value in the "data" parameter will be shifted out to the PHY one 644 * bit at a time. In order to do this, "data" must be broken down 645 * into bits. 646 */ 647 mask = 0x01; 648 mask <<= (count -1); 649 650 ctrl = E1000_READ_REG(hw, E1000_CTRL); 651 652 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 653 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 654 655 while (mask) { 656 /* 657 * A "1" is shifted out to the PHY by setting the MDIO bit to 658 * "1" and then raising and lowering the Management Data Clock. 659 * A "0" is shifted out to the PHY by setting the MDIO bit to 660 * "0" and then raising and lowering the clock. 661 */ 662 if (data & mask) ctrl |= E1000_CTRL_MDIO; 663 else ctrl &= ~E1000_CTRL_MDIO; 664 665 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 666 E1000_WRITE_FLUSH(hw); 667 668 usec_delay(10); 669 670 e1000_raise_mdi_clk_82543(hw, &ctrl); 671 e1000_lower_mdi_clk_82543(hw, &ctrl); 672 673 mask >>= 1; 674 } 675 } 676 677 /** 678 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 679 * @hw: pointer to the HW structure 680 * 681 * In order to read a register from the PHY, we need to shift 18 bits 682 * in from the PHY. Bits are "shifted in" by raising the clock input to 683 * the PHY (setting the MDC bit), and then reading the value of the data out 684 * MDIO bit. 685 **/ 686 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 687 { 688 u32 ctrl; 689 u16 data = 0; 690 u8 i; 691 692 /* 693 * In order to read a register from the PHY, we need to shift in a 694 * total of 18 bits from the PHY. The first two bit (turnaround) 695 * times are used to avoid contention on the MDIO pin when a read 696 * operation is performed. These two bits are ignored by us and 697 * thrown away. Bits are "shifted in" by raising the input to the 698 * Management Data Clock (setting the MDC bit) and then reading the 699 * value of the MDIO bit. 700 */ 701 ctrl = E1000_READ_REG(hw, E1000_CTRL); 702 703 /* 704 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 705 * input. 706 */ 707 ctrl &= ~E1000_CTRL_MDIO_DIR; 708 ctrl &= ~E1000_CTRL_MDIO; 709 710 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 711 E1000_WRITE_FLUSH(hw); 712 713 /* 714 * Raise and lower the clock before reading in the data. This accounts 715 * for the turnaround bits. The first clock occurred when we clocked 716 * out the last bit of the Register Address. 717 */ 718 e1000_raise_mdi_clk_82543(hw, &ctrl); 719 e1000_lower_mdi_clk_82543(hw, &ctrl); 720 721 for (data = 0, i = 0; i < 16; i++) { 722 data <<= 1; 723 e1000_raise_mdi_clk_82543(hw, &ctrl); 724 ctrl = E1000_READ_REG(hw, E1000_CTRL); 725 /* Check to see if we shifted in a "1". */ 726 if (ctrl & E1000_CTRL_MDIO) 727 data |= 1; 728 e1000_lower_mdi_clk_82543(hw, &ctrl); 729 } 730 731 e1000_raise_mdi_clk_82543(hw, &ctrl); 732 e1000_lower_mdi_clk_82543(hw, &ctrl); 733 734 return data; 735 } 736 737 /** 738 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 739 * @hw: pointer to the HW structure 740 * 741 * Calls the function to force speed and duplex for the m88 PHY, and 742 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 743 * then call the function for polarity reversal workaround. 744 **/ 745 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 746 { 747 s32 ret_val; 748 749 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 750 751 ret_val = e1000_phy_force_speed_duplex_m88(hw); 752 if (ret_val) 753 goto out; 754 755 if (!hw->mac.autoneg && 756 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 757 ret_val = e1000_polarity_reversal_workaround_82543(hw); 758 759 out: 760 return ret_val; 761 } 762 763 /** 764 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 765 * @hw: pointer to the HW structure 766 * 767 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 768 * inadvertently. To workaround the issue, we disable the transmitter on 769 * the PHY until we have established the link partner's link parameters. 770 **/ 771 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 772 { 773 s32 ret_val = E1000_SUCCESS; 774 u16 mii_status_reg; 775 u16 i; 776 bool link; 777 778 if (!(hw->phy.ops.write_reg)) 779 goto out; 780 781 /* Polarity reversal workaround for forced 10F/10H links. */ 782 783 /* Disable the transmitter on the PHY */ 784 785 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 786 if (ret_val) 787 goto out; 788 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 789 if (ret_val) 790 goto out; 791 792 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 793 if (ret_val) 794 goto out; 795 796 /* 797 * This loop will early-out if the NO link condition has been met. 798 * In other words, DO NOT use e1000_phy_has_link_generic() here. 799 */ 800 for (i = PHY_FORCE_TIME; i > 0; i--) { 801 /* 802 * Read the MII Status Register and wait for Link Status bit 803 * to be clear. 804 */ 805 806 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 807 if (ret_val) 808 goto out; 809 810 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 811 if (ret_val) 812 goto out; 813 814 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 815 break; 816 msec_delay_irq(100); 817 } 818 819 /* Recommended delay time after link has been lost */ 820 msec_delay_irq(1000); 821 822 /* Now we will re-enable the transmitter on the PHY */ 823 824 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 825 if (ret_val) 826 goto out; 827 msec_delay_irq(50); 828 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 829 if (ret_val) 830 goto out; 831 msec_delay_irq(50); 832 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 833 if (ret_val) 834 goto out; 835 msec_delay_irq(50); 836 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 837 if (ret_val) 838 goto out; 839 840 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 841 if (ret_val) 842 goto out; 843 844 /* 845 * Read the MII Status Register and wait for Link Status bit 846 * to be set. 847 */ 848 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 849 if (ret_val) 850 goto out; 851 852 out: 853 return ret_val; 854 } 855 856 /** 857 * e1000_phy_hw_reset_82543 - PHY hardware reset 858 * @hw: pointer to the HW structure 859 * 860 * Sets the PHY_RESET_DIR bit in the extended device control register 861 * to put the PHY into a reset and waits for completion. Once the reset 862 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 863 * of reset. 864 **/ 865 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 866 { 867 u32 ctrl_ext; 868 s32 ret_val; 869 870 DEBUGFUNC("e1000_phy_hw_reset_82543"); 871 872 /* 873 * Read the Extended Device Control Register, assert the PHY_RESET_DIR 874 * bit to put the PHY into reset... 875 */ 876 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 877 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 878 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 879 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 880 E1000_WRITE_FLUSH(hw); 881 882 msec_delay(10); 883 884 /* ...then take it out of reset. */ 885 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 886 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 887 E1000_WRITE_FLUSH(hw); 888 889 usec_delay(150); 890 891 if (!(hw->phy.ops.get_cfg_done)) 892 return E1000_SUCCESS; 893 894 ret_val = hw->phy.ops.get_cfg_done(hw); 895 896 return ret_val; 897 } 898 899 /** 900 * e1000_reset_hw_82543 - Reset hardware 901 * @hw: pointer to the HW structure 902 * 903 * This resets the hardware into a known state. 904 **/ 905 static s32 e1000_reset_hw_82543(struct e1000_hw *hw) 906 { 907 u32 ctrl, icr; 908 s32 ret_val = E1000_SUCCESS; 909 910 DEBUGFUNC("e1000_reset_hw_82543"); 911 912 DEBUGOUT("Masking off all interrupts\n"); 913 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 914 915 E1000_WRITE_REG(hw, E1000_RCTL, 0); 916 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 917 E1000_WRITE_FLUSH(hw); 918 919 e1000_set_tbi_sbp_82543(hw, FALSE); 920 921 /* 922 * Delay to allow any outstanding PCI transactions to complete before 923 * resetting the device 924 */ 925 msec_delay(10); 926 927 ctrl = E1000_READ_REG(hw, E1000_CTRL); 928 929 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 930 if (hw->mac.type == e1000_82543) { 931 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 932 } else { 933 /* 934 * The 82544 can't ACK the 64-bit write when issuing the 935 * reset, so use IO-mapping as a workaround. 936 */ 937 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 938 } 939 940 /* 941 * After MAC reset, force reload of NVM to restore power-on 942 * settings to device. 943 */ 944 hw->nvm.ops.reload(hw); 945 msec_delay(2); 946 947 /* Masking off and clearing any pending interrupts */ 948 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 949 icr = E1000_READ_REG(hw, E1000_ICR); 950 951 return ret_val; 952 } 953 954 /** 955 * e1000_init_hw_82543 - Initialize hardware 956 * @hw: pointer to the HW structure 957 * 958 * This inits the hardware readying it for operation. 959 **/ 960 static s32 e1000_init_hw_82543(struct e1000_hw *hw) 961 { 962 struct e1000_mac_info *mac = &hw->mac; 963 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 964 u32 ctrl; 965 s32 ret_val; 966 u16 i; 967 968 DEBUGFUNC("e1000_init_hw_82543"); 969 970 /* Disabling VLAN filtering */ 971 E1000_WRITE_REG(hw, E1000_VET, 0); 972 mac->ops.clear_vfta(hw); 973 974 /* Setup the receive address. */ 975 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 976 977 /* Zero out the Multicast HASH table */ 978 DEBUGOUT("Zeroing the MTA\n"); 979 for (i = 0; i < mac->mta_reg_count; i++) { 980 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 981 E1000_WRITE_FLUSH(hw); 982 } 983 984 /* 985 * Set the PCI priority bit correctly in the CTRL register. This 986 * determines if the adapter gives priority to receives, or if it 987 * gives equal priority to transmits and receives. 988 */ 989 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 990 ctrl = E1000_READ_REG(hw, E1000_CTRL); 991 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 992 } 993 994 e1000_pcix_mmrbc_workaround_generic(hw); 995 996 /* Setup link and flow control */ 997 ret_val = mac->ops.setup_link(hw); 998 999 /* 1000 * Clear all of the statistics registers (clear on read). It is 1001 * important that we do this after we have tried to establish link 1002 * because the symbol error count will increment wildly if there 1003 * is no link. 1004 */ 1005 e1000_clear_hw_cntrs_82543(hw); 1006 1007 return ret_val; 1008 } 1009 1010 /** 1011 * e1000_setup_link_82543 - Setup flow control and link settings 1012 * @hw: pointer to the HW structure 1013 * 1014 * Read the EEPROM to determine the initial polarity value and write the 1015 * extended device control register with the information before calling 1016 * the generic setup link function, which does the following: 1017 * Determines which flow control settings to use, then configures flow 1018 * control. Calls the appropriate media-specific link configuration 1019 * function. Assuming the adapter has a valid link partner, a valid link 1020 * should be established. Assumes the hardware has previously been reset 1021 * and the transmitter and receiver are not enabled. 1022 **/ 1023 static s32 e1000_setup_link_82543(struct e1000_hw *hw) 1024 { 1025 u32 ctrl_ext; 1026 s32 ret_val; 1027 u16 data; 1028 1029 DEBUGFUNC("e1000_setup_link_82543"); 1030 1031 /* 1032 * Take the 4 bits from NVM word 0xF that determine the initial 1033 * polarity value for the SW controlled pins, and setup the 1034 * Extended Device Control reg with that info. 1035 * This is needed because one of the SW controlled pins is used for 1036 * signal detection. So this should be done before phy setup. 1037 */ 1038 if (hw->mac.type == e1000_82543) { 1039 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1040 if (ret_val) { 1041 DEBUGOUT("NVM Read Error\n"); 1042 ret_val = -E1000_ERR_NVM; 1043 goto out; 1044 } 1045 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1046 NVM_SWDPIO_EXT_SHIFT); 1047 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1048 } 1049 1050 ret_val = e1000_setup_link_generic(hw); 1051 1052 out: 1053 return ret_val; 1054 } 1055 1056 /** 1057 * e1000_setup_copper_link_82543 - Configure copper link settings 1058 * @hw: pointer to the HW structure 1059 * 1060 * Configures the link for auto-neg or forced speed and duplex. Then we check 1061 * for link, once link is established calls to configure collision distance 1062 * and flow control are called. 1063 **/ 1064 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1065 { 1066 u32 ctrl; 1067 s32 ret_val; 1068 bool link; 1069 1070 DEBUGFUNC("e1000_setup_copper_link_82543"); 1071 1072 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1073 /* 1074 * With 82543, we need to force speed and duplex on the MAC 1075 * equal to what the PHY speed and duplex configuration is. 1076 * In addition, we need to perform a hardware reset on the 1077 * PHY to take it out of reset. 1078 */ 1079 if (hw->mac.type == e1000_82543) { 1080 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1081 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1082 ret_val = hw->phy.ops.reset(hw); 1083 if (ret_val) 1084 goto out; 1085 hw->phy.reset_disable = FALSE; 1086 } else { 1087 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1088 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1089 } 1090 1091 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1092 ret_val = e1000_copper_link_setup_m88(hw); 1093 if (ret_val) 1094 goto out; 1095 1096 if (hw->mac.autoneg) { 1097 /* 1098 * Setup autoneg and flow control advertisement and perform 1099 * autonegotiation. 1100 */ 1101 ret_val = e1000_copper_link_autoneg(hw); 1102 if (ret_val) 1103 goto out; 1104 } else { 1105 /* 1106 * PHY will be set to 10H, 10F, 100H or 100F 1107 * depending on user settings. 1108 */ 1109 DEBUGOUT("Forcing Speed and Duplex\n"); 1110 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1111 if (ret_val) { 1112 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1113 goto out; 1114 } 1115 } 1116 1117 /* 1118 * Check link status. Wait up to 100 microseconds for link to become 1119 * valid. 1120 */ 1121 ret_val = e1000_phy_has_link_generic(hw, 1122 COPPER_LINK_UP_LIMIT, 1123 10, 1124 &link); 1125 if (ret_val) 1126 goto out; 1127 1128 1129 if (link) { 1130 DEBUGOUT("Valid link established!!!\n"); 1131 /* Config the MAC and PHY after link is up */ 1132 if (hw->mac.type == e1000_82544) { 1133 e1000_config_collision_dist_generic(hw); 1134 } else { 1135 ret_val = e1000_config_mac_to_phy_82543(hw); 1136 if (ret_val) 1137 goto out; 1138 } 1139 ret_val = e1000_config_fc_after_link_up_generic(hw); 1140 } else { 1141 DEBUGOUT("Unable to establish link!!!\n"); 1142 } 1143 1144 out: 1145 return ret_val; 1146 } 1147 1148 /** 1149 * e1000_setup_fiber_link_82543 - Setup link for fiber 1150 * @hw: pointer to the HW structure 1151 * 1152 * Configures collision distance and flow control for fiber links. Upon 1153 * successful setup, poll for link. 1154 **/ 1155 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1156 { 1157 u32 ctrl; 1158 s32 ret_val; 1159 1160 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1161 1162 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1163 1164 /* Take the link out of reset */ 1165 ctrl &= ~E1000_CTRL_LRST; 1166 1167 e1000_config_collision_dist_generic(hw); 1168 1169 ret_val = e1000_commit_fc_settings_generic(hw); 1170 if (ret_val) 1171 goto out; 1172 1173 DEBUGOUT("Auto-negotiation enabled\n"); 1174 1175 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1176 E1000_WRITE_FLUSH(hw); 1177 msec_delay(1); 1178 1179 /* 1180 * For these adapters, the SW definable pin 1 is cleared when the 1181 * optics detect a signal. If we have a signal, then poll for a 1182 * "Link-Up" indication. 1183 */ 1184 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1185 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1186 } else { 1187 DEBUGOUT("No signal detected\n"); 1188 } 1189 1190 out: 1191 return ret_val; 1192 } 1193 1194 /** 1195 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1196 * @hw: pointer to the HW structure 1197 * 1198 * Checks the phy for link, if link exists, do the following: 1199 * - check for downshift 1200 * - do polarity workaround (if necessary) 1201 * - configure collision distance 1202 * - configure flow control after link up 1203 * - configure tbi compatibility 1204 **/ 1205 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1206 { 1207 struct e1000_mac_info *mac = &hw->mac; 1208 u32 icr, rctl; 1209 s32 ret_val; 1210 u16 speed, duplex; 1211 bool link; 1212 1213 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1214 1215 if (!mac->get_link_status) { 1216 ret_val = E1000_SUCCESS; 1217 goto out; 1218 } 1219 1220 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1221 if (ret_val) 1222 goto out; 1223 1224 if (!link) 1225 goto out; /* No link detected */ 1226 1227 mac->get_link_status = FALSE; 1228 1229 e1000_check_downshift_generic(hw); 1230 1231 /* 1232 * If we are forcing speed/duplex, then we can return since 1233 * we have already determined whether we have link or not. 1234 */ 1235 if (!mac->autoneg) { 1236 /* 1237 * If speed and duplex are forced to 10H or 10F, then we will 1238 * implement the polarity reversal workaround. We disable 1239 * interrupts first, and upon returning, place the devices 1240 * interrupt state to its previous value except for the link 1241 * status change interrupt which will happened due to the 1242 * execution of this workaround. 1243 */ 1244 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1245 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1246 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1247 icr = E1000_READ_REG(hw, E1000_ICR); 1248 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1249 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1250 } 1251 1252 ret_val = -E1000_ERR_CONFIG; 1253 goto out; 1254 } 1255 1256 /* 1257 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1258 * have Si on board that is 82544 or newer, Auto 1259 * Speed Detection takes care of MAC speed/duplex 1260 * configuration. So we only need to configure Collision 1261 * Distance in the MAC. Otherwise, we need to force 1262 * speed/duplex on the MAC to the current PHY speed/duplex 1263 * settings. 1264 */ 1265 if (mac->type == e1000_82544) 1266 e1000_config_collision_dist_generic(hw); 1267 else { 1268 ret_val = e1000_config_mac_to_phy_82543(hw); 1269 if (ret_val) { 1270 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1271 goto out; 1272 } 1273 } 1274 1275 /* 1276 * Configure Flow Control now that Auto-Neg has completed. 1277 * First, we need to restore the desired flow control 1278 * settings because we may have had to re-autoneg with a 1279 * different link partner. 1280 */ 1281 ret_val = e1000_config_fc_after_link_up_generic(hw); 1282 if (ret_val) { 1283 DEBUGOUT("Error configuring flow control\n"); 1284 } 1285 1286 /* 1287 * At this point we know that we are on copper and we have 1288 * auto-negotiated link. These are conditions for checking the link 1289 * partner capability register. We use the link speed to determine if 1290 * TBI compatibility needs to be turned on or off. If the link is not 1291 * at gigabit speed, then TBI compatibility is not needed. If we are 1292 * at gigabit speed, we turn on TBI compatibility. 1293 */ 1294 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1295 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1296 if (ret_val) { 1297 DEBUGOUT("Error getting link speed and duplex\n"); 1298 return ret_val; 1299 } 1300 if (speed != SPEED_1000) { 1301 /* 1302 * If link speed is not set to gigabit speed, 1303 * we do not need to enable TBI compatibility. 1304 */ 1305 if (e1000_tbi_sbp_enabled_82543(hw)) { 1306 /* 1307 * If we previously were in the mode, 1308 * turn it off. 1309 */ 1310 e1000_set_tbi_sbp_82543(hw, FALSE); 1311 rctl = E1000_READ_REG(hw, E1000_RCTL); 1312 rctl &= ~E1000_RCTL_SBP; 1313 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1314 } 1315 } else { 1316 /* 1317 * If TBI compatibility is was previously off, 1318 * turn it on. For compatibility with a TBI link 1319 * partner, we will store bad packets. Some 1320 * frames have an additional byte on the end and 1321 * will look like CRC errors to to the hardware. 1322 */ 1323 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1324 e1000_set_tbi_sbp_82543(hw, TRUE); 1325 rctl = E1000_READ_REG(hw, E1000_RCTL); 1326 rctl |= E1000_RCTL_SBP; 1327 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1328 } 1329 } 1330 } 1331 out: 1332 return ret_val; 1333 } 1334 1335 /** 1336 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1337 * @hw: pointer to the HW structure 1338 * 1339 * Checks for link up on the hardware. If link is not up and we have 1340 * a signal, then we need to force link up. 1341 **/ 1342 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1343 { 1344 struct e1000_mac_info *mac = &hw->mac; 1345 u32 rxcw, ctrl, status; 1346 s32 ret_val = E1000_SUCCESS; 1347 1348 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1349 1350 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1351 status = E1000_READ_REG(hw, E1000_STATUS); 1352 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1353 1354 /* 1355 * If we don't have link (auto-negotiation failed or link partner 1356 * cannot auto-negotiate), the cable is plugged in (we have signal), 1357 * and our link partner is not trying to auto-negotiate with us (we 1358 * are receiving idles or data), we need to force link up. We also 1359 * need to give auto-negotiation time to complete, in case the cable 1360 * was just plugged in. The autoneg_failed flag does this. 1361 */ 1362 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1363 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1364 (!(status & E1000_STATUS_LU)) && 1365 (!(rxcw & E1000_RXCW_C))) { 1366 if (mac->autoneg_failed == 0) { 1367 mac->autoneg_failed = 1; 1368 ret_val = 0; 1369 goto out; 1370 } 1371 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1372 1373 /* Disable auto-negotiation in the TXCW register */ 1374 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1375 1376 /* Force link-up and also force full-duplex. */ 1377 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1378 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1379 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1380 1381 /* Configure Flow Control after forcing link up. */ 1382 ret_val = e1000_config_fc_after_link_up_generic(hw); 1383 if (ret_val) { 1384 DEBUGOUT("Error configuring flow control\n"); 1385 goto out; 1386 } 1387 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1388 /* 1389 * If we are forcing link and we are receiving /C/ ordered 1390 * sets, re-enable auto-negotiation in the TXCW register 1391 * and disable forced link in the Device Control register 1392 * in an attempt to auto-negotiate with our link partner. 1393 */ 1394 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1395 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1396 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1397 1398 mac->serdes_has_link = TRUE; 1399 } 1400 1401 out: 1402 return ret_val; 1403 } 1404 1405 /** 1406 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1407 * @hw: pointer to the HW structure 1408 * 1409 * For the 82543 silicon, we need to set the MAC to match the settings 1410 * of the PHY, even if the PHY is auto-negotiating. 1411 **/ 1412 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1413 { 1414 u32 ctrl; 1415 s32 ret_val = E1000_SUCCESS; 1416 u16 phy_data; 1417 1418 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1419 1420 if (!(hw->phy.ops.read_reg)) 1421 goto out; 1422 1423 /* Set the bits to force speed and duplex */ 1424 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1425 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1426 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1427 1428 /* 1429 * Set up duplex in the Device Control and Transmit Control 1430 * registers depending on negotiated values. 1431 */ 1432 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1433 if (ret_val) 1434 goto out; 1435 1436 ctrl &= ~E1000_CTRL_FD; 1437 if (phy_data & M88E1000_PSSR_DPLX) 1438 ctrl |= E1000_CTRL_FD; 1439 1440 e1000_config_collision_dist_generic(hw); 1441 1442 /* 1443 * Set up speed in the Device Control register depending on 1444 * negotiated values. 1445 */ 1446 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1447 ctrl |= E1000_CTRL_SPD_1000; 1448 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1449 ctrl |= E1000_CTRL_SPD_100; 1450 1451 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1452 1453 out: 1454 return ret_val; 1455 } 1456 1457 /** 1458 * e1000_write_vfta_82543 - Write value to VLAN filter table 1459 * @hw: pointer to the HW structure 1460 * @offset: the 32-bit offset in which to write the value to. 1461 * @value: the 32-bit value to write at location offset. 1462 * 1463 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1464 * table. 1465 **/ 1466 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1467 { 1468 u32 temp; 1469 1470 DEBUGFUNC("e1000_write_vfta_82543"); 1471 1472 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1473 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1474 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1475 E1000_WRITE_FLUSH(hw); 1476 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1477 E1000_WRITE_FLUSH(hw); 1478 } else { 1479 e1000_write_vfta_generic(hw, offset, value); 1480 } 1481 } 1482 1483 /** 1484 * e1000_mta_set_82543 - Set multicast filter table address 1485 * @hw: pointer to the HW structure 1486 * @hash_value: determines the MTA register and bit to set 1487 * 1488 * The multicast table address is a register array of 32-bit registers. 1489 * The hash_value is used to determine what register the bit is in, the 1490 * current value is read, the new bit is OR'd in and the new value is 1491 * written back into the register. 1492 **/ 1493 static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) 1494 { 1495 u32 hash_bit, hash_reg, mta, temp; 1496 1497 DEBUGFUNC("e1000_mta_set_82543"); 1498 1499 hash_reg = (hash_value >> 5); 1500 1501 /* 1502 * If we are on an 82544 and we are trying to write an odd offset 1503 * in the MTA, save off the previous entry before writing and 1504 * restore the old value after writing. 1505 */ 1506 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 1507 hash_reg &= (hw->mac.mta_reg_count - 1); 1508 hash_bit = hash_value & 0x1F; 1509 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 1510 mta |= (1 << hash_bit); 1511 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 1512 1513 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 1514 E1000_WRITE_FLUSH(hw); 1515 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 1516 E1000_WRITE_FLUSH(hw); 1517 } else { 1518 e1000_mta_set_generic(hw, hash_value); 1519 } 1520 } 1521 1522 /** 1523 * e1000_led_on_82543 - Turn on SW controllable LED 1524 * @hw: pointer to the HW structure 1525 * 1526 * Turns the SW defined LED on. 1527 **/ 1528 static s32 e1000_led_on_82543(struct e1000_hw *hw) 1529 { 1530 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1531 1532 DEBUGFUNC("e1000_led_on_82543"); 1533 1534 if (hw->mac.type == e1000_82544 && 1535 hw->phy.media_type == e1000_media_type_copper) { 1536 /* Clear SW-definable Pin 0 to turn on the LED */ 1537 ctrl &= ~E1000_CTRL_SWDPIN0; 1538 ctrl |= E1000_CTRL_SWDPIO0; 1539 } else { 1540 /* Fiber 82544 and all 82543 use this method */ 1541 ctrl |= E1000_CTRL_SWDPIN0; 1542 ctrl |= E1000_CTRL_SWDPIO0; 1543 } 1544 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1545 1546 return E1000_SUCCESS; 1547 } 1548 1549 /** 1550 * e1000_led_off_82543 - Turn off SW controllable LED 1551 * @hw: pointer to the HW structure 1552 * 1553 * Turns the SW defined LED off. 1554 **/ 1555 static s32 e1000_led_off_82543(struct e1000_hw *hw) 1556 { 1557 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1558 1559 DEBUGFUNC("e1000_led_off_82543"); 1560 1561 if (hw->mac.type == e1000_82544 && 1562 hw->phy.media_type == e1000_media_type_copper) { 1563 /* Set SW-definable Pin 0 to turn off the LED */ 1564 ctrl |= E1000_CTRL_SWDPIN0; 1565 ctrl |= E1000_CTRL_SWDPIO0; 1566 } else { 1567 ctrl &= ~E1000_CTRL_SWDPIN0; 1568 ctrl |= E1000_CTRL_SWDPIO0; 1569 } 1570 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1571 1572 return E1000_SUCCESS; 1573 } 1574 1575 /** 1576 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1577 * @hw: pointer to the HW structure 1578 * 1579 * Clears the hardware counters by reading the counter registers. 1580 **/ 1581 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1582 { 1583 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1584 1585 e1000_clear_hw_cntrs_base_generic(hw); 1586 1587 E1000_READ_REG(hw, E1000_PRC64); 1588 E1000_READ_REG(hw, E1000_PRC127); 1589 E1000_READ_REG(hw, E1000_PRC255); 1590 E1000_READ_REG(hw, E1000_PRC511); 1591 E1000_READ_REG(hw, E1000_PRC1023); 1592 E1000_READ_REG(hw, E1000_PRC1522); 1593 E1000_READ_REG(hw, E1000_PTC64); 1594 E1000_READ_REG(hw, E1000_PTC127); 1595 E1000_READ_REG(hw, E1000_PTC255); 1596 E1000_READ_REG(hw, E1000_PTC511); 1597 E1000_READ_REG(hw, E1000_PTC1023); 1598 E1000_READ_REG(hw, E1000_PTC1522); 1599 1600 E1000_READ_REG(hw, E1000_ALGNERRC); 1601 E1000_READ_REG(hw, E1000_RXERRC); 1602 E1000_READ_REG(hw, E1000_TNCRS); 1603 E1000_READ_REG(hw, E1000_CEXTERR); 1604 E1000_READ_REG(hw, E1000_TSCTC); 1605 E1000_READ_REG(hw, E1000_TSCTFC); 1606 } 1607 1608 /** 1609 * e1000_read_mac_addr_82543 - Read device MAC address 1610 * @hw: pointer to the HW structure 1611 * 1612 * Reads the device MAC address from the EEPROM and stores the value. 1613 * Since devices with two ports use the same EEPROM, we increment the 1614 * last bit in the MAC address for the second port. 1615 * 1616 **/ 1617 s32 e1000_read_mac_addr_82543(struct e1000_hw *hw) 1618 { 1619 s32 ret_val = E1000_SUCCESS; 1620 u16 offset, nvm_data, i; 1621 1622 DEBUGFUNC("e1000_read_mac_addr"); 1623 1624 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 1625 offset = i >> 1; 1626 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 1627 if (ret_val) { 1628 DEBUGOUT("NVM Read Error\n"); 1629 goto out; 1630 } 1631 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 1632 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 1633 } 1634 1635 /* Flip last bit of mac address if we're on second port */ 1636 if (hw->bus.func == E1000_FUNC_1) 1637 hw->mac.perm_addr[5] ^= 1; 1638 1639 for (i = 0; i < ETH_ADDR_LEN; i++) 1640 hw->mac.addr[i] = hw->mac.perm_addr[i]; 1641 1642 out: 1643 return ret_val; 1644 } 1645