1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* e1000_82542 (rev 1 & 2) 36 */ 37 38 #include "e1000_api.h" 39 40 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw); 41 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw); 42 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw); 43 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw); 44 static s32 e1000_reset_hw_82542(struct e1000_hw *hw); 45 static s32 e1000_init_hw_82542(struct e1000_hw *hw); 46 static s32 e1000_setup_link_82542(struct e1000_hw *hw); 47 static s32 e1000_led_on_82542(struct e1000_hw *hw); 48 static s32 e1000_led_off_82542(struct e1000_hw *hw); 49 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index); 50 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw); 51 52 struct e1000_dev_spec_82542 { 53 bool dma_fairness; 54 }; 55 56 /** 57 * e1000_init_phy_params_82542 - Init PHY func ptrs. 58 * @hw: pointer to the HW structure 59 * 60 * This is a function pointer entry point called by the api module. 61 **/ 62 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw) 63 { 64 struct e1000_phy_info *phy = &hw->phy; 65 s32 ret_val = E1000_SUCCESS; 66 67 DEBUGFUNC("e1000_init_phy_params_82542"); 68 69 phy->type = e1000_phy_none; 70 71 return ret_val; 72 } 73 74 /** 75 * e1000_init_nvm_params_82542 - Init NVM func ptrs. 76 * @hw: pointer to the HW structure 77 * 78 * This is a function pointer entry point called by the api module. 79 **/ 80 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw) 81 { 82 struct e1000_nvm_info *nvm = &hw->nvm; 83 84 DEBUGFUNC("e1000_init_nvm_params_82542"); 85 86 nvm->address_bits = 6; 87 nvm->delay_usec = 50; 88 nvm->opcode_bits = 3; 89 nvm->type = e1000_nvm_eeprom_microwire; 90 nvm->word_size = 64; 91 92 /* Function Pointers */ 93 nvm->ops.read = e1000_read_nvm_microwire; 94 nvm->ops.release = e1000_stop_nvm; 95 nvm->ops.write = e1000_write_nvm_microwire; 96 nvm->ops.update = e1000_update_nvm_checksum_generic; 97 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 98 99 return E1000_SUCCESS; 100 } 101 102 /** 103 * e1000_init_mac_params_82542 - Init MAC func ptrs. 104 * @hw: pointer to the HW structure 105 * 106 * This is a function pointer entry point called by the api module. 107 **/ 108 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw) 109 { 110 struct e1000_mac_info *mac = &hw->mac; 111 s32 ret_val = E1000_SUCCESS; 112 113 DEBUGFUNC("e1000_init_mac_params_82542"); 114 115 /* Set media type */ 116 hw->phy.media_type = e1000_media_type_fiber; 117 118 /* Set mta register count */ 119 mac->mta_reg_count = 128; 120 /* Set rar entry count */ 121 mac->rar_entry_count = E1000_RAR_ENTRIES; 122 123 /* Function pointers */ 124 125 /* bus type/speed/width */ 126 mac->ops.get_bus_info = e1000_get_bus_info_82542; 127 /* reset */ 128 mac->ops.reset_hw = e1000_reset_hw_82542; 129 /* hw initialization */ 130 mac->ops.init_hw = e1000_init_hw_82542; 131 /* link setup */ 132 mac->ops.setup_link = e1000_setup_link_82542; 133 /* phy/fiber/serdes setup */ 134 mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic; 135 /* check for link */ 136 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 137 /* multicast address update */ 138 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 139 /* writing VFTA */ 140 mac->ops.write_vfta = e1000_write_vfta_generic; 141 /* clearing VFTA */ 142 mac->ops.clear_vfta = e1000_clear_vfta_generic; 143 /* setting MTA */ 144 mac->ops.mta_set = e1000_mta_set_generic; 145 /* set RAR */ 146 mac->ops.rar_set = e1000_rar_set_82542; 147 /* turn on/off LED */ 148 mac->ops.led_on = e1000_led_on_82542; 149 mac->ops.led_off = e1000_led_off_82542; 150 /* remove device */ 151 mac->ops.remove_device = e1000_remove_device_generic; 152 /* clear hardware counters */ 153 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542; 154 /* link info */ 155 mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic; 156 157 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82542); 158 159 /* Device-specific structure allocation */ 160 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 161 162 return ret_val; 163 } 164 165 /** 166 * e1000_init_function_pointers_82542 - Init func ptrs. 167 * @hw: pointer to the HW structure 168 * 169 * The only function explicitly called by the api module to initialize 170 * all function pointers and parameters. 171 **/ 172 void e1000_init_function_pointers_82542(struct e1000_hw *hw) 173 { 174 DEBUGFUNC("e1000_init_function_pointers_82542"); 175 176 hw->mac.ops.init_params = e1000_init_mac_params_82542; 177 hw->nvm.ops.init_params = e1000_init_nvm_params_82542; 178 hw->phy.ops.init_params = e1000_init_phy_params_82542; 179 } 180 181 /** 182 * e1000_get_bus_info_82542 - Obtain bus information for adapter 183 * @hw: pointer to the HW structure 184 * 185 * This will obtain information about the HW bus for which the 186 * adapter is attached and stores it in the hw structure. This is a function 187 * pointer entry point called by the api module. 188 **/ 189 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw) 190 { 191 DEBUGFUNC("e1000_get_bus_info_82542"); 192 193 hw->bus.type = e1000_bus_type_pci; 194 hw->bus.speed = e1000_bus_speed_unknown; 195 hw->bus.width = e1000_bus_width_unknown; 196 197 return E1000_SUCCESS; 198 } 199 200 /** 201 * e1000_reset_hw_82542 - Reset hardware 202 * @hw: pointer to the HW structure 203 * 204 * This resets the hardware into a known state. This is a 205 * function pointer entry point called by the api module. 206 **/ 207 static s32 e1000_reset_hw_82542(struct e1000_hw *hw) 208 { 209 struct e1000_bus_info *bus = &hw->bus; 210 s32 ret_val = E1000_SUCCESS; 211 u32 ctrl, icr; 212 213 DEBUGFUNC("e1000_reset_hw_82542"); 214 215 if (hw->revision_id == E1000_REVISION_2) { 216 DEBUGOUT("Disabling MWI on 82542 rev 2\n"); 217 e1000_pci_clear_mwi(hw); 218 } 219 220 DEBUGOUT("Masking off all interrupts\n"); 221 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 222 223 E1000_WRITE_REG(hw, E1000_RCTL, 0); 224 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 225 E1000_WRITE_FLUSH(hw); 226 227 /* 228 * Delay to allow any outstanding PCI transactions to complete before 229 * resetting the device 230 */ 231 msec_delay(10); 232 233 ctrl = E1000_READ_REG(hw, E1000_CTRL); 234 235 DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n"); 236 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 237 238 hw->nvm.ops.reload(hw); 239 msec_delay(2); 240 241 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 242 icr = E1000_READ_REG(hw, E1000_ICR); 243 244 if (hw->revision_id == E1000_REVISION_2) { 245 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 246 e1000_pci_set_mwi(hw); 247 } 248 249 return ret_val; 250 } 251 252 /** 253 * e1000_init_hw_82542 - Initialize hardware 254 * @hw: pointer to the HW structure 255 * 256 * This inits the hardware readying it for operation. This is a 257 * function pointer entry point called by the api module. 258 **/ 259 static s32 e1000_init_hw_82542(struct e1000_hw *hw) 260 { 261 struct e1000_mac_info *mac = &hw->mac; 262 struct e1000_dev_spec_82542 *dev_spec; 263 s32 ret_val = E1000_SUCCESS; 264 u32 ctrl; 265 u16 i; 266 267 DEBUGFUNC("e1000_init_hw_82542"); 268 269 dev_spec = (struct e1000_dev_spec_82542 *)hw->dev_spec; 270 271 /* Disabling VLAN filtering */ 272 E1000_WRITE_REG(hw, E1000_VET, 0); 273 mac->ops.clear_vfta(hw); 274 275 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 276 if (hw->revision_id == E1000_REVISION_2) { 277 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 278 e1000_pci_clear_mwi(hw); 279 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 280 E1000_WRITE_FLUSH(hw); 281 msec_delay(5); 282 } 283 284 /* Setup the receive address. */ 285 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 286 287 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 288 if (hw->revision_id == E1000_REVISION_2) { 289 E1000_WRITE_REG(hw, E1000_RCTL, 0); 290 E1000_WRITE_FLUSH(hw); 291 msec_delay(1); 292 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 293 e1000_pci_set_mwi(hw); 294 } 295 296 /* Zero out the Multicast HASH table */ 297 DEBUGOUT("Zeroing the MTA\n"); 298 for (i = 0; i < mac->mta_reg_count; i++) 299 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 300 301 /* 302 * Set the PCI priority bit correctly in the CTRL register. This 303 * determines if the adapter gives priority to receives, or if it 304 * gives equal priority to transmits and receives. 305 */ 306 if (dev_spec->dma_fairness) { 307 ctrl = E1000_READ_REG(hw, E1000_CTRL); 308 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 309 } 310 311 /* Setup link and flow control */ 312 ret_val = e1000_setup_link_82542(hw); 313 314 /* 315 * Clear all of the statistics registers (clear on read). It is 316 * important that we do this after we have tried to establish link 317 * because the symbol error count will increment wildly if there 318 * is no link. 319 */ 320 e1000_clear_hw_cntrs_82542(hw); 321 322 return ret_val; 323 } 324 325 /** 326 * e1000_setup_link_82542 - Setup flow control and link settings 327 * @hw: pointer to the HW structure 328 * 329 * Determines which flow control settings to use, then configures flow 330 * control. Calls the appropriate media-specific link configuration 331 * function. Assuming the adapter has a valid link partner, a valid link 332 * should be established. Assumes the hardware has previously been reset 333 * and the transmitter and receiver are not enabled. This is a function 334 * pointer entry point called by the api module. 335 **/ 336 static s32 e1000_setup_link_82542(struct e1000_hw *hw) 337 { 338 struct e1000_mac_info *mac = &hw->mac; 339 s32 ret_val = E1000_SUCCESS; 340 341 DEBUGFUNC("e1000_setup_link_82542"); 342 343 ret_val = e1000_set_default_fc_generic(hw); 344 if (ret_val) 345 goto out; 346 347 hw->fc.type &= ~e1000_fc_tx_pause; 348 349 if (mac->report_tx_early == 1) 350 hw->fc.type &= ~e1000_fc_rx_pause; 351 352 /* 353 * We want to save off the original Flow Control configuration just in 354 * case we get disconnected and then reconnected into a different hub 355 * or switch with different Flow Control capabilities. 356 */ 357 hw->fc.original_type = hw->fc.type; 358 359 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type); 360 361 /* Call the necessary subroutine to configure the link. */ 362 ret_val = mac->ops.setup_physical_interface(hw); 363 if (ret_val) 364 goto out; 365 366 /* 367 * Initialize the flow control address, type, and PAUSE timer 368 * registers to their default values. This is done even if flow 369 * control is disabled, because it does not hurt anything to 370 * initialize these registers. 371 */ 372 DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); 373 374 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 375 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 376 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 377 378 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 379 380 ret_val = e1000_set_fc_watermarks_generic(hw); 381 382 out: 383 return ret_val; 384 } 385 386 /** 387 * e1000_led_on_82542 - Turn on SW controllable LED 388 * @hw: pointer to the HW structure 389 * 390 * Turns the SW defined LED on. This is a function pointer entry point 391 * called by the api module. 392 **/ 393 static s32 e1000_led_on_82542(struct e1000_hw *hw) 394 { 395 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 396 397 DEBUGFUNC("e1000_led_on_82542"); 398 399 ctrl |= E1000_CTRL_SWDPIN0; 400 ctrl |= E1000_CTRL_SWDPIO0; 401 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 402 403 return E1000_SUCCESS; 404 } 405 406 /** 407 * e1000_led_off_82542 - Turn off SW controllable LED 408 * @hw: pointer to the HW structure 409 * 410 * Turns the SW defined LED off. This is a function pointer entry point 411 * called by the api module. 412 **/ 413 static s32 e1000_led_off_82542(struct e1000_hw *hw) 414 { 415 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 416 417 DEBUGFUNC("e1000_led_off_82542"); 418 419 ctrl &= ~E1000_CTRL_SWDPIN0; 420 ctrl |= E1000_CTRL_SWDPIO0; 421 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 422 423 return E1000_SUCCESS; 424 } 425 426 /** 427 * e1000_rar_set_82542 - Set receive address register 428 * @hw: pointer to the HW structure 429 * @addr: pointer to the receive address 430 * @index: receive address array register 431 * 432 * Sets the receive address array register at index to the address passed 433 * in by addr. 434 **/ 435 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index) 436 { 437 u32 rar_low, rar_high; 438 439 DEBUGFUNC("e1000_rar_set_82542"); 440 441 /* 442 * HW expects these in little endian so we reverse the byte order 443 * from network order (big endian) to little endian 444 */ 445 rar_low = ((u32) addr[0] | 446 ((u32) addr[1] << 8) | 447 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 448 449 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 450 451 /* If MAC address zero, no need to set the AV bit */ 452 if (rar_low || rar_high) { 453 if (!hw->mac.disable_av) 454 rar_high |= E1000_RAH_AV; 455 } 456 457 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 458 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 459 } 460 461 /** 462 * e1000_translate_register_82542 - Translate the proper register offset 463 * @reg: e1000 register to be read 464 * 465 * Registers in 82542 are located in different offsets than other adapters 466 * even though they function in the same manner. This function takes in 467 * the name of the register to read and returns the correct offset for 468 * 82542 silicon. 469 **/ 470 u32 e1000_translate_register_82542(u32 reg) 471 { 472 /* 473 * Some of the 82542 registers are located at different 474 * offsets than they are in newer adapters. 475 * Despite the difference in location, the registers 476 * function in the same manner. 477 */ 478 switch (reg) { 479 case E1000_RA: 480 reg = 0x00040; 481 break; 482 case E1000_RDTR: 483 reg = 0x00108; 484 break; 485 case E1000_RDBAL(0): 486 reg = 0x00110; 487 break; 488 case E1000_RDBAH(0): 489 reg = 0x00114; 490 break; 491 case E1000_RDLEN(0): 492 reg = 0x00118; 493 break; 494 case E1000_RDH(0): 495 reg = 0x00120; 496 break; 497 case E1000_RDT(0): 498 reg = 0x00128; 499 break; 500 case E1000_RDBAL(1): 501 reg = 0x00138; 502 break; 503 case E1000_RDBAH(1): 504 reg = 0x0013C; 505 break; 506 case E1000_RDLEN(1): 507 reg = 0x00140; 508 break; 509 case E1000_RDH(1): 510 reg = 0x00148; 511 break; 512 case E1000_RDT(1): 513 reg = 0x00150; 514 break; 515 case E1000_FCRTH: 516 reg = 0x00160; 517 break; 518 case E1000_FCRTL: 519 reg = 0x00168; 520 break; 521 case E1000_MTA: 522 reg = 0x00200; 523 break; 524 case E1000_TDBAL(0): 525 reg = 0x00420; 526 break; 527 case E1000_TDBAH(0): 528 reg = 0x00424; 529 break; 530 case E1000_TDLEN(0): 531 reg = 0x00428; 532 break; 533 case E1000_TDH(0): 534 reg = 0x00430; 535 break; 536 case E1000_TDT(0): 537 reg = 0x00438; 538 break; 539 case E1000_TIDV: 540 reg = 0x00440; 541 break; 542 case E1000_VFTA: 543 reg = 0x00600; 544 break; 545 case E1000_TDFH: 546 reg = 0x08010; 547 break; 548 case E1000_TDFT: 549 reg = 0x08018; 550 break; 551 default: 552 break; 553 } 554 555 return reg; 556 } 557 558 /** 559 * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters 560 * @hw: pointer to the HW structure 561 * 562 * Clears the hardware counters by reading the counter registers. 563 **/ 564 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw) 565 { 566 volatile u32 temp; 567 568 DEBUGFUNC("e1000_clear_hw_cntrs_82542"); 569 570 e1000_clear_hw_cntrs_base_generic(hw); 571 572 temp = E1000_READ_REG(hw, E1000_PRC64); 573 temp = E1000_READ_REG(hw, E1000_PRC127); 574 temp = E1000_READ_REG(hw, E1000_PRC255); 575 temp = E1000_READ_REG(hw, E1000_PRC511); 576 temp = E1000_READ_REG(hw, E1000_PRC1023); 577 temp = E1000_READ_REG(hw, E1000_PRC1522); 578 temp = E1000_READ_REG(hw, E1000_PTC64); 579 temp = E1000_READ_REG(hw, E1000_PTC127); 580 temp = E1000_READ_REG(hw, E1000_PTC255); 581 temp = E1000_READ_REG(hw, E1000_PTC511); 582 temp = E1000_READ_REG(hw, E1000_PTC1023); 583 temp = E1000_READ_REG(hw, E1000_PTC1522); 584 } 585