1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82542 Gigabit Ethernet Controller 37 */ 38 39 #include "e1000_api.h" 40 41 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw); 42 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw); 43 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw); 44 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw); 45 static s32 e1000_reset_hw_82542(struct e1000_hw *hw); 46 static s32 e1000_init_hw_82542(struct e1000_hw *hw); 47 static s32 e1000_setup_link_82542(struct e1000_hw *hw); 48 static s32 e1000_led_on_82542(struct e1000_hw *hw); 49 static s32 e1000_led_off_82542(struct e1000_hw *hw); 50 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index); 51 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw); 52 static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw); 53 54 55 /** 56 * e1000_init_phy_params_82542 - Init PHY func ptrs. 57 * @hw: pointer to the HW structure 58 **/ 59 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw) 60 { 61 struct e1000_phy_info *phy = &hw->phy; 62 s32 ret_val = E1000_SUCCESS; 63 64 DEBUGFUNC("e1000_init_phy_params_82542"); 65 66 phy->type = e1000_phy_none; 67 68 return ret_val; 69 } 70 71 /** 72 * e1000_init_nvm_params_82542 - Init NVM func ptrs. 73 * @hw: pointer to the HW structure 74 **/ 75 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw) 76 { 77 struct e1000_nvm_info *nvm = &hw->nvm; 78 79 DEBUGFUNC("e1000_init_nvm_params_82542"); 80 81 nvm->address_bits = 6; 82 nvm->delay_usec = 50; 83 nvm->opcode_bits = 3; 84 nvm->type = e1000_nvm_eeprom_microwire; 85 nvm->word_size = 64; 86 87 /* Function Pointers */ 88 nvm->ops.read = e1000_read_nvm_microwire; 89 nvm->ops.release = e1000_stop_nvm; 90 nvm->ops.write = e1000_write_nvm_microwire; 91 nvm->ops.update = e1000_update_nvm_checksum_generic; 92 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 93 94 return E1000_SUCCESS; 95 } 96 97 /** 98 * e1000_init_mac_params_82542 - Init MAC func ptrs. 99 * @hw: pointer to the HW structure 100 **/ 101 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw) 102 { 103 struct e1000_mac_info *mac = &hw->mac; 104 105 DEBUGFUNC("e1000_init_mac_params_82542"); 106 107 /* Set media type */ 108 hw->phy.media_type = e1000_media_type_fiber; 109 110 /* Set mta register count */ 111 mac->mta_reg_count = 128; 112 /* Set rar entry count */ 113 mac->rar_entry_count = E1000_RAR_ENTRIES; 114 115 /* Function pointers */ 116 117 /* bus type/speed/width */ 118 mac->ops.get_bus_info = e1000_get_bus_info_82542; 119 /* function id */ 120 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 121 /* reset */ 122 mac->ops.reset_hw = e1000_reset_hw_82542; 123 /* hw initialization */ 124 mac->ops.init_hw = e1000_init_hw_82542; 125 /* link setup */ 126 mac->ops.setup_link = e1000_setup_link_82542; 127 /* phy/fiber/serdes setup */ 128 mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic; 129 /* check for link */ 130 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 131 /* multicast address update */ 132 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 133 /* writing VFTA */ 134 mac->ops.write_vfta = e1000_write_vfta_generic; 135 /* clearing VFTA */ 136 mac->ops.clear_vfta = e1000_clear_vfta_generic; 137 /* setting MTA */ 138 mac->ops.mta_set = e1000_mta_set_generic; 139 /* read mac address */ 140 mac->ops.read_mac_addr = e1000_read_mac_addr_82542; 141 /* set RAR */ 142 mac->ops.rar_set = e1000_rar_set_82542; 143 /* turn on/off LED */ 144 mac->ops.led_on = e1000_led_on_82542; 145 mac->ops.led_off = e1000_led_off_82542; 146 /* clear hardware counters */ 147 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542; 148 /* link info */ 149 mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic; 150 151 return E1000_SUCCESS; 152 } 153 154 /** 155 * e1000_init_function_pointers_82542 - Init func ptrs. 156 * @hw: pointer to the HW structure 157 * 158 * Called to initialize all function pointers and parameters. 159 **/ 160 void e1000_init_function_pointers_82542(struct e1000_hw *hw) 161 { 162 DEBUGFUNC("e1000_init_function_pointers_82542"); 163 164 hw->mac.ops.init_params = e1000_init_mac_params_82542; 165 hw->nvm.ops.init_params = e1000_init_nvm_params_82542; 166 hw->phy.ops.init_params = e1000_init_phy_params_82542; 167 } 168 169 /** 170 * e1000_get_bus_info_82542 - Obtain bus information for adapter 171 * @hw: pointer to the HW structure 172 * 173 * This will obtain information about the HW bus for which the 174 * adapter is attached and stores it in the hw structure. 175 **/ 176 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw) 177 { 178 DEBUGFUNC("e1000_get_bus_info_82542"); 179 180 hw->bus.type = e1000_bus_type_pci; 181 hw->bus.speed = e1000_bus_speed_unknown; 182 hw->bus.width = e1000_bus_width_unknown; 183 184 return E1000_SUCCESS; 185 } 186 187 /** 188 * e1000_reset_hw_82542 - Reset hardware 189 * @hw: pointer to the HW structure 190 * 191 * This resets the hardware into a known state. 192 **/ 193 static s32 e1000_reset_hw_82542(struct e1000_hw *hw) 194 { 195 struct e1000_bus_info *bus = &hw->bus; 196 s32 ret_val = E1000_SUCCESS; 197 u32 ctrl, icr; 198 199 DEBUGFUNC("e1000_reset_hw_82542"); 200 201 if (hw->revision_id == E1000_REVISION_2) { 202 DEBUGOUT("Disabling MWI on 82542 rev 2\n"); 203 e1000_pci_clear_mwi(hw); 204 } 205 206 DEBUGOUT("Masking off all interrupts\n"); 207 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 208 209 E1000_WRITE_REG(hw, E1000_RCTL, 0); 210 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 211 E1000_WRITE_FLUSH(hw); 212 213 /* 214 * Delay to allow any outstanding PCI transactions to complete before 215 * resetting the device 216 */ 217 msec_delay(10); 218 219 ctrl = E1000_READ_REG(hw, E1000_CTRL); 220 221 DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n"); 222 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 223 224 hw->nvm.ops.reload(hw); 225 msec_delay(2); 226 227 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 228 icr = E1000_READ_REG(hw, E1000_ICR); 229 230 if (hw->revision_id == E1000_REVISION_2) { 231 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 232 e1000_pci_set_mwi(hw); 233 } 234 235 return ret_val; 236 } 237 238 /** 239 * e1000_init_hw_82542 - Initialize hardware 240 * @hw: pointer to the HW structure 241 * 242 * This inits the hardware readying it for operation. 243 **/ 244 static s32 e1000_init_hw_82542(struct e1000_hw *hw) 245 { 246 struct e1000_mac_info *mac = &hw->mac; 247 struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542; 248 s32 ret_val = E1000_SUCCESS; 249 u32 ctrl; 250 u16 i; 251 252 DEBUGFUNC("e1000_init_hw_82542"); 253 254 /* Disabling VLAN filtering */ 255 E1000_WRITE_REG(hw, E1000_VET, 0); 256 mac->ops.clear_vfta(hw); 257 258 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 259 if (hw->revision_id == E1000_REVISION_2) { 260 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 261 e1000_pci_clear_mwi(hw); 262 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 263 E1000_WRITE_FLUSH(hw); 264 msec_delay(5); 265 } 266 267 /* Setup the receive address. */ 268 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 269 270 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 271 if (hw->revision_id == E1000_REVISION_2) { 272 E1000_WRITE_REG(hw, E1000_RCTL, 0); 273 E1000_WRITE_FLUSH(hw); 274 msec_delay(1); 275 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 276 e1000_pci_set_mwi(hw); 277 } 278 279 /* Zero out the Multicast HASH table */ 280 DEBUGOUT("Zeroing the MTA\n"); 281 for (i = 0; i < mac->mta_reg_count; i++) 282 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 283 284 /* 285 * Set the PCI priority bit correctly in the CTRL register. This 286 * determines if the adapter gives priority to receives, or if it 287 * gives equal priority to transmits and receives. 288 */ 289 if (dev_spec->dma_fairness) { 290 ctrl = E1000_READ_REG(hw, E1000_CTRL); 291 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 292 } 293 294 /* Setup link and flow control */ 295 ret_val = e1000_setup_link_82542(hw); 296 297 /* 298 * Clear all of the statistics registers (clear on read). It is 299 * important that we do this after we have tried to establish link 300 * because the symbol error count will increment wildly if there 301 * is no link. 302 */ 303 e1000_clear_hw_cntrs_82542(hw); 304 305 return ret_val; 306 } 307 308 /** 309 * e1000_setup_link_82542 - Setup flow control and link settings 310 * @hw: pointer to the HW structure 311 * 312 * Determines which flow control settings to use, then configures flow 313 * control. Calls the appropriate media-specific link configuration 314 * function. Assuming the adapter has a valid link partner, a valid link 315 * should be established. Assumes the hardware has previously been reset 316 * and the transmitter and receiver are not enabled. 317 **/ 318 static s32 e1000_setup_link_82542(struct e1000_hw *hw) 319 { 320 struct e1000_mac_info *mac = &hw->mac; 321 s32 ret_val = E1000_SUCCESS; 322 323 DEBUGFUNC("e1000_setup_link_82542"); 324 325 ret_val = e1000_set_default_fc_generic(hw); 326 if (ret_val) 327 goto out; 328 329 hw->fc.requested_mode &= ~e1000_fc_tx_pause; 330 331 if (mac->report_tx_early == 1) 332 hw->fc.requested_mode &= ~e1000_fc_rx_pause; 333 334 /* 335 * Save off the requested flow control mode for use later. Depending 336 * on the link partner's capabilities, we may or may not use this mode. 337 */ 338 hw->fc.current_mode = hw->fc.requested_mode; 339 340 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 341 hw->fc.current_mode); 342 343 /* Call the necessary subroutine to configure the link. */ 344 ret_val = mac->ops.setup_physical_interface(hw); 345 if (ret_val) 346 goto out; 347 348 /* 349 * Initialize the flow control address, type, and PAUSE timer 350 * registers to their default values. This is done even if flow 351 * control is disabled, because it does not hurt anything to 352 * initialize these registers. 353 */ 354 DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); 355 356 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 357 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 358 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 359 360 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 361 362 ret_val = e1000_set_fc_watermarks_generic(hw); 363 364 out: 365 return ret_val; 366 } 367 368 /** 369 * e1000_led_on_82542 - Turn on SW controllable LED 370 * @hw: pointer to the HW structure 371 * 372 * Turns the SW defined LED on. 373 **/ 374 static s32 e1000_led_on_82542(struct e1000_hw *hw) 375 { 376 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 377 378 DEBUGFUNC("e1000_led_on_82542"); 379 380 ctrl |= E1000_CTRL_SWDPIN0; 381 ctrl |= E1000_CTRL_SWDPIO0; 382 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 383 384 return E1000_SUCCESS; 385 } 386 387 /** 388 * e1000_led_off_82542 - Turn off SW controllable LED 389 * @hw: pointer to the HW structure 390 * 391 * Turns the SW defined LED off. 392 **/ 393 static s32 e1000_led_off_82542(struct e1000_hw *hw) 394 { 395 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 396 397 DEBUGFUNC("e1000_led_off_82542"); 398 399 ctrl &= ~E1000_CTRL_SWDPIN0; 400 ctrl |= E1000_CTRL_SWDPIO0; 401 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 402 403 return E1000_SUCCESS; 404 } 405 406 /** 407 * e1000_rar_set_82542 - Set receive address register 408 * @hw: pointer to the HW structure 409 * @addr: pointer to the receive address 410 * @index: receive address array register 411 * 412 * Sets the receive address array register at index to the address passed 413 * in by addr. 414 **/ 415 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index) 416 { 417 u32 rar_low, rar_high; 418 419 DEBUGFUNC("e1000_rar_set_82542"); 420 421 /* 422 * HW expects these in little endian so we reverse the byte order 423 * from network order (big endian) to little endian 424 */ 425 rar_low = ((u32) addr[0] | 426 ((u32) addr[1] << 8) | 427 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 428 429 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 430 431 /* If MAC address zero, no need to set the AV bit */ 432 if (rar_low || rar_high) 433 rar_high |= E1000_RAH_AV; 434 435 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 436 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 437 } 438 439 /** 440 * e1000_translate_register_82542 - Translate the proper register offset 441 * @reg: e1000 register to be read 442 * 443 * Registers in 82542 are located in different offsets than other adapters 444 * even though they function in the same manner. This function takes in 445 * the name of the register to read and returns the correct offset for 446 * 82542 silicon. 447 **/ 448 u32 e1000_translate_register_82542(u32 reg) 449 { 450 /* 451 * Some of the 82542 registers are located at different 452 * offsets than they are in newer adapters. 453 * Despite the difference in location, the registers 454 * function in the same manner. 455 */ 456 switch (reg) { 457 case E1000_RA: 458 reg = 0x00040; 459 break; 460 case E1000_RDTR: 461 reg = 0x00108; 462 break; 463 case E1000_RDBAL(0): 464 reg = 0x00110; 465 break; 466 case E1000_RDBAH(0): 467 reg = 0x00114; 468 break; 469 case E1000_RDLEN(0): 470 reg = 0x00118; 471 break; 472 case E1000_RDH(0): 473 reg = 0x00120; 474 break; 475 case E1000_RDT(0): 476 reg = 0x00128; 477 break; 478 case E1000_RDBAL(1): 479 reg = 0x00138; 480 break; 481 case E1000_RDBAH(1): 482 reg = 0x0013C; 483 break; 484 case E1000_RDLEN(1): 485 reg = 0x00140; 486 break; 487 case E1000_RDH(1): 488 reg = 0x00148; 489 break; 490 case E1000_RDT(1): 491 reg = 0x00150; 492 break; 493 case E1000_FCRTH: 494 reg = 0x00160; 495 break; 496 case E1000_FCRTL: 497 reg = 0x00168; 498 break; 499 case E1000_MTA: 500 reg = 0x00200; 501 break; 502 case E1000_TDBAL(0): 503 reg = 0x00420; 504 break; 505 case E1000_TDBAH(0): 506 reg = 0x00424; 507 break; 508 case E1000_TDLEN(0): 509 reg = 0x00428; 510 break; 511 case E1000_TDH(0): 512 reg = 0x00430; 513 break; 514 case E1000_TDT(0): 515 reg = 0x00438; 516 break; 517 case E1000_TIDV: 518 reg = 0x00440; 519 break; 520 case E1000_VFTA: 521 reg = 0x00600; 522 break; 523 case E1000_TDFH: 524 reg = 0x08010; 525 break; 526 case E1000_TDFT: 527 reg = 0x08018; 528 break; 529 default: 530 break; 531 } 532 533 return reg; 534 } 535 536 /** 537 * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters 538 * @hw: pointer to the HW structure 539 * 540 * Clears the hardware counters by reading the counter registers. 541 **/ 542 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw) 543 { 544 DEBUGFUNC("e1000_clear_hw_cntrs_82542"); 545 546 e1000_clear_hw_cntrs_base_generic(hw); 547 548 E1000_READ_REG(hw, E1000_PRC64); 549 E1000_READ_REG(hw, E1000_PRC127); 550 E1000_READ_REG(hw, E1000_PRC255); 551 E1000_READ_REG(hw, E1000_PRC511); 552 E1000_READ_REG(hw, E1000_PRC1023); 553 E1000_READ_REG(hw, E1000_PRC1522); 554 E1000_READ_REG(hw, E1000_PTC64); 555 E1000_READ_REG(hw, E1000_PTC127); 556 E1000_READ_REG(hw, E1000_PTC255); 557 E1000_READ_REG(hw, E1000_PTC511); 558 E1000_READ_REG(hw, E1000_PTC1023); 559 E1000_READ_REG(hw, E1000_PTC1522); 560 } 561 562 /** 563 * e1000_read_mac_addr_82542 - Read device MAC address 564 * @hw: pointer to the HW structure 565 * 566 * Reads the device MAC address from the EEPROM and stores the value. 567 **/ 568 static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw) 569 { 570 s32 ret_val = E1000_SUCCESS; 571 u16 offset, nvm_data, i; 572 573 DEBUGFUNC("e1000_read_mac_addr"); 574 575 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 576 offset = i >> 1; 577 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 578 if (ret_val) { 579 DEBUGOUT("NVM Read Error\n"); 580 goto out; 581 } 582 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 583 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 584 } 585 586 for (i = 0; i < ETH_ADDR_LEN; i++) 587 hw->mac.addr[i] = hw->mac.perm_addr[i]; 588 589 out: 590 return ret_val; 591 } 592