1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82541EI Gigabit Ethernet Controller 37 * 82541ER Gigabit Ethernet Controller 38 * 82541GI Gigabit Ethernet Controller 39 * 82541PI Gigabit Ethernet Controller 40 * 82547EI Gigabit Ethernet Controller 41 * 82547GI Gigabit Ethernet Controller 42 */ 43 44 #include "e1000_api.h" 45 46 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 47 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 48 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 49 static s32 e1000_reset_hw_82541(struct e1000_hw *hw); 50 static s32 e1000_init_hw_82541(struct e1000_hw *hw); 51 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 52 u16 *duplex); 53 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 54 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 55 static s32 e1000_check_for_link_82541(struct e1000_hw *hw); 56 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 57 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 58 bool active); 59 static s32 e1000_setup_led_82541(struct e1000_hw *hw); 60 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 62 static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw); 63 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 64 bool link_up); 65 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 66 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 67 68 static const u16 e1000_igp_cable_length_table[] = 69 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 70 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 71 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 72 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 73 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 74 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 75 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 76 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 77 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 78 (sizeof(e1000_igp_cable_length_table) / \ 79 sizeof(e1000_igp_cable_length_table[0])) 80 81 /** 82 * e1000_init_phy_params_82541 - Init PHY func ptrs. 83 * @hw: pointer to the HW structure 84 **/ 85 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw) 86 { 87 struct e1000_phy_info *phy = &hw->phy; 88 s32 ret_val = E1000_SUCCESS; 89 90 DEBUGFUNC("e1000_init_phy_params_82541"); 91 92 phy->addr = 1; 93 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 94 phy->reset_delay_us = 10000; 95 phy->type = e1000_phy_igp; 96 97 /* Function Pointers */ 98 phy->ops.check_polarity = e1000_check_polarity_igp; 99 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 100 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; 101 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 102 phy->ops.get_info = e1000_get_phy_info_igp; 103 phy->ops.read_reg = e1000_read_phy_reg_igp; 104 phy->ops.reset = e1000_phy_hw_reset_82541; 105 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 106 phy->ops.write_reg = e1000_write_phy_reg_igp; 107 phy->ops.power_up = e1000_power_up_phy_copper; 108 phy->ops.power_down = e1000_power_down_phy_copper_82541; 109 110 ret_val = e1000_get_phy_id(hw); 111 if (ret_val) 112 goto out; 113 114 /* Verify phy id */ 115 if (phy->id != IGP01E1000_I_PHY_ID) { 116 ret_val = -E1000_ERR_PHY; 117 goto out; 118 } 119 120 out: 121 return ret_val; 122 } 123 124 /** 125 * e1000_init_nvm_params_82541 - Init NVM func ptrs. 126 * @hw: pointer to the HW structure 127 **/ 128 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) 129 { 130 struct e1000_nvm_info *nvm = &hw->nvm; 131 s32 ret_val = E1000_SUCCESS; 132 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 133 u16 size; 134 135 DEBUGFUNC("e1000_init_nvm_params_82541"); 136 137 switch (nvm->override) { 138 case e1000_nvm_override_spi_large: 139 nvm->type = e1000_nvm_eeprom_spi; 140 eecd |= E1000_EECD_ADDR_BITS; 141 break; 142 case e1000_nvm_override_spi_small: 143 nvm->type = e1000_nvm_eeprom_spi; 144 eecd &= ~E1000_EECD_ADDR_BITS; 145 break; 146 case e1000_nvm_override_microwire_large: 147 nvm->type = e1000_nvm_eeprom_microwire; 148 eecd |= E1000_EECD_SIZE; 149 break; 150 case e1000_nvm_override_microwire_small: 151 nvm->type = e1000_nvm_eeprom_microwire; 152 eecd &= ~E1000_EECD_SIZE; 153 break; 154 default: 155 nvm->type = eecd & E1000_EECD_TYPE 156 ? e1000_nvm_eeprom_spi 157 : e1000_nvm_eeprom_microwire; 158 break; 159 } 160 161 if (nvm->type == e1000_nvm_eeprom_spi) { 162 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 163 ? 16 : 8; 164 nvm->delay_usec = 1; 165 nvm->opcode_bits = 8; 166 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 167 ? 32 : 8; 168 169 /* Function Pointers */ 170 nvm->ops.acquire = e1000_acquire_nvm_generic; 171 nvm->ops.read = e1000_read_nvm_spi; 172 nvm->ops.release = e1000_release_nvm_generic; 173 nvm->ops.update = e1000_update_nvm_checksum_generic; 174 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 175 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 176 nvm->ops.write = e1000_write_nvm_spi; 177 178 /* 179 * nvm->word_size must be discovered after the pointers 180 * are set so we can verify the size from the nvm image 181 * itself. Temporarily set it to a dummy value so the 182 * read will work. 183 */ 184 nvm->word_size = 64; 185 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); 186 if (ret_val) 187 goto out; 188 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 189 /* 190 * if size != 0, it can be added to a constant and become 191 * the left-shift value to set the word_size. Otherwise, 192 * word_size stays at 64. 193 */ 194 if (size) { 195 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 196 nvm->word_size = 1 << size; 197 } 198 } else { 199 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 200 ? 8 : 6; 201 nvm->delay_usec = 50; 202 nvm->opcode_bits = 3; 203 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 204 ? 256 : 64; 205 206 /* Function Pointers */ 207 nvm->ops.acquire = e1000_acquire_nvm_generic; 208 nvm->ops.read = e1000_read_nvm_microwire; 209 nvm->ops.release = e1000_release_nvm_generic; 210 nvm->ops.update = e1000_update_nvm_checksum_generic; 211 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 212 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 213 nvm->ops.write = e1000_write_nvm_microwire; 214 } 215 216 out: 217 return ret_val; 218 } 219 220 /** 221 * e1000_init_mac_params_82541 - Init MAC func ptrs. 222 * @hw: pointer to the HW structure 223 **/ 224 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw) 225 { 226 struct e1000_mac_info *mac = &hw->mac; 227 228 DEBUGFUNC("e1000_init_mac_params_82541"); 229 230 /* Set media type */ 231 hw->phy.media_type = e1000_media_type_copper; 232 /* Set mta register count */ 233 mac->mta_reg_count = 128; 234 /* Set rar entry count */ 235 mac->rar_entry_count = E1000_RAR_ENTRIES; 236 /* Set if part includes ASF firmware */ 237 mac->asf_firmware_present = TRUE; 238 239 /* Function Pointers */ 240 241 /* bus type/speed/width */ 242 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 243 /* function id */ 244 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 245 /* reset */ 246 mac->ops.reset_hw = e1000_reset_hw_82541; 247 /* hw initialization */ 248 mac->ops.init_hw = e1000_init_hw_82541; 249 /* link setup */ 250 mac->ops.setup_link = e1000_setup_link_generic; 251 /* physical interface link setup */ 252 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; 253 /* check for link */ 254 mac->ops.check_for_link = e1000_check_for_link_82541; 255 /* link info */ 256 mac->ops.get_link_up_info = e1000_get_link_up_info_82541; 257 /* multicast address update */ 258 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 259 /* writing VFTA */ 260 mac->ops.write_vfta = e1000_write_vfta_generic; 261 /* clearing VFTA */ 262 mac->ops.clear_vfta = e1000_clear_vfta_generic; 263 /* setting MTA */ 264 mac->ops.mta_set = e1000_mta_set_generic; 265 /* read mac address */ 266 mac->ops.read_mac_addr = e1000_read_mac_addr_82541; 267 /* ID LED init */ 268 mac->ops.id_led_init = e1000_id_led_init_generic; 269 /* setup LED */ 270 mac->ops.setup_led = e1000_setup_led_82541; 271 /* cleanup LED */ 272 mac->ops.cleanup_led = e1000_cleanup_led_82541; 273 /* turn on/off LED */ 274 mac->ops.led_on = e1000_led_on_generic; 275 mac->ops.led_off = e1000_led_off_generic; 276 /* clear hardware counters */ 277 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 278 279 return E1000_SUCCESS; 280 } 281 282 /** 283 * e1000_init_function_pointers_82541 - Init func ptrs. 284 * @hw: pointer to the HW structure 285 * 286 * Called to initialize all function pointers and parameters. 287 **/ 288 void e1000_init_function_pointers_82541(struct e1000_hw *hw) 289 { 290 DEBUGFUNC("e1000_init_function_pointers_82541"); 291 292 hw->mac.ops.init_params = e1000_init_mac_params_82541; 293 hw->nvm.ops.init_params = e1000_init_nvm_params_82541; 294 hw->phy.ops.init_params = e1000_init_phy_params_82541; 295 } 296 297 /** 298 * e1000_reset_hw_82541 - Reset hardware 299 * @hw: pointer to the HW structure 300 * 301 * This resets the hardware into a known state. 302 **/ 303 static s32 e1000_reset_hw_82541(struct e1000_hw *hw) 304 { 305 u32 ledctl, ctrl, icr, manc; 306 307 DEBUGFUNC("e1000_reset_hw_82541"); 308 309 DEBUGOUT("Masking off all interrupts\n"); 310 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 311 312 E1000_WRITE_REG(hw, E1000_RCTL, 0); 313 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 314 E1000_WRITE_FLUSH(hw); 315 316 /* 317 * Delay to allow any outstanding PCI transactions to complete 318 * before resetting the device. 319 */ 320 msec_delay(10); 321 322 ctrl = E1000_READ_REG(hw, E1000_CTRL); 323 324 /* Must reset the Phy before resetting the MAC */ 325 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 326 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 327 msec_delay(5); 328 } 329 330 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 331 switch (hw->mac.type) { 332 case e1000_82541: 333 case e1000_82541_rev_2: 334 /* 335 * These controllers can't ack the 64-bit write when 336 * issuing the reset, so we use IO-mapping as a 337 * workaround to issue the reset. 338 */ 339 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 340 break; 341 default: 342 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 343 break; 344 } 345 346 /* Wait for NVM reload */ 347 msec_delay(20); 348 349 /* Disable HW ARPs on ASF enabled adapters */ 350 manc = E1000_READ_REG(hw, E1000_MANC); 351 manc &= ~E1000_MANC_ARP_EN; 352 E1000_WRITE_REG(hw, E1000_MANC, manc); 353 354 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 355 e1000_phy_init_script_82541(hw); 356 357 /* Configure activity LED after Phy reset */ 358 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 359 ledctl &= IGP_ACTIVITY_LED_MASK; 360 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 361 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 362 } 363 364 /* Once again, mask the interrupts */ 365 DEBUGOUT("Masking off all interrupts\n"); 366 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 367 368 /* Clear any pending interrupt events. */ 369 icr = E1000_READ_REG(hw, E1000_ICR); 370 371 return E1000_SUCCESS; 372 } 373 374 /** 375 * e1000_init_hw_82541 - Initialize hardware 376 * @hw: pointer to the HW structure 377 * 378 * This inits the hardware readying it for operation. 379 **/ 380 static s32 e1000_init_hw_82541(struct e1000_hw *hw) 381 { 382 struct e1000_mac_info *mac = &hw->mac; 383 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 384 u32 i, txdctl; 385 s32 ret_val; 386 387 DEBUGFUNC("e1000_init_hw_82541"); 388 389 /* Initialize identification LED */ 390 ret_val = mac->ops.id_led_init(hw); 391 if (ret_val) { 392 DEBUGOUT("Error initializing identification LED\n"); 393 /* This is not fatal and we should not stop init due to this */ 394 } 395 396 /* Storing the Speed Power Down value for later use */ 397 ret_val = hw->phy.ops.read_reg(hw, 398 IGP01E1000_GMII_FIFO, 399 &dev_spec->spd_default); 400 if (ret_val) 401 goto out; 402 403 /* Disabling VLAN filtering */ 404 DEBUGOUT("Initializing the IEEE VLAN\n"); 405 mac->ops.clear_vfta(hw); 406 407 /* Setup the receive address. */ 408 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 409 410 /* Zero out the Multicast HASH table */ 411 DEBUGOUT("Zeroing the MTA\n"); 412 for (i = 0; i < mac->mta_reg_count; i++) { 413 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 414 /* 415 * Avoid back to back register writes by adding the register 416 * read (flush). This is to protect against some strange 417 * bridge configurations that may issue Memory Write Block 418 * (MWB) to our register space. 419 */ 420 E1000_WRITE_FLUSH(hw); 421 } 422 423 /* Setup link and flow control */ 424 ret_val = mac->ops.setup_link(hw); 425 426 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 427 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 428 E1000_TXDCTL_FULL_TX_DESC_WB; 429 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 430 431 /* 432 * Clear all of the statistics registers (clear on read). It is 433 * important that we do this after we have tried to establish link 434 * because the symbol error count will increment wildly if there 435 * is no link. 436 */ 437 e1000_clear_hw_cntrs_82541(hw); 438 439 out: 440 return ret_val; 441 } 442 443 /** 444 * e1000_get_link_up_info_82541 - Report speed and duplex 445 * @hw: pointer to the HW structure 446 * @speed: pointer to speed buffer 447 * @duplex: pointer to duplex buffer 448 * 449 * Retrieve the current speed and duplex configuration. 450 **/ 451 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 452 u16 *duplex) 453 { 454 struct e1000_phy_info *phy = &hw->phy; 455 s32 ret_val; 456 u16 data; 457 458 DEBUGFUNC("e1000_get_link_up_info_82541"); 459 460 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 461 if (ret_val) 462 goto out; 463 464 if (!phy->speed_downgraded) 465 goto out; 466 467 /* 468 * IGP01 PHY may advertise full duplex operation after speed 469 * downgrade even if it is operating at half duplex. 470 * Here we set the duplex settings to match the duplex in the 471 * link partner's capabilities. 472 */ 473 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); 474 if (ret_val) 475 goto out; 476 477 if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 478 *duplex = HALF_DUPLEX; 479 } else { 480 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); 481 if (ret_val) 482 goto out; 483 484 if (*speed == SPEED_100) { 485 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 486 *duplex = HALF_DUPLEX; 487 } else if (*speed == SPEED_10) { 488 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 489 *duplex = HALF_DUPLEX; 490 } 491 } 492 493 out: 494 return ret_val; 495 } 496 497 /** 498 * e1000_phy_hw_reset_82541 - PHY hardware reset 499 * @hw: pointer to the HW structure 500 * 501 * Verify the reset block is not blocking us from resetting. Acquire 502 * semaphore (if necessary) and read/set/write the device control reset 503 * bit in the PHY. Wait the appropriate delay time for the device to 504 * reset and release the semaphore (if necessary). 505 **/ 506 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 507 { 508 s32 ret_val; 509 u32 ledctl; 510 511 DEBUGFUNC("e1000_phy_hw_reset_82541"); 512 513 ret_val = e1000_phy_hw_reset_generic(hw); 514 if (ret_val) 515 goto out; 516 517 e1000_phy_init_script_82541(hw); 518 519 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 520 /* Configure activity LED after PHY reset */ 521 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 522 ledctl &= IGP_ACTIVITY_LED_MASK; 523 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 524 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 525 } 526 527 out: 528 return ret_val; 529 } 530 531 /** 532 * e1000_setup_copper_link_82541 - Configure copper link settings 533 * @hw: pointer to the HW structure 534 * 535 * Calls the appropriate function to configure the link for auto-neg or forced 536 * speed and duplex. Then we check for link, once link is established calls 537 * to configure collision distance and flow control are called. If link is 538 * not established, we return -E1000_ERR_PHY (-2). 539 **/ 540 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) 541 { 542 struct e1000_phy_info *phy = &hw->phy; 543 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 544 s32 ret_val; 545 u32 ctrl, ledctl; 546 547 DEBUGFUNC("e1000_setup_copper_link_82541"); 548 549 ctrl = E1000_READ_REG(hw, E1000_CTRL); 550 ctrl |= E1000_CTRL_SLU; 551 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 552 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 553 554 hw->phy.reset_disable = FALSE; 555 556 /* Earlier revs of the IGP phy require us to force MDI. */ 557 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 558 dev_spec->dsp_config = e1000_dsp_config_disabled; 559 phy->mdix = 1; 560 } else { 561 dev_spec->dsp_config = e1000_dsp_config_enabled; 562 } 563 564 ret_val = e1000_copper_link_setup_igp(hw); 565 if (ret_val) 566 goto out; 567 568 if (hw->mac.autoneg) { 569 if (dev_spec->ffe_config == e1000_ffe_config_active) 570 dev_spec->ffe_config = e1000_ffe_config_enabled; 571 } 572 573 /* Configure activity LED after Phy reset */ 574 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 575 ledctl &= IGP_ACTIVITY_LED_MASK; 576 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 577 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 578 579 ret_val = e1000_setup_copper_link_generic(hw); 580 581 out: 582 return ret_val; 583 } 584 585 /** 586 * e1000_check_for_link_82541 - Check/Store link connection 587 * @hw: pointer to the HW structure 588 * 589 * This checks the link condition of the adapter and stores the 590 * results in the hw->mac structure. 591 **/ 592 static s32 e1000_check_for_link_82541(struct e1000_hw *hw) 593 { 594 struct e1000_mac_info *mac = &hw->mac; 595 s32 ret_val; 596 bool link; 597 598 DEBUGFUNC("e1000_check_for_link_82541"); 599 600 /* 601 * We only want to go out to the PHY registers to see if Auto-Neg 602 * has completed and/or if our link status has changed. The 603 * get_link_status flag is set upon receiving a Link Status 604 * Change or Rx Sequence Error interrupt. 605 */ 606 if (!mac->get_link_status) { 607 ret_val = E1000_SUCCESS; 608 goto out; 609 } 610 611 /* 612 * First we want to see if the MII Status Register reports 613 * link. If so, then we want to get the current speed/duplex 614 * of the PHY. 615 */ 616 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 617 if (ret_val) 618 goto out; 619 620 if (!link) { 621 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); 622 goto out; /* No link detected */ 623 } 624 625 mac->get_link_status = FALSE; 626 627 /* 628 * Check if there was DownShift, must be checked 629 * immediately after link-up 630 */ 631 e1000_check_downshift_generic(hw); 632 633 /* 634 * If we are forcing speed/duplex, then we simply return since 635 * we have already determined whether we have link or not. 636 */ 637 if (!mac->autoneg) { 638 ret_val = -E1000_ERR_CONFIG; 639 goto out; 640 } 641 642 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); 643 644 /* 645 * Auto-Neg is enabled. Auto Speed Detection takes care 646 * of MAC speed/duplex configuration. So we only need to 647 * configure Collision Distance in the MAC. 648 */ 649 e1000_config_collision_dist_generic(hw); 650 651 /* 652 * Configure Flow Control now that Auto-Neg has completed. 653 * First, we need to restore the desired flow control 654 * settings because we may have had to re-autoneg with a 655 * different link partner. 656 */ 657 ret_val = e1000_config_fc_after_link_up_generic(hw); 658 if (ret_val) { 659 DEBUGOUT("Error configuring flow control\n"); 660 } 661 662 out: 663 return ret_val; 664 } 665 666 /** 667 * e1000_config_dsp_after_link_change_82541 - Config DSP after link 668 * @hw: pointer to the HW structure 669 * @link_up: boolean flag for link up status 670 * 671 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 672 * at any other case. 673 * 674 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 675 * gigabit link is achieved to improve link quality. 676 **/ 677 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 678 bool link_up) 679 { 680 struct e1000_phy_info *phy = &hw->phy; 681 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 682 s32 ret_val; 683 u32 idle_errs = 0; 684 u16 phy_data, phy_saved_data, speed, duplex, i; 685 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 686 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 687 {IGP01E1000_PHY_AGC_PARAM_A, 688 IGP01E1000_PHY_AGC_PARAM_B, 689 IGP01E1000_PHY_AGC_PARAM_C, 690 IGP01E1000_PHY_AGC_PARAM_D}; 691 692 DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 693 694 if (link_up) { 695 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 696 if (ret_val) { 697 DEBUGOUT("Error getting link speed and duplex\n"); 698 goto out; 699 } 700 701 if (speed != SPEED_1000) { 702 ret_val = E1000_SUCCESS; 703 goto out; 704 } 705 706 ret_val = phy->ops.get_cable_length(hw); 707 if (ret_val) 708 goto out; 709 710 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 711 phy->min_cable_length >= 50) { 712 713 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 714 ret_val = phy->ops.read_reg(hw, 715 dsp_reg_array[i], 716 &phy_data); 717 if (ret_val) 718 goto out; 719 720 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 721 722 ret_val = phy->ops.write_reg(hw, 723 dsp_reg_array[i], 724 phy_data); 725 if (ret_val) 726 goto out; 727 } 728 dev_spec->dsp_config = e1000_dsp_config_activated; 729 } 730 731 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 732 (phy->min_cable_length >= 50)) { 733 ret_val = E1000_SUCCESS; 734 goto out; 735 } 736 737 /* clear previous idle error counts */ 738 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 739 if (ret_val) 740 goto out; 741 742 for (i = 0; i < ffe_idle_err_timeout; i++) { 743 usec_delay(1000); 744 ret_val = phy->ops.read_reg(hw, 745 PHY_1000T_STATUS, 746 &phy_data); 747 if (ret_val) 748 goto out; 749 750 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 751 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 752 dev_spec->ffe_config = e1000_ffe_config_active; 753 754 ret_val = phy->ops.write_reg(hw, 755 IGP01E1000_PHY_DSP_FFE, 756 IGP01E1000_PHY_DSP_FFE_CM_CP); 757 if (ret_val) 758 goto out; 759 break; 760 } 761 762 if (idle_errs) 763 ffe_idle_err_timeout = 764 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 765 } 766 } else { 767 if (dev_spec->dsp_config == e1000_dsp_config_activated) { 768 /* 769 * Save off the current value of register 0x2F5B 770 * to be restored at the end of the routines. 771 */ 772 ret_val = phy->ops.read_reg(hw, 773 0x2F5B, 774 &phy_saved_data); 775 if (ret_val) 776 goto out; 777 778 /* Disable the PHY transmitter */ 779 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 780 if (ret_val) 781 goto out; 782 783 msec_delay_irq(20); 784 785 ret_val = phy->ops.write_reg(hw, 786 0x0000, 787 IGP01E1000_IEEE_FORCE_GIG); 788 if (ret_val) 789 goto out; 790 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 791 ret_val = phy->ops.read_reg(hw, 792 dsp_reg_array[i], 793 &phy_data); 794 if (ret_val) 795 goto out; 796 797 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 798 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 799 800 ret_val = phy->ops.write_reg(hw, 801 dsp_reg_array[i], 802 phy_data); 803 if (ret_val) 804 goto out; 805 } 806 807 ret_val = phy->ops.write_reg(hw, 808 0x0000, 809 IGP01E1000_IEEE_RESTART_AUTONEG); 810 if (ret_val) 811 goto out; 812 813 msec_delay_irq(20); 814 815 /* Now enable the transmitter */ 816 ret_val = phy->ops.write_reg(hw, 817 0x2F5B, 818 phy_saved_data); 819 if (ret_val) 820 goto out; 821 822 dev_spec->dsp_config = e1000_dsp_config_enabled; 823 } 824 825 if (dev_spec->ffe_config != e1000_ffe_config_active) { 826 ret_val = E1000_SUCCESS; 827 goto out; 828 } 829 830 /* 831 * Save off the current value of register 0x2F5B 832 * to be restored at the end of the routines. 833 */ 834 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data); 835 if (ret_val) 836 goto out; 837 838 /* Disable the PHY transmitter */ 839 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 840 if (ret_val) 841 goto out; 842 843 msec_delay_irq(20); 844 845 ret_val = phy->ops.write_reg(hw, 846 0x0000, 847 IGP01E1000_IEEE_FORCE_GIG); 848 if (ret_val) 849 goto out; 850 851 ret_val = phy->ops.write_reg(hw, 852 IGP01E1000_PHY_DSP_FFE, 853 IGP01E1000_PHY_DSP_FFE_DEFAULT); 854 if (ret_val) 855 goto out; 856 857 ret_val = phy->ops.write_reg(hw, 858 0x0000, 859 IGP01E1000_IEEE_RESTART_AUTONEG); 860 if (ret_val) 861 goto out; 862 863 msec_delay_irq(20); 864 865 /* Now enable the transmitter */ 866 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data); 867 868 if (ret_val) 869 goto out; 870 871 dev_spec->ffe_config = e1000_ffe_config_enabled; 872 } 873 874 out: 875 return ret_val; 876 } 877 878 /** 879 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 880 * @hw: pointer to the HW structure 881 * 882 * The automatic gain control (agc) normalizes the amplitude of the 883 * received signal, adjusting for the attenuation produced by the 884 * cable. By reading the AGC registers, which represent the 885 * combination of coarse and fine gain value, the value can be put 886 * into a lookup table to obtain the approximate cable length 887 * for each channel. 888 **/ 889 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 890 { 891 struct e1000_phy_info *phy = &hw->phy; 892 s32 ret_val = E1000_SUCCESS; 893 u16 i, data; 894 u16 cur_agc_value, agc_value = 0; 895 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 896 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 897 {IGP01E1000_PHY_AGC_A, 898 IGP01E1000_PHY_AGC_B, 899 IGP01E1000_PHY_AGC_C, 900 IGP01E1000_PHY_AGC_D}; 901 902 DEBUGFUNC("e1000_get_cable_length_igp_82541"); 903 904 /* Read the AGC registers for all channels */ 905 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 906 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data); 907 if (ret_val) 908 goto out; 909 910 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 911 912 /* Bounds checking */ 913 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 914 (cur_agc_value == 0)) { 915 ret_val = -E1000_ERR_PHY; 916 goto out; 917 } 918 919 agc_value += cur_agc_value; 920 921 if (min_agc_value > cur_agc_value) 922 min_agc_value = cur_agc_value; 923 } 924 925 /* Remove the minimal AGC result for length < 50m */ 926 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 927 agc_value -= min_agc_value; 928 /* Average the three remaining channels for the length. */ 929 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 930 } else { 931 /* Average the channels for the length. */ 932 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 933 } 934 935 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 936 IGP01E1000_AGC_RANGE) 937 ? (e1000_igp_cable_length_table[agc_value] - 938 IGP01E1000_AGC_RANGE) 939 : 0; 940 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 941 IGP01E1000_AGC_RANGE; 942 943 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 944 945 out: 946 return ret_val; 947 } 948 949 /** 950 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 951 * @hw: pointer to the HW structure 952 * @active: boolean used to enable/disable lplu 953 * 954 * Success returns 0, Failure returns 1 955 * 956 * The low power link up (lplu) state is set to the power management level D3 957 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 958 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 959 * is used during Dx states where the power conservation is most important. 960 * During driver activity, SmartSpeed should be enabled so performance is 961 * maintained. 962 **/ 963 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 964 { 965 struct e1000_phy_info *phy = &hw->phy; 966 s32 ret_val; 967 u16 data; 968 969 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 970 971 switch (hw->mac.type) { 972 case e1000_82541_rev_2: 973 case e1000_82547_rev_2: 974 break; 975 default: 976 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 977 goto out; 978 break; 979 } 980 981 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); 982 if (ret_val) 983 goto out; 984 985 if (!active) { 986 data &= ~IGP01E1000_GMII_FLEX_SPD; 987 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 988 if (ret_val) 989 goto out; 990 991 /* 992 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 993 * during Dx states where the power conservation is most 994 * important. During driver activity we should enable 995 * SmartSpeed, so performance is maintained. 996 */ 997 if (phy->smart_speed == e1000_smart_speed_on) { 998 ret_val = phy->ops.read_reg(hw, 999 IGP01E1000_PHY_PORT_CONFIG, 1000 &data); 1001 if (ret_val) 1002 goto out; 1003 1004 data |= IGP01E1000_PSCFR_SMART_SPEED; 1005 ret_val = phy->ops.write_reg(hw, 1006 IGP01E1000_PHY_PORT_CONFIG, 1007 data); 1008 if (ret_val) 1009 goto out; 1010 } else if (phy->smart_speed == e1000_smart_speed_off) { 1011 ret_val = phy->ops.read_reg(hw, 1012 IGP01E1000_PHY_PORT_CONFIG, 1013 &data); 1014 if (ret_val) 1015 goto out; 1016 1017 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1018 ret_val = phy->ops.write_reg(hw, 1019 IGP01E1000_PHY_PORT_CONFIG, 1020 data); 1021 if (ret_val) 1022 goto out; 1023 } 1024 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1025 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1026 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1027 data |= IGP01E1000_GMII_FLEX_SPD; 1028 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 1029 if (ret_val) 1030 goto out; 1031 1032 /* When LPLU is enabled, we should disable SmartSpeed */ 1033 ret_val = phy->ops.read_reg(hw, 1034 IGP01E1000_PHY_PORT_CONFIG, 1035 &data); 1036 if (ret_val) 1037 goto out; 1038 1039 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1040 ret_val = phy->ops.write_reg(hw, 1041 IGP01E1000_PHY_PORT_CONFIG, 1042 data); 1043 } 1044 1045 out: 1046 return ret_val; 1047 } 1048 1049 /** 1050 * e1000_setup_led_82541 - Configures SW controllable LED 1051 * @hw: pointer to the HW structure 1052 * 1053 * This prepares the SW controllable LED for use and saves the current state 1054 * of the LED so it can be later restored. 1055 **/ 1056 static s32 e1000_setup_led_82541(struct e1000_hw *hw) 1057 { 1058 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1059 s32 ret_val; 1060 1061 DEBUGFUNC("e1000_setup_led_82541"); 1062 1063 ret_val = hw->phy.ops.read_reg(hw, 1064 IGP01E1000_GMII_FIFO, 1065 &dev_spec->spd_default); 1066 if (ret_val) 1067 goto out; 1068 1069 ret_val = hw->phy.ops.write_reg(hw, 1070 IGP01E1000_GMII_FIFO, 1071 (u16)(dev_spec->spd_default & 1072 ~IGP01E1000_GMII_SPD)); 1073 if (ret_val) 1074 goto out; 1075 1076 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1077 1078 out: 1079 return ret_val; 1080 } 1081 1082 /** 1083 * e1000_cleanup_led_82541 - Set LED config to default operation 1084 * @hw: pointer to the HW structure 1085 * 1086 * Remove the current LED configuration and set the LED configuration 1087 * to the default value, saved from the EEPROM. 1088 **/ 1089 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw) 1090 { 1091 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1092 s32 ret_val; 1093 1094 DEBUGFUNC("e1000_cleanup_led_82541"); 1095 1096 ret_val = hw->phy.ops.write_reg(hw, 1097 IGP01E1000_GMII_FIFO, 1098 dev_spec->spd_default); 1099 if (ret_val) 1100 goto out; 1101 1102 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1103 1104 out: 1105 return ret_val; 1106 } 1107 1108 /** 1109 * e1000_phy_init_script_82541 - Initialize GbE PHY 1110 * @hw: pointer to the HW structure 1111 * 1112 * Initializes the IGP PHY. 1113 **/ 1114 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw) 1115 { 1116 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1117 u32 ret_val; 1118 u16 phy_saved_data; 1119 1120 DEBUGFUNC("e1000_phy_init_script_82541"); 1121 1122 if (!dev_spec->phy_init_script) { 1123 ret_val = E1000_SUCCESS; 1124 goto out; 1125 } 1126 1127 /* Delay after phy reset to enable NVM configuration to load */ 1128 msec_delay(20); 1129 1130 /* 1131 * Save off the current value of register 0x2F5B to be restored at 1132 * the end of this routine. 1133 */ 1134 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); 1135 1136 /* Disabled the PHY transmitter */ 1137 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); 1138 1139 msec_delay(20); 1140 1141 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 1142 1143 msec_delay(5); 1144 1145 switch (hw->mac.type) { 1146 case e1000_82541: 1147 case e1000_82547: 1148 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); 1149 1150 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); 1151 1152 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); 1153 1154 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); 1155 1156 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); 1157 1158 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); 1159 1160 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); 1161 1162 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); 1163 1164 hw->phy.ops.write_reg(hw, 0x2010, 0x0008); 1165 break; 1166 case e1000_82541_rev_2: 1167 case e1000_82547_rev_2: 1168 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); 1169 break; 1170 default: 1171 break; 1172 } 1173 1174 hw->phy.ops.write_reg(hw, 0x0000, 0x3300); 1175 1176 msec_delay(20); 1177 1178 /* Now enable the transmitter */ 1179 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); 1180 1181 if (hw->mac.type == e1000_82547) { 1182 u16 fused, fine, coarse; 1183 1184 /* Move to analog registers page */ 1185 hw->phy.ops.read_reg(hw, 1186 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1187 &fused); 1188 1189 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1190 hw->phy.ops.read_reg(hw, 1191 IGP01E1000_ANALOG_FUSE_STATUS, 1192 &fused); 1193 1194 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1195 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1196 1197 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1198 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1199 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1200 } else if (coarse == 1201 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1202 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1203 1204 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1205 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1206 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1207 1208 hw->phy.ops.write_reg(hw, 1209 IGP01E1000_ANALOG_FUSE_CONTROL, 1210 fused); 1211 hw->phy.ops.write_reg(hw, 1212 IGP01E1000_ANALOG_FUSE_BYPASS, 1213 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1214 } 1215 } 1216 1217 out: 1218 return ret_val; 1219 } 1220 1221 /** 1222 * e1000_init_script_state_82541 - Enable/Disable PHY init script 1223 * @hw: pointer to the HW structure 1224 * @state: boolean value used to enable/disable PHY init script 1225 * 1226 * Allows the driver to enable/disable the PHY init script, if the PHY is an 1227 * IGP PHY. 1228 **/ 1229 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1230 { 1231 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1232 1233 DEBUGFUNC("e1000_init_script_state_82541"); 1234 1235 if (hw->phy.type != e1000_phy_igp) { 1236 DEBUGOUT("Initialization script not necessary.\n"); 1237 goto out; 1238 } 1239 1240 dev_spec->phy_init_script = state; 1241 1242 out: 1243 return; 1244 } 1245 1246 /** 1247 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1248 * @hw: pointer to the HW structure 1249 * 1250 * In the case of a PHY power down to save power, or to turn off link during a 1251 * driver unload, or wake on lan is not enabled, remove the link. 1252 **/ 1253 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1254 { 1255 /* If the management interface is not enabled, then power down */ 1256 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1257 e1000_power_down_phy_copper(hw); 1258 1259 return; 1260 } 1261 1262 /** 1263 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1264 * @hw: pointer to the HW structure 1265 * 1266 * Clears the hardware counters by reading the counter registers. 1267 **/ 1268 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1269 { 1270 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1271 1272 e1000_clear_hw_cntrs_base_generic(hw); 1273 1274 E1000_READ_REG(hw, E1000_PRC64); 1275 E1000_READ_REG(hw, E1000_PRC127); 1276 E1000_READ_REG(hw, E1000_PRC255); 1277 E1000_READ_REG(hw, E1000_PRC511); 1278 E1000_READ_REG(hw, E1000_PRC1023); 1279 E1000_READ_REG(hw, E1000_PRC1522); 1280 E1000_READ_REG(hw, E1000_PTC64); 1281 E1000_READ_REG(hw, E1000_PTC127); 1282 E1000_READ_REG(hw, E1000_PTC255); 1283 E1000_READ_REG(hw, E1000_PTC511); 1284 E1000_READ_REG(hw, E1000_PTC1023); 1285 E1000_READ_REG(hw, E1000_PTC1522); 1286 1287 E1000_READ_REG(hw, E1000_ALGNERRC); 1288 E1000_READ_REG(hw, E1000_RXERRC); 1289 E1000_READ_REG(hw, E1000_TNCRS); 1290 E1000_READ_REG(hw, E1000_CEXTERR); 1291 E1000_READ_REG(hw, E1000_TSCTC); 1292 E1000_READ_REG(hw, E1000_TSCTFC); 1293 1294 E1000_READ_REG(hw, E1000_MGTPRC); 1295 E1000_READ_REG(hw, E1000_MGTPDC); 1296 E1000_READ_REG(hw, E1000_MGTPTC); 1297 } 1298 1299 /** 1300 * e1000_read_mac_addr_82541 - Read device MAC address 1301 * @hw: pointer to the HW structure 1302 * 1303 * Reads the device MAC address from the EEPROM and stores the value. 1304 **/ 1305 static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw) 1306 { 1307 s32 ret_val = E1000_SUCCESS; 1308 u16 offset, nvm_data, i; 1309 1310 DEBUGFUNC("e1000_read_mac_addr"); 1311 1312 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 1313 offset = i >> 1; 1314 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 1315 if (ret_val) { 1316 DEBUGOUT("NVM Read Error\n"); 1317 goto out; 1318 } 1319 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 1320 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 1321 } 1322 1323 for (i = 0; i < ETH_ADDR_LEN; i++) 1324 hw->mac.addr[i] = hw->mac.perm_addr[i]; 1325 1326 out: 1327 return ret_val; 1328 } 1329 1330