xref: /freebsd/sys/dev/e1000/e1000_82541.c (revision d8b878873e7aa8df1972cc6a642804b17eb61087)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2010, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
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14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
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18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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31 
32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 /*
36  * 82541EI Gigabit Ethernet Controller
37  * 82541ER Gigabit Ethernet Controller
38  * 82541GI Gigabit Ethernet Controller
39  * 82541PI Gigabit Ethernet Controller
40  * 82547EI Gigabit Ethernet Controller
41  * 82547GI Gigabit Ethernet Controller
42  */
43 
44 #include "e1000_api.h"
45 
46 static s32  e1000_init_phy_params_82541(struct e1000_hw *hw);
47 static s32  e1000_init_nvm_params_82541(struct e1000_hw *hw);
48 static s32  e1000_init_mac_params_82541(struct e1000_hw *hw);
49 static s32  e1000_reset_hw_82541(struct e1000_hw *hw);
50 static s32  e1000_init_hw_82541(struct e1000_hw *hw);
51 static s32  e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
52                                          u16 *duplex);
53 static s32  e1000_phy_hw_reset_82541(struct e1000_hw *hw);
54 static s32  e1000_setup_copper_link_82541(struct e1000_hw *hw);
55 static s32  e1000_check_for_link_82541(struct e1000_hw *hw);
56 static s32  e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
57 static s32  e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
58                                           bool active);
59 static s32  e1000_setup_led_82541(struct e1000_hw *hw);
60 static s32  e1000_cleanup_led_82541(struct e1000_hw *hw);
61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
62 static s32  e1000_read_mac_addr_82541(struct e1000_hw *hw);
63 static s32  e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
64                                                      bool link_up);
65 static s32  e1000_phy_init_script_82541(struct e1000_hw *hw);
66 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
67 
68 static const u16 e1000_igp_cable_length_table[] =
69     { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
70       5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
71       25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
72       40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
73       60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
74       90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
75       100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
76       110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
77 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
78                 (sizeof(e1000_igp_cable_length_table) / \
79                  sizeof(e1000_igp_cable_length_table[0]))
80 
81 /**
82  *  e1000_init_phy_params_82541 - Init PHY func ptrs.
83  *  @hw: pointer to the HW structure
84  **/
85 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
86 {
87 	struct e1000_phy_info *phy = &hw->phy;
88 	s32 ret_val = E1000_SUCCESS;
89 
90 	DEBUGFUNC("e1000_init_phy_params_82541");
91 
92 	phy->addr                      = 1;
93 	phy->autoneg_mask              = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94 	phy->reset_delay_us            = 10000;
95 	phy->type                      = e1000_phy_igp;
96 
97 	/* Function Pointers */
98 	phy->ops.check_polarity        = e1000_check_polarity_igp;
99 	phy->ops.force_speed_duplex    = e1000_phy_force_speed_duplex_igp;
100 	phy->ops.get_cable_length      = e1000_get_cable_length_igp_82541;
101 	phy->ops.get_cfg_done          = e1000_get_cfg_done_generic;
102 	phy->ops.get_info              = e1000_get_phy_info_igp;
103 	phy->ops.read_reg              = e1000_read_phy_reg_igp;
104 	phy->ops.reset                 = e1000_phy_hw_reset_82541;
105 	phy->ops.set_d3_lplu_state     = e1000_set_d3_lplu_state_82541;
106 	phy->ops.write_reg             = e1000_write_phy_reg_igp;
107 	phy->ops.power_up              = e1000_power_up_phy_copper;
108 	phy->ops.power_down            = e1000_power_down_phy_copper_82541;
109 
110 	ret_val = e1000_get_phy_id(hw);
111 	if (ret_val)
112 		goto out;
113 
114 	/* Verify phy id */
115 	if (phy->id != IGP01E1000_I_PHY_ID) {
116 		ret_val = -E1000_ERR_PHY;
117 		goto out;
118 	}
119 
120 out:
121 	return ret_val;
122 }
123 
124 /**
125  *  e1000_init_nvm_params_82541 - Init NVM func ptrs.
126  *  @hw: pointer to the HW structure
127  **/
128 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
129 {
130 	struct   e1000_nvm_info *nvm = &hw->nvm;
131 	s32  ret_val = E1000_SUCCESS;
132 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
133 	u16 size;
134 
135 	DEBUGFUNC("e1000_init_nvm_params_82541");
136 
137 	switch (nvm->override) {
138 	case e1000_nvm_override_spi_large:
139 		nvm->type = e1000_nvm_eeprom_spi;
140 		eecd |= E1000_EECD_ADDR_BITS;
141 		break;
142 	case e1000_nvm_override_spi_small:
143 		nvm->type = e1000_nvm_eeprom_spi;
144 		eecd &= ~E1000_EECD_ADDR_BITS;
145 		break;
146 	case e1000_nvm_override_microwire_large:
147 		nvm->type = e1000_nvm_eeprom_microwire;
148 		eecd |= E1000_EECD_SIZE;
149 		break;
150 	case e1000_nvm_override_microwire_small:
151 		nvm->type = e1000_nvm_eeprom_microwire;
152 		eecd &= ~E1000_EECD_SIZE;
153 		break;
154 	default:
155 		nvm->type = eecd & E1000_EECD_TYPE
156 		            ? e1000_nvm_eeprom_spi
157 		            : e1000_nvm_eeprom_microwire;
158 		break;
159 	}
160 
161 	if (nvm->type == e1000_nvm_eeprom_spi) {
162 		nvm->address_bits       = (eecd & E1000_EECD_ADDR_BITS)
163 		                          ? 16 : 8;
164 		nvm->delay_usec         = 1;
165 		nvm->opcode_bits        = 8;
166 		nvm->page_size          = (eecd & E1000_EECD_ADDR_BITS)
167 		                          ? 32 : 8;
168 
169 		/* Function Pointers */
170 		nvm->ops.acquire        = e1000_acquire_nvm_generic;
171 		nvm->ops.read           = e1000_read_nvm_spi;
172 		nvm->ops.release        = e1000_release_nvm_generic;
173 		nvm->ops.update         = e1000_update_nvm_checksum_generic;
174 		nvm->ops.valid_led_default = e1000_valid_led_default_generic;
175 		nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
176 		nvm->ops.write          = e1000_write_nvm_spi;
177 
178 		/*
179 		 * nvm->word_size must be discovered after the pointers
180 		 * are set so we can verify the size from the nvm image
181 		 * itself.  Temporarily set it to a dummy value so the
182 		 * read will work.
183 		 */
184 		nvm->word_size = 64;
185 		ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
186 		if (ret_val)
187 			goto out;
188 		size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
189 		/*
190 		 * if size != 0, it can be added to a constant and become
191 		 * the left-shift value to set the word_size.  Otherwise,
192 		 * word_size stays at 64.
193 		 */
194 		if (size) {
195 			size += NVM_WORD_SIZE_BASE_SHIFT_82541;
196 			nvm->word_size = 1 << size;
197 		}
198 	} else {
199 		nvm->address_bits       = (eecd & E1000_EECD_ADDR_BITS)
200 		                          ? 8 : 6;
201 		nvm->delay_usec         = 50;
202 		nvm->opcode_bits        = 3;
203 		nvm->word_size          = (eecd & E1000_EECD_ADDR_BITS)
204 		                          ? 256 : 64;
205 
206 		/* Function Pointers */
207 		nvm->ops.acquire        = e1000_acquire_nvm_generic;
208 		nvm->ops.read           = e1000_read_nvm_microwire;
209 		nvm->ops.release        = e1000_release_nvm_generic;
210 		nvm->ops.update         = e1000_update_nvm_checksum_generic;
211 		nvm->ops.valid_led_default = e1000_valid_led_default_generic;
212 		nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
213 		nvm->ops.write          = e1000_write_nvm_microwire;
214 	}
215 
216 out:
217 	return ret_val;
218 }
219 
220 /**
221  *  e1000_init_mac_params_82541 - Init MAC func ptrs.
222  *  @hw: pointer to the HW structure
223  **/
224 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
225 {
226 	struct e1000_mac_info *mac = &hw->mac;
227 
228 	DEBUGFUNC("e1000_init_mac_params_82541");
229 
230 	/* Set media type */
231 	hw->phy.media_type = e1000_media_type_copper;
232 	/* Set mta register count */
233 	mac->mta_reg_count = 128;
234 	/* Set rar entry count */
235 	mac->rar_entry_count = E1000_RAR_ENTRIES;
236 	/* Set if part includes ASF firmware */
237 	mac->asf_firmware_present = TRUE;
238 
239 	/* Function Pointers */
240 
241 	/* bus type/speed/width */
242 	mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
243 	/* function id */
244 	mac->ops.set_lan_id = e1000_set_lan_id_single_port;
245 	/* reset */
246 	mac->ops.reset_hw = e1000_reset_hw_82541;
247 	/* hw initialization */
248 	mac->ops.init_hw = e1000_init_hw_82541;
249 	/* link setup */
250 	mac->ops.setup_link = e1000_setup_link_generic;
251 	/* physical interface link setup */
252 	mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
253 	/* check for link */
254 	mac->ops.check_for_link = e1000_check_for_link_82541;
255 	/* link info */
256 	mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
257 	/* multicast address update */
258 	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
259 	/* writing VFTA */
260 	mac->ops.write_vfta = e1000_write_vfta_generic;
261 	/* clearing VFTA */
262 	mac->ops.clear_vfta = e1000_clear_vfta_generic;
263 	/* read mac address */
264 	mac->ops.read_mac_addr = e1000_read_mac_addr_82541;
265 	/* ID LED init */
266 	mac->ops.id_led_init = e1000_id_led_init_generic;
267 	/* setup LED */
268 	mac->ops.setup_led = e1000_setup_led_82541;
269 	/* cleanup LED */
270 	mac->ops.cleanup_led = e1000_cleanup_led_82541;
271 	/* turn on/off LED */
272 	mac->ops.led_on = e1000_led_on_generic;
273 	mac->ops.led_off = e1000_led_off_generic;
274 	/* clear hardware counters */
275 	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
276 
277 	return E1000_SUCCESS;
278 }
279 
280 /**
281  *  e1000_init_function_pointers_82541 - Init func ptrs.
282  *  @hw: pointer to the HW structure
283  *
284  *  Called to initialize all function pointers and parameters.
285  **/
286 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
287 {
288 	DEBUGFUNC("e1000_init_function_pointers_82541");
289 
290 	hw->mac.ops.init_params = e1000_init_mac_params_82541;
291 	hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
292 	hw->phy.ops.init_params = e1000_init_phy_params_82541;
293 }
294 
295 /**
296  *  e1000_reset_hw_82541 - Reset hardware
297  *  @hw: pointer to the HW structure
298  *
299  *  This resets the hardware into a known state.
300  **/
301 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
302 {
303 	u32 ledctl, ctrl, icr, manc;
304 
305 	DEBUGFUNC("e1000_reset_hw_82541");
306 
307 	DEBUGOUT("Masking off all interrupts\n");
308 	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
309 
310 	E1000_WRITE_REG(hw, E1000_RCTL, 0);
311 	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
312 	E1000_WRITE_FLUSH(hw);
313 
314 	/*
315 	 * Delay to allow any outstanding PCI transactions to complete
316 	 * before resetting the device.
317 	 */
318 	msec_delay(10);
319 
320 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
321 
322 	/* Must reset the Phy before resetting the MAC */
323 	if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
324 		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
325 		msec_delay(5);
326 	}
327 
328 	DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
329 	switch (hw->mac.type) {
330 	case e1000_82541:
331 	case e1000_82541_rev_2:
332 		/*
333 		 * These controllers can't ack the 64-bit write when
334 		 * issuing the reset, so we use IO-mapping as a
335 		 * workaround to issue the reset.
336 		 */
337 		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
338 		break;
339 	default:
340 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
341 		break;
342 	}
343 
344 	/* Wait for NVM reload */
345 	msec_delay(20);
346 
347 	/* Disable HW ARPs on ASF enabled adapters */
348 	manc = E1000_READ_REG(hw, E1000_MANC);
349 	manc &= ~E1000_MANC_ARP_EN;
350 	E1000_WRITE_REG(hw, E1000_MANC, manc);
351 
352 	if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
353 		e1000_phy_init_script_82541(hw);
354 
355 		/* Configure activity LED after Phy reset */
356 		ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
357 		ledctl &= IGP_ACTIVITY_LED_MASK;
358 		ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
359 		E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
360 	}
361 
362 	/* Once again, mask the interrupts */
363 	DEBUGOUT("Masking off all interrupts\n");
364 	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
365 
366 	/* Clear any pending interrupt events. */
367 	icr = E1000_READ_REG(hw, E1000_ICR);
368 
369 	return E1000_SUCCESS;
370 }
371 
372 /**
373  *  e1000_init_hw_82541 - Initialize hardware
374  *  @hw: pointer to the HW structure
375  *
376  *  This inits the hardware readying it for operation.
377  **/
378 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
379 {
380 	struct e1000_mac_info *mac = &hw->mac;
381 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
382 	u32 i, txdctl;
383 	s32 ret_val;
384 
385 	DEBUGFUNC("e1000_init_hw_82541");
386 
387 	/* Initialize identification LED */
388 	ret_val = mac->ops.id_led_init(hw);
389 	if (ret_val) {
390 		DEBUGOUT("Error initializing identification LED\n");
391 		/* This is not fatal and we should not stop init due to this */
392 	}
393 
394 	/* Storing the Speed Power Down  value for later use */
395 	ret_val = hw->phy.ops.read_reg(hw,
396 	                               IGP01E1000_GMII_FIFO,
397 	                               &dev_spec->spd_default);
398 	if (ret_val)
399 		goto out;
400 
401 	/* Disabling VLAN filtering */
402 	DEBUGOUT("Initializing the IEEE VLAN\n");
403 	mac->ops.clear_vfta(hw);
404 
405 	/* Setup the receive address. */
406 	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
407 
408 	/* Zero out the Multicast HASH table */
409 	DEBUGOUT("Zeroing the MTA\n");
410 	for (i = 0; i < mac->mta_reg_count; i++) {
411 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
412 		/*
413 		 * Avoid back to back register writes by adding the register
414 		 * read (flush).  This is to protect against some strange
415 		 * bridge configurations that may issue Memory Write Block
416 		 * (MWB) to our register space.
417 		 */
418 		E1000_WRITE_FLUSH(hw);
419 	}
420 
421 	/* Setup link and flow control */
422 	ret_val = mac->ops.setup_link(hw);
423 
424 	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
425 	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
426 	         E1000_TXDCTL_FULL_TX_DESC_WB;
427 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
428 
429 	/*
430 	 * Clear all of the statistics registers (clear on read).  It is
431 	 * important that we do this after we have tried to establish link
432 	 * because the symbol error count will increment wildly if there
433 	 * is no link.
434 	 */
435 	e1000_clear_hw_cntrs_82541(hw);
436 
437 out:
438 	return ret_val;
439 }
440 
441 /**
442  * e1000_get_link_up_info_82541 - Report speed and duplex
443  * @hw: pointer to the HW structure
444  * @speed: pointer to speed buffer
445  * @duplex: pointer to duplex buffer
446  *
447  * Retrieve the current speed and duplex configuration.
448  **/
449 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
450                                         u16 *duplex)
451 {
452 	struct e1000_phy_info *phy = &hw->phy;
453 	s32 ret_val;
454 	u16 data;
455 
456 	DEBUGFUNC("e1000_get_link_up_info_82541");
457 
458 	ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
459 	if (ret_val)
460 		goto out;
461 
462 	if (!phy->speed_downgraded)
463 		goto out;
464 
465 	/*
466 	 * IGP01 PHY may advertise full duplex operation after speed
467 	 * downgrade even if it is operating at half duplex.
468 	 * Here we set the duplex settings to match the duplex in the
469 	 * link partner's capabilities.
470 	 */
471 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
472 	if (ret_val)
473 		goto out;
474 
475 	if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
476 		*duplex = HALF_DUPLEX;
477 	} else {
478 		ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
479 		if (ret_val)
480 			goto out;
481 
482 		if (*speed == SPEED_100) {
483 			if (!(data & NWAY_LPAR_100TX_FD_CAPS))
484 				*duplex = HALF_DUPLEX;
485 		} else if (*speed == SPEED_10) {
486 			if (!(data & NWAY_LPAR_10T_FD_CAPS))
487 				*duplex = HALF_DUPLEX;
488 		}
489 	}
490 
491 out:
492 	return ret_val;
493 }
494 
495 /**
496  *  e1000_phy_hw_reset_82541 - PHY hardware reset
497  *  @hw: pointer to the HW structure
498  *
499  *  Verify the reset block is not blocking us from resetting.  Acquire
500  *  semaphore (if necessary) and read/set/write the device control reset
501  *  bit in the PHY.  Wait the appropriate delay time for the device to
502  *  reset and release the semaphore (if necessary).
503  **/
504 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
505 {
506 	s32 ret_val;
507 	u32 ledctl;
508 
509 	DEBUGFUNC("e1000_phy_hw_reset_82541");
510 
511 	ret_val = e1000_phy_hw_reset_generic(hw);
512 	if (ret_val)
513 		goto out;
514 
515 	e1000_phy_init_script_82541(hw);
516 
517 	if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
518 		/* Configure activity LED after PHY reset */
519 		ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
520 		ledctl &= IGP_ACTIVITY_LED_MASK;
521 		ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
522 		E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
523 	}
524 
525 out:
526 	return ret_val;
527 }
528 
529 /**
530  *  e1000_setup_copper_link_82541 - Configure copper link settings
531  *  @hw: pointer to the HW structure
532  *
533  *  Calls the appropriate function to configure the link for auto-neg or forced
534  *  speed and duplex.  Then we check for link, once link is established calls
535  *  to configure collision distance and flow control are called.  If link is
536  *  not established, we return -E1000_ERR_PHY (-2).
537  **/
538 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
539 {
540 	struct e1000_phy_info *phy = &hw->phy;
541 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
542 	s32  ret_val;
543 	u32 ctrl, ledctl;
544 
545 	DEBUGFUNC("e1000_setup_copper_link_82541");
546 
547 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
548 	ctrl |= E1000_CTRL_SLU;
549 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
550 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
551 
552 	hw->phy.reset_disable = FALSE;
553 
554 	/* Earlier revs of the IGP phy require us to force MDI. */
555 	if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
556 		dev_spec->dsp_config = e1000_dsp_config_disabled;
557 		phy->mdix = 1;
558 	} else {
559 		dev_spec->dsp_config = e1000_dsp_config_enabled;
560 	}
561 
562 	ret_val = e1000_copper_link_setup_igp(hw);
563 	if (ret_val)
564 		goto out;
565 
566 	if (hw->mac.autoneg) {
567 		if (dev_spec->ffe_config == e1000_ffe_config_active)
568 			dev_spec->ffe_config = e1000_ffe_config_enabled;
569 	}
570 
571 	/* Configure activity LED after Phy reset */
572 	ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
573 	ledctl &= IGP_ACTIVITY_LED_MASK;
574 	ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
575 	E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
576 
577 	ret_val = e1000_setup_copper_link_generic(hw);
578 
579 out:
580 	return ret_val;
581 }
582 
583 /**
584  *  e1000_check_for_link_82541 - Check/Store link connection
585  *  @hw: pointer to the HW structure
586  *
587  *  This checks the link condition of the adapter and stores the
588  *  results in the hw->mac structure.
589  **/
590 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
591 {
592 	struct e1000_mac_info *mac = &hw->mac;
593 	s32 ret_val;
594 	bool link;
595 
596 	DEBUGFUNC("e1000_check_for_link_82541");
597 
598 	/*
599 	 * We only want to go out to the PHY registers to see if Auto-Neg
600 	 * has completed and/or if our link status has changed.  The
601 	 * get_link_status flag is set upon receiving a Link Status
602 	 * Change or Rx Sequence Error interrupt.
603 	 */
604 	if (!mac->get_link_status) {
605 		ret_val = E1000_SUCCESS;
606 		goto out;
607 	}
608 
609 	/*
610 	 * First we want to see if the MII Status Register reports
611 	 * link.  If so, then we want to get the current speed/duplex
612 	 * of the PHY.
613 	 */
614 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
615 	if (ret_val)
616 		goto out;
617 
618 	if (!link) {
619 		ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE);
620 		goto out; /* No link detected */
621 	}
622 
623 	mac->get_link_status = FALSE;
624 
625 	/*
626 	 * Check if there was DownShift, must be checked
627 	 * immediately after link-up
628 	 */
629 	e1000_check_downshift_generic(hw);
630 
631 	/*
632 	 * If we are forcing speed/duplex, then we simply return since
633 	 * we have already determined whether we have link or not.
634 	 */
635 	if (!mac->autoneg) {
636 		ret_val = -E1000_ERR_CONFIG;
637 		goto out;
638 	}
639 
640 	ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE);
641 
642 	/*
643 	 * Auto-Neg is enabled.  Auto Speed Detection takes care
644 	 * of MAC speed/duplex configuration.  So we only need to
645 	 * configure Collision Distance in the MAC.
646 	 */
647 	e1000_config_collision_dist_generic(hw);
648 
649 	/*
650 	 * Configure Flow Control now that Auto-Neg has completed.
651 	 * First, we need to restore the desired flow control
652 	 * settings because we may have had to re-autoneg with a
653 	 * different link partner.
654 	 */
655 	ret_val = e1000_config_fc_after_link_up_generic(hw);
656 	if (ret_val) {
657 		DEBUGOUT("Error configuring flow control\n");
658 	}
659 
660 out:
661 	return ret_val;
662 }
663 
664 /**
665  *  e1000_config_dsp_after_link_change_82541 - Config DSP after link
666  *  @hw: pointer to the HW structure
667  *  @link_up: boolean flag for link up status
668  *
669  *  Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
670  *  at any other case.
671  *
672  *  82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
673  *  gigabit link is achieved to improve link quality.
674  **/
675 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
676                                                     bool link_up)
677 {
678 	struct e1000_phy_info *phy = &hw->phy;
679 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
680 	s32 ret_val;
681 	u32 idle_errs = 0;
682 	u16 phy_data, phy_saved_data, speed, duplex, i;
683 	u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
684 	u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
685 	                                           {IGP01E1000_PHY_AGC_PARAM_A,
686 	                                            IGP01E1000_PHY_AGC_PARAM_B,
687 	                                            IGP01E1000_PHY_AGC_PARAM_C,
688 	                                            IGP01E1000_PHY_AGC_PARAM_D};
689 
690 	DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
691 
692 	if (link_up) {
693 		ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
694 		if (ret_val) {
695 			DEBUGOUT("Error getting link speed and duplex\n");
696 			goto out;
697 		}
698 
699 		if (speed != SPEED_1000) {
700 			ret_val = E1000_SUCCESS;
701 			goto out;
702 		}
703 
704 		ret_val = phy->ops.get_cable_length(hw);
705 		if (ret_val)
706 			goto out;
707 
708 		if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
709 		    phy->min_cable_length >= 50) {
710 
711 			for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
712 				ret_val = phy->ops.read_reg(hw,
713 				                            dsp_reg_array[i],
714 				                            &phy_data);
715 				if (ret_val)
716 					goto out;
717 
718 				phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
719 
720 				ret_val = phy->ops.write_reg(hw,
721 				                             dsp_reg_array[i],
722 				                             phy_data);
723 				if (ret_val)
724 					goto out;
725 			}
726 			dev_spec->dsp_config = e1000_dsp_config_activated;
727 		}
728 
729 		if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
730 		    (phy->min_cable_length >= 50)) {
731 			ret_val = E1000_SUCCESS;
732 			goto out;
733 		}
734 
735 		/* clear previous idle error counts */
736 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
737 		if (ret_val)
738 			goto out;
739 
740 		for (i = 0; i < ffe_idle_err_timeout; i++) {
741 			usec_delay(1000);
742 			ret_val = phy->ops.read_reg(hw,
743 			                            PHY_1000T_STATUS,
744 			                            &phy_data);
745 			if (ret_val)
746 				goto out;
747 
748 			idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
749 			if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
750 				dev_spec->ffe_config = e1000_ffe_config_active;
751 
752 				ret_val = phy->ops.write_reg(hw,
753 				                  IGP01E1000_PHY_DSP_FFE,
754 				                  IGP01E1000_PHY_DSP_FFE_CM_CP);
755 				if (ret_val)
756 					goto out;
757 				break;
758 			}
759 
760 			if (idle_errs)
761 				ffe_idle_err_timeout =
762 				                 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
763 		}
764 	} else {
765 		if (dev_spec->dsp_config == e1000_dsp_config_activated) {
766 			/*
767 			 * Save off the current value of register 0x2F5B
768 			 * to be restored at the end of the routines.
769 			 */
770 			ret_val = phy->ops.read_reg(hw,
771 			                            0x2F5B,
772 			                            &phy_saved_data);
773 			if (ret_val)
774 				goto out;
775 
776 			/* Disable the PHY transmitter */
777 			ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
778 			if (ret_val)
779 				goto out;
780 
781 			msec_delay_irq(20);
782 
783 			ret_val = phy->ops.write_reg(hw,
784 			                             0x0000,
785 			                             IGP01E1000_IEEE_FORCE_GIG);
786 			if (ret_val)
787 				goto out;
788 			for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
789 				ret_val = phy->ops.read_reg(hw,
790 				                            dsp_reg_array[i],
791 				                            &phy_data);
792 				if (ret_val)
793 					goto out;
794 
795 				phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
796 				phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
797 
798 				ret_val = phy->ops.write_reg(hw,
799 				                             dsp_reg_array[i],
800 				                             phy_data);
801 				if (ret_val)
802 					goto out;
803 			}
804 
805 			ret_val = phy->ops.write_reg(hw,
806 			                       0x0000,
807 			                       IGP01E1000_IEEE_RESTART_AUTONEG);
808 			if (ret_val)
809 				goto out;
810 
811 			msec_delay_irq(20);
812 
813 			/* Now enable the transmitter */
814 			ret_val = phy->ops.write_reg(hw,
815 			                             0x2F5B,
816 			                             phy_saved_data);
817 			if (ret_val)
818 				goto out;
819 
820 			dev_spec->dsp_config = e1000_dsp_config_enabled;
821 		}
822 
823 		if (dev_spec->ffe_config != e1000_ffe_config_active) {
824 			ret_val = E1000_SUCCESS;
825 			goto out;
826 		}
827 
828 		/*
829 		 * Save off the current value of register 0x2F5B
830 		 * to be restored at the end of the routines.
831 		 */
832 		ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
833 		if (ret_val)
834 			goto out;
835 
836 		/* Disable the PHY transmitter */
837 		ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
838 		if (ret_val)
839 			goto out;
840 
841 		msec_delay_irq(20);
842 
843 		ret_val = phy->ops.write_reg(hw,
844 		                             0x0000,
845 		                             IGP01E1000_IEEE_FORCE_GIG);
846 		if (ret_val)
847 			goto out;
848 
849 		ret_val = phy->ops.write_reg(hw,
850 		                             IGP01E1000_PHY_DSP_FFE,
851 		                             IGP01E1000_PHY_DSP_FFE_DEFAULT);
852 		if (ret_val)
853 			goto out;
854 
855 		ret_val = phy->ops.write_reg(hw,
856 		                             0x0000,
857 		                             IGP01E1000_IEEE_RESTART_AUTONEG);
858 		if (ret_val)
859 			goto out;
860 
861 		msec_delay_irq(20);
862 
863 		/* Now enable the transmitter */
864 		ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
865 
866 		if (ret_val)
867 			goto out;
868 
869 		dev_spec->ffe_config = e1000_ffe_config_enabled;
870 	}
871 
872 out:
873 	return ret_val;
874 }
875 
876 /**
877  *  e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
878  *  @hw: pointer to the HW structure
879  *
880  *  The automatic gain control (agc) normalizes the amplitude of the
881  *  received signal, adjusting for the attenuation produced by the
882  *  cable.  By reading the AGC registers, which represent the
883  *  combination of coarse and fine gain value, the value can be put
884  *  into a lookup table to obtain the approximate cable length
885  *  for each channel.
886  **/
887 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
888 {
889 	struct e1000_phy_info *phy = &hw->phy;
890 	s32 ret_val = E1000_SUCCESS;
891 	u16 i, data;
892 	u16 cur_agc_value, agc_value = 0;
893 	u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
894 	u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
895 	                                                 {IGP01E1000_PHY_AGC_A,
896 	                                                  IGP01E1000_PHY_AGC_B,
897 	                                                  IGP01E1000_PHY_AGC_C,
898 	                                                  IGP01E1000_PHY_AGC_D};
899 
900 	DEBUGFUNC("e1000_get_cable_length_igp_82541");
901 
902 	/* Read the AGC registers for all channels */
903 	for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
904 		ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
905 		if (ret_val)
906 			goto out;
907 
908 		cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
909 
910 		/* Bounds checking */
911 		if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
912 		    (cur_agc_value == 0)) {
913 			ret_val = -E1000_ERR_PHY;
914 			goto out;
915 		}
916 
917 		agc_value += cur_agc_value;
918 
919 		if (min_agc_value > cur_agc_value)
920 			min_agc_value = cur_agc_value;
921 	}
922 
923 	/* Remove the minimal AGC result for length < 50m */
924 	if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
925 		agc_value -= min_agc_value;
926 		/* Average the three remaining channels for the length. */
927 		agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
928 	} else {
929 		/* Average the channels for the length. */
930 		agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
931 	}
932 
933 	phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
934 	                         IGP01E1000_AGC_RANGE)
935 	                        ? (e1000_igp_cable_length_table[agc_value] -
936 	                           IGP01E1000_AGC_RANGE)
937 	                        : 0;
938 	phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
939 	                        IGP01E1000_AGC_RANGE;
940 
941 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
942 
943 out:
944 	return ret_val;
945 }
946 
947 /**
948  *  e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
949  *  @hw: pointer to the HW structure
950  *  @active: boolean used to enable/disable lplu
951  *
952  *  Success returns 0, Failure returns 1
953  *
954  *  The low power link up (lplu) state is set to the power management level D3
955  *  and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
956  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
957  *  is used during Dx states where the power conservation is most important.
958  *  During driver activity, SmartSpeed should be enabled so performance is
959  *  maintained.
960  **/
961 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
962 {
963 	struct e1000_phy_info *phy = &hw->phy;
964 	s32 ret_val;
965 	u16 data;
966 
967 	DEBUGFUNC("e1000_set_d3_lplu_state_82541");
968 
969 	switch (hw->mac.type) {
970 	case e1000_82541_rev_2:
971 	case e1000_82547_rev_2:
972 		break;
973 	default:
974 		ret_val = e1000_set_d3_lplu_state_generic(hw, active);
975 		goto out;
976 		break;
977 	}
978 
979 	ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
980 	if (ret_val)
981 		goto out;
982 
983 	if (!active) {
984 		data &= ~IGP01E1000_GMII_FLEX_SPD;
985 		ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
986 		if (ret_val)
987 			goto out;
988 
989 		/*
990 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
991 		 * during Dx states where the power conservation is most
992 		 * important.  During driver activity we should enable
993 		 * SmartSpeed, so performance is maintained.
994 		 */
995 		if (phy->smart_speed == e1000_smart_speed_on) {
996 			ret_val = phy->ops.read_reg(hw,
997 			                            IGP01E1000_PHY_PORT_CONFIG,
998 			                            &data);
999 			if (ret_val)
1000 				goto out;
1001 
1002 			data |= IGP01E1000_PSCFR_SMART_SPEED;
1003 			ret_val = phy->ops.write_reg(hw,
1004 			                             IGP01E1000_PHY_PORT_CONFIG,
1005 			                             data);
1006 			if (ret_val)
1007 				goto out;
1008 		} else if (phy->smart_speed == e1000_smart_speed_off) {
1009 			ret_val = phy->ops.read_reg(hw,
1010 			                            IGP01E1000_PHY_PORT_CONFIG,
1011 			                            &data);
1012 			if (ret_val)
1013 				goto out;
1014 
1015 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1016 			ret_val = phy->ops.write_reg(hw,
1017 			                             IGP01E1000_PHY_PORT_CONFIG,
1018 			                             data);
1019 			if (ret_val)
1020 				goto out;
1021 		}
1022 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1023 	           (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1024 	           (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1025 		data |= IGP01E1000_GMII_FLEX_SPD;
1026 		ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1027 		if (ret_val)
1028 			goto out;
1029 
1030 		/* When LPLU is enabled, we should disable SmartSpeed */
1031 		ret_val = phy->ops.read_reg(hw,
1032 		                            IGP01E1000_PHY_PORT_CONFIG,
1033 		                            &data);
1034 		if (ret_val)
1035 			goto out;
1036 
1037 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1038 		ret_val = phy->ops.write_reg(hw,
1039 		                             IGP01E1000_PHY_PORT_CONFIG,
1040 		                             data);
1041 	}
1042 
1043 out:
1044 	return ret_val;
1045 }
1046 
1047 /**
1048  *  e1000_setup_led_82541 - Configures SW controllable LED
1049  *  @hw: pointer to the HW structure
1050  *
1051  *  This prepares the SW controllable LED for use and saves the current state
1052  *  of the LED so it can be later restored.
1053  **/
1054 static s32 e1000_setup_led_82541(struct e1000_hw *hw)
1055 {
1056 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1057 	s32 ret_val;
1058 
1059 	DEBUGFUNC("e1000_setup_led_82541");
1060 
1061 	ret_val = hw->phy.ops.read_reg(hw,
1062 	                               IGP01E1000_GMII_FIFO,
1063 	                               &dev_spec->spd_default);
1064 	if (ret_val)
1065 		goto out;
1066 
1067 	ret_val = hw->phy.ops.write_reg(hw,
1068 	                                IGP01E1000_GMII_FIFO,
1069 	                                (u16)(dev_spec->spd_default &
1070 	                                        ~IGP01E1000_GMII_SPD));
1071 	if (ret_val)
1072 		goto out;
1073 
1074 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1075 
1076 out:
1077 	return ret_val;
1078 }
1079 
1080 /**
1081  *  e1000_cleanup_led_82541 - Set LED config to default operation
1082  *  @hw: pointer to the HW structure
1083  *
1084  *  Remove the current LED configuration and set the LED configuration
1085  *  to the default value, saved from the EEPROM.
1086  **/
1087 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1088 {
1089 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1090 	s32 ret_val;
1091 
1092 	DEBUGFUNC("e1000_cleanup_led_82541");
1093 
1094 	ret_val = hw->phy.ops.write_reg(hw,
1095 	                                IGP01E1000_GMII_FIFO,
1096 	                                dev_spec->spd_default);
1097 	if (ret_val)
1098 		goto out;
1099 
1100 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1101 
1102 out:
1103 	return ret_val;
1104 }
1105 
1106 /**
1107  *  e1000_phy_init_script_82541 - Initialize GbE PHY
1108  *  @hw: pointer to the HW structure
1109  *
1110  *  Initializes the IGP PHY.
1111  **/
1112 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1113 {
1114 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1115 	u32 ret_val;
1116 	u16 phy_saved_data;
1117 
1118 	DEBUGFUNC("e1000_phy_init_script_82541");
1119 
1120 	if (!dev_spec->phy_init_script) {
1121 		ret_val = E1000_SUCCESS;
1122 		goto out;
1123 	}
1124 
1125 	/* Delay after phy reset to enable NVM configuration to load */
1126 	msec_delay(20);
1127 
1128 	/*
1129 	 * Save off the current value of register 0x2F5B to be restored at
1130 	 * the end of this routine.
1131 	 */
1132 	ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1133 
1134 	/* Disabled the PHY transmitter */
1135 	hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1136 
1137 	msec_delay(20);
1138 
1139 	hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1140 
1141 	msec_delay(5);
1142 
1143 	switch (hw->mac.type) {
1144 	case e1000_82541:
1145 	case e1000_82547:
1146 		hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1147 
1148 		hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1149 
1150 		hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1151 
1152 		hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1153 
1154 		hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1155 
1156 		hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1157 
1158 		hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1159 
1160 		hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1161 
1162 		hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1163 		break;
1164 	case e1000_82541_rev_2:
1165 	case e1000_82547_rev_2:
1166 		hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1167 		break;
1168 	default:
1169 		break;
1170 	}
1171 
1172 	hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1173 
1174 	msec_delay(20);
1175 
1176 	/* Now enable the transmitter */
1177 	hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1178 
1179 	if (hw->mac.type == e1000_82547) {
1180 		u16 fused, fine, coarse;
1181 
1182 		/* Move to analog registers page */
1183 		hw->phy.ops.read_reg(hw,
1184 		                  IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1185 		                  &fused);
1186 
1187 		if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1188 			hw->phy.ops.read_reg(hw,
1189 			                  IGP01E1000_ANALOG_FUSE_STATUS,
1190 			                  &fused);
1191 
1192 			fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1193 			coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1194 
1195 			if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1196 				coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1197 				fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1198 			} else if (coarse ==
1199 			           IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1200 				fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1201 
1202 			fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1203 			        (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1204 			        (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1205 
1206 			hw->phy.ops.write_reg(hw,
1207 			                   IGP01E1000_ANALOG_FUSE_CONTROL,
1208 			                   fused);
1209 			hw->phy.ops.write_reg(hw,
1210 			              IGP01E1000_ANALOG_FUSE_BYPASS,
1211 			              IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1212 		}
1213 	}
1214 
1215 out:
1216 	return ret_val;
1217 }
1218 
1219 /**
1220  *  e1000_init_script_state_82541 - Enable/Disable PHY init script
1221  *  @hw: pointer to the HW structure
1222  *  @state: boolean value used to enable/disable PHY init script
1223  *
1224  *  Allows the driver to enable/disable the PHY init script, if the PHY is an
1225  *  IGP PHY.
1226  **/
1227 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1228 {
1229 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1230 
1231 	DEBUGFUNC("e1000_init_script_state_82541");
1232 
1233 	if (hw->phy.type != e1000_phy_igp) {
1234 		DEBUGOUT("Initialization script not necessary.\n");
1235 		goto out;
1236 	}
1237 
1238 	dev_spec->phy_init_script = state;
1239 
1240 out:
1241 	return;
1242 }
1243 
1244 /**
1245  * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1246  * @hw: pointer to the HW structure
1247  *
1248  * In the case of a PHY power down to save power, or to turn off link during a
1249  * driver unload, or wake on lan is not enabled, remove the link.
1250  **/
1251 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1252 {
1253 	/* If the management interface is not enabled, then power down */
1254 	if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1255 		e1000_power_down_phy_copper(hw);
1256 
1257 	return;
1258 }
1259 
1260 /**
1261  *  e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1262  *  @hw: pointer to the HW structure
1263  *
1264  *  Clears the hardware counters by reading the counter registers.
1265  **/
1266 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1267 {
1268 	DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1269 
1270 	e1000_clear_hw_cntrs_base_generic(hw);
1271 
1272 	E1000_READ_REG(hw, E1000_PRC64);
1273 	E1000_READ_REG(hw, E1000_PRC127);
1274 	E1000_READ_REG(hw, E1000_PRC255);
1275 	E1000_READ_REG(hw, E1000_PRC511);
1276 	E1000_READ_REG(hw, E1000_PRC1023);
1277 	E1000_READ_REG(hw, E1000_PRC1522);
1278 	E1000_READ_REG(hw, E1000_PTC64);
1279 	E1000_READ_REG(hw, E1000_PTC127);
1280 	E1000_READ_REG(hw, E1000_PTC255);
1281 	E1000_READ_REG(hw, E1000_PTC511);
1282 	E1000_READ_REG(hw, E1000_PTC1023);
1283 	E1000_READ_REG(hw, E1000_PTC1522);
1284 
1285 	E1000_READ_REG(hw, E1000_ALGNERRC);
1286 	E1000_READ_REG(hw, E1000_RXERRC);
1287 	E1000_READ_REG(hw, E1000_TNCRS);
1288 	E1000_READ_REG(hw, E1000_CEXTERR);
1289 	E1000_READ_REG(hw, E1000_TSCTC);
1290 	E1000_READ_REG(hw, E1000_TSCTFC);
1291 
1292 	E1000_READ_REG(hw, E1000_MGTPRC);
1293 	E1000_READ_REG(hw, E1000_MGTPDC);
1294 	E1000_READ_REG(hw, E1000_MGTPTC);
1295 }
1296 
1297 /**
1298  *  e1000_read_mac_addr_82541 - Read device MAC address
1299  *  @hw: pointer to the HW structure
1300  *
1301  *  Reads the device MAC address from the EEPROM and stores the value.
1302  **/
1303 static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw)
1304 {
1305 	s32  ret_val = E1000_SUCCESS;
1306 	u16 offset, nvm_data, i;
1307 
1308 	DEBUGFUNC("e1000_read_mac_addr");
1309 
1310 	for (i = 0; i < ETH_ADDR_LEN; i += 2) {
1311 		offset = i >> 1;
1312 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
1313 		if (ret_val) {
1314 			DEBUGOUT("NVM Read Error\n");
1315 			goto out;
1316 		}
1317 		hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
1318 		hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
1319 	}
1320 
1321 	for (i = 0; i < ETH_ADDR_LEN; i++)
1322 		hw->mac.addr[i] = hw->mac.perm_addr[i];
1323 
1324 out:
1325 	return ret_val;
1326 }
1327 
1328