1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82541EI Gigabit Ethernet Controller 37 * 82541ER Gigabit Ethernet Controller 38 * 82541GI Gigabit Ethernet Controller 39 * 82541PI Gigabit Ethernet Controller 40 * 82547EI Gigabit Ethernet Controller 41 * 82547GI Gigabit Ethernet Controller 42 */ 43 44 #include "e1000_api.h" 45 46 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 47 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 48 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 49 static s32 e1000_reset_hw_82541(struct e1000_hw *hw); 50 static s32 e1000_init_hw_82541(struct e1000_hw *hw); 51 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 52 u16 *duplex); 53 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 54 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 55 static s32 e1000_check_for_link_82541(struct e1000_hw *hw); 56 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 57 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 58 bool active); 59 static s32 e1000_setup_led_82541(struct e1000_hw *hw); 60 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 62 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 63 bool link_up); 64 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 65 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 66 67 static const u16 e1000_igp_cable_length_table[] = 68 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 69 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 70 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 71 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 72 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 73 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 74 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 75 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 76 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 77 (sizeof(e1000_igp_cable_length_table) / \ 78 sizeof(e1000_igp_cable_length_table[0])) 79 80 /** 81 * e1000_init_phy_params_82541 - Init PHY func ptrs. 82 * @hw: pointer to the HW structure 83 **/ 84 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw) 85 { 86 struct e1000_phy_info *phy = &hw->phy; 87 s32 ret_val = E1000_SUCCESS; 88 89 DEBUGFUNC("e1000_init_phy_params_82541"); 90 91 phy->addr = 1; 92 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 93 phy->reset_delay_us = 10000; 94 phy->type = e1000_phy_igp; 95 96 /* Function Pointers */ 97 phy->ops.check_polarity = e1000_check_polarity_igp; 98 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 99 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; 100 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 101 phy->ops.get_info = e1000_get_phy_info_igp; 102 phy->ops.read_reg = e1000_read_phy_reg_igp; 103 phy->ops.reset = e1000_phy_hw_reset_82541; 104 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 105 phy->ops.write_reg = e1000_write_phy_reg_igp; 106 phy->ops.power_up = e1000_power_up_phy_copper; 107 phy->ops.power_down = e1000_power_down_phy_copper_82541; 108 109 ret_val = e1000_get_phy_id(hw); 110 if (ret_val) 111 goto out; 112 113 /* Verify phy id */ 114 if (phy->id != IGP01E1000_I_PHY_ID) { 115 ret_val = -E1000_ERR_PHY; 116 goto out; 117 } 118 119 out: 120 return ret_val; 121 } 122 123 /** 124 * e1000_init_nvm_params_82541 - Init NVM func ptrs. 125 * @hw: pointer to the HW structure 126 **/ 127 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) 128 { 129 struct e1000_nvm_info *nvm = &hw->nvm; 130 s32 ret_val = E1000_SUCCESS; 131 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 132 u16 size; 133 134 DEBUGFUNC("e1000_init_nvm_params_82541"); 135 136 switch (nvm->override) { 137 case e1000_nvm_override_spi_large: 138 nvm->type = e1000_nvm_eeprom_spi; 139 eecd |= E1000_EECD_ADDR_BITS; 140 break; 141 case e1000_nvm_override_spi_small: 142 nvm->type = e1000_nvm_eeprom_spi; 143 eecd &= ~E1000_EECD_ADDR_BITS; 144 break; 145 case e1000_nvm_override_microwire_large: 146 nvm->type = e1000_nvm_eeprom_microwire; 147 eecd |= E1000_EECD_SIZE; 148 break; 149 case e1000_nvm_override_microwire_small: 150 nvm->type = e1000_nvm_eeprom_microwire; 151 eecd &= ~E1000_EECD_SIZE; 152 break; 153 default: 154 nvm->type = eecd & E1000_EECD_TYPE 155 ? e1000_nvm_eeprom_spi 156 : e1000_nvm_eeprom_microwire; 157 break; 158 } 159 160 if (nvm->type == e1000_nvm_eeprom_spi) { 161 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 162 ? 16 : 8; 163 nvm->delay_usec = 1; 164 nvm->opcode_bits = 8; 165 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 166 ? 32 : 8; 167 168 /* Function Pointers */ 169 nvm->ops.acquire = e1000_acquire_nvm_generic; 170 nvm->ops.read = e1000_read_nvm_spi; 171 nvm->ops.release = e1000_release_nvm_generic; 172 nvm->ops.update = e1000_update_nvm_checksum_generic; 173 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 174 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 175 nvm->ops.write = e1000_write_nvm_spi; 176 177 /* 178 * nvm->word_size must be discovered after the pointers 179 * are set so we can verify the size from the nvm image 180 * itself. Temporarily set it to a dummy value so the 181 * read will work. 182 */ 183 nvm->word_size = 64; 184 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); 185 if (ret_val) 186 goto out; 187 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 188 /* 189 * if size != 0, it can be added to a constant and become 190 * the left-shift value to set the word_size. Otherwise, 191 * word_size stays at 64. 192 */ 193 if (size) { 194 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 195 nvm->word_size = 1 << size; 196 } 197 } else { 198 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 199 ? 8 : 6; 200 nvm->delay_usec = 50; 201 nvm->opcode_bits = 3; 202 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 203 ? 256 : 64; 204 205 /* Function Pointers */ 206 nvm->ops.acquire = e1000_acquire_nvm_generic; 207 nvm->ops.read = e1000_read_nvm_microwire; 208 nvm->ops.release = e1000_release_nvm_generic; 209 nvm->ops.update = e1000_update_nvm_checksum_generic; 210 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 211 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 212 nvm->ops.write = e1000_write_nvm_microwire; 213 } 214 215 out: 216 return ret_val; 217 } 218 219 /** 220 * e1000_init_mac_params_82541 - Init MAC func ptrs. 221 * @hw: pointer to the HW structure 222 **/ 223 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw) 224 { 225 struct e1000_mac_info *mac = &hw->mac; 226 227 DEBUGFUNC("e1000_init_mac_params_82541"); 228 229 /* Set media type */ 230 hw->phy.media_type = e1000_media_type_copper; 231 /* Set mta register count */ 232 mac->mta_reg_count = 128; 233 /* Set rar entry count */ 234 mac->rar_entry_count = E1000_RAR_ENTRIES; 235 /* Set if part includes ASF firmware */ 236 mac->asf_firmware_present = TRUE; 237 238 /* Function Pointers */ 239 240 /* bus type/speed/width */ 241 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 242 /* function id */ 243 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 244 /* reset */ 245 mac->ops.reset_hw = e1000_reset_hw_82541; 246 /* hw initialization */ 247 mac->ops.init_hw = e1000_init_hw_82541; 248 /* link setup */ 249 mac->ops.setup_link = e1000_setup_link_generic; 250 /* physical interface link setup */ 251 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; 252 /* check for link */ 253 mac->ops.check_for_link = e1000_check_for_link_82541; 254 /* link info */ 255 mac->ops.get_link_up_info = e1000_get_link_up_info_82541; 256 /* multicast address update */ 257 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 258 /* writing VFTA */ 259 mac->ops.write_vfta = e1000_write_vfta_generic; 260 /* clearing VFTA */ 261 mac->ops.clear_vfta = e1000_clear_vfta_generic; 262 /* setting MTA */ 263 mac->ops.mta_set = e1000_mta_set_generic; 264 /* ID LED init */ 265 mac->ops.id_led_init = e1000_id_led_init_generic; 266 /* setup LED */ 267 mac->ops.setup_led = e1000_setup_led_82541; 268 /* cleanup LED */ 269 mac->ops.cleanup_led = e1000_cleanup_led_82541; 270 /* turn on/off LED */ 271 mac->ops.led_on = e1000_led_on_generic; 272 mac->ops.led_off = e1000_led_off_generic; 273 /* clear hardware counters */ 274 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 275 276 return E1000_SUCCESS; 277 } 278 279 /** 280 * e1000_init_function_pointers_82541 - Init func ptrs. 281 * @hw: pointer to the HW structure 282 * 283 * Called to initialize all function pointers and parameters. 284 **/ 285 void e1000_init_function_pointers_82541(struct e1000_hw *hw) 286 { 287 DEBUGFUNC("e1000_init_function_pointers_82541"); 288 289 hw->mac.ops.init_params = e1000_init_mac_params_82541; 290 hw->nvm.ops.init_params = e1000_init_nvm_params_82541; 291 hw->phy.ops.init_params = e1000_init_phy_params_82541; 292 } 293 294 /** 295 * e1000_reset_hw_82541 - Reset hardware 296 * @hw: pointer to the HW structure 297 * 298 * This resets the hardware into a known state. 299 **/ 300 static s32 e1000_reset_hw_82541(struct e1000_hw *hw) 301 { 302 u32 ledctl, ctrl, icr, manc; 303 304 DEBUGFUNC("e1000_reset_hw_82541"); 305 306 DEBUGOUT("Masking off all interrupts\n"); 307 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 308 309 E1000_WRITE_REG(hw, E1000_RCTL, 0); 310 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 311 E1000_WRITE_FLUSH(hw); 312 313 /* 314 * Delay to allow any outstanding PCI transactions to complete 315 * before resetting the device. 316 */ 317 msec_delay(10); 318 319 ctrl = E1000_READ_REG(hw, E1000_CTRL); 320 321 /* Must reset the Phy before resetting the MAC */ 322 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 323 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 324 msec_delay(5); 325 } 326 327 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 328 switch (hw->mac.type) { 329 case e1000_82541: 330 case e1000_82541_rev_2: 331 /* 332 * These controllers can't ack the 64-bit write when 333 * issuing the reset, so we use IO-mapping as a 334 * workaround to issue the reset. 335 */ 336 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 337 break; 338 default: 339 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 340 break; 341 } 342 343 /* Wait for NVM reload */ 344 msec_delay(20); 345 346 /* Disable HW ARPs on ASF enabled adapters */ 347 manc = E1000_READ_REG(hw, E1000_MANC); 348 manc &= ~E1000_MANC_ARP_EN; 349 E1000_WRITE_REG(hw, E1000_MANC, manc); 350 351 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 352 e1000_phy_init_script_82541(hw); 353 354 /* Configure activity LED after Phy reset */ 355 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 356 ledctl &= IGP_ACTIVITY_LED_MASK; 357 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 358 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 359 } 360 361 /* Once again, mask the interrupts */ 362 DEBUGOUT("Masking off all interrupts\n"); 363 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 364 365 /* Clear any pending interrupt events. */ 366 icr = E1000_READ_REG(hw, E1000_ICR); 367 368 return E1000_SUCCESS; 369 } 370 371 /** 372 * e1000_init_hw_82541 - Initialize hardware 373 * @hw: pointer to the HW structure 374 * 375 * This inits the hardware readying it for operation. 376 **/ 377 static s32 e1000_init_hw_82541(struct e1000_hw *hw) 378 { 379 struct e1000_mac_info *mac = &hw->mac; 380 u32 i, txdctl; 381 s32 ret_val; 382 383 DEBUGFUNC("e1000_init_hw_82541"); 384 385 /* Initialize identification LED */ 386 ret_val = mac->ops.id_led_init(hw); 387 if (ret_val) { 388 DEBUGOUT("Error initializing identification LED\n"); 389 /* This is not fatal and we should not stop init due to this */ 390 } 391 392 /* Disabling VLAN filtering */ 393 DEBUGOUT("Initializing the IEEE VLAN\n"); 394 mac->ops.clear_vfta(hw); 395 396 /* Setup the receive address. */ 397 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 398 399 /* Zero out the Multicast HASH table */ 400 DEBUGOUT("Zeroing the MTA\n"); 401 for (i = 0; i < mac->mta_reg_count; i++) { 402 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 403 /* 404 * Avoid back to back register writes by adding the register 405 * read (flush). This is to protect against some strange 406 * bridge configurations that may issue Memory Write Block 407 * (MWB) to our register space. 408 */ 409 E1000_WRITE_FLUSH(hw); 410 } 411 412 /* Setup link and flow control */ 413 ret_val = mac->ops.setup_link(hw); 414 415 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 416 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 417 E1000_TXDCTL_FULL_TX_DESC_WB; 418 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 419 420 /* 421 * Clear all of the statistics registers (clear on read). It is 422 * important that we do this after we have tried to establish link 423 * because the symbol error count will increment wildly if there 424 * is no link. 425 */ 426 e1000_clear_hw_cntrs_82541(hw); 427 428 return ret_val; 429 } 430 431 /** 432 * e1000_get_link_up_info_82541 - Report speed and duplex 433 * @hw: pointer to the HW structure 434 * @speed: pointer to speed buffer 435 * @duplex: pointer to duplex buffer 436 * 437 * Retrieve the current speed and duplex configuration. 438 **/ 439 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 440 u16 *duplex) 441 { 442 struct e1000_phy_info *phy = &hw->phy; 443 s32 ret_val; 444 u16 data; 445 446 DEBUGFUNC("e1000_get_link_up_info_82541"); 447 448 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 449 if (ret_val) 450 goto out; 451 452 if (!phy->speed_downgraded) 453 goto out; 454 455 /* 456 * IGP01 PHY may advertise full duplex operation after speed 457 * downgrade even if it is operating at half duplex. 458 * Here we set the duplex settings to match the duplex in the 459 * link partner's capabilities. 460 */ 461 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); 462 if (ret_val) 463 goto out; 464 465 if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 466 *duplex = HALF_DUPLEX; 467 } else { 468 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); 469 if (ret_val) 470 goto out; 471 472 if (*speed == SPEED_100) { 473 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 474 *duplex = HALF_DUPLEX; 475 } else if (*speed == SPEED_10) { 476 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 477 *duplex = HALF_DUPLEX; 478 } 479 } 480 481 out: 482 return ret_val; 483 } 484 485 /** 486 * e1000_phy_hw_reset_82541 - PHY hardware reset 487 * @hw: pointer to the HW structure 488 * 489 * Verify the reset block is not blocking us from resetting. Acquire 490 * semaphore (if necessary) and read/set/write the device control reset 491 * bit in the PHY. Wait the appropriate delay time for the device to 492 * reset and release the semaphore (if necessary). 493 **/ 494 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 495 { 496 s32 ret_val; 497 u32 ledctl; 498 499 DEBUGFUNC("e1000_phy_hw_reset_82541"); 500 501 ret_val = e1000_phy_hw_reset_generic(hw); 502 if (ret_val) 503 goto out; 504 505 e1000_phy_init_script_82541(hw); 506 507 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 508 /* Configure activity LED after PHY reset */ 509 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 510 ledctl &= IGP_ACTIVITY_LED_MASK; 511 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 512 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 513 } 514 515 out: 516 return ret_val; 517 } 518 519 /** 520 * e1000_setup_copper_link_82541 - Configure copper link settings 521 * @hw: pointer to the HW structure 522 * 523 * Calls the appropriate function to configure the link for auto-neg or forced 524 * speed and duplex. Then we check for link, once link is established calls 525 * to configure collision distance and flow control are called. If link is 526 * not established, we return -E1000_ERR_PHY (-2). 527 **/ 528 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) 529 { 530 struct e1000_phy_info *phy = &hw->phy; 531 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 532 s32 ret_val; 533 u32 ctrl, ledctl; 534 535 DEBUGFUNC("e1000_setup_copper_link_82541"); 536 537 ctrl = E1000_READ_REG(hw, E1000_CTRL); 538 ctrl |= E1000_CTRL_SLU; 539 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 540 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 541 542 hw->phy.reset_disable = FALSE; 543 544 /* Earlier revs of the IGP phy require us to force MDI. */ 545 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 546 dev_spec->dsp_config = e1000_dsp_config_disabled; 547 phy->mdix = 1; 548 } else { 549 dev_spec->dsp_config = e1000_dsp_config_enabled; 550 } 551 552 ret_val = e1000_copper_link_setup_igp(hw); 553 if (ret_val) 554 goto out; 555 556 if (hw->mac.autoneg) { 557 if (dev_spec->ffe_config == e1000_ffe_config_active) 558 dev_spec->ffe_config = e1000_ffe_config_enabled; 559 } 560 561 /* Configure activity LED after Phy reset */ 562 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 563 ledctl &= IGP_ACTIVITY_LED_MASK; 564 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 565 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 566 567 ret_val = e1000_setup_copper_link_generic(hw); 568 569 out: 570 return ret_val; 571 } 572 573 /** 574 * e1000_check_for_link_82541 - Check/Store link connection 575 * @hw: pointer to the HW structure 576 * 577 * This checks the link condition of the adapter and stores the 578 * results in the hw->mac structure. 579 **/ 580 static s32 e1000_check_for_link_82541(struct e1000_hw *hw) 581 { 582 struct e1000_mac_info *mac = &hw->mac; 583 s32 ret_val; 584 bool link; 585 586 DEBUGFUNC("e1000_check_for_link_82541"); 587 588 /* 589 * We only want to go out to the PHY registers to see if Auto-Neg 590 * has completed and/or if our link status has changed. The 591 * get_link_status flag is set upon receiving a Link Status 592 * Change or Rx Sequence Error interrupt. 593 */ 594 if (!mac->get_link_status) { 595 ret_val = E1000_SUCCESS; 596 goto out; 597 } 598 599 /* 600 * First we want to see if the MII Status Register reports 601 * link. If so, then we want to get the current speed/duplex 602 * of the PHY. 603 */ 604 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 605 if (ret_val) 606 goto out; 607 608 if (!link) { 609 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); 610 goto out; /* No link detected */ 611 } 612 613 mac->get_link_status = FALSE; 614 615 /* 616 * Check if there was DownShift, must be checked 617 * immediately after link-up 618 */ 619 e1000_check_downshift_generic(hw); 620 621 /* 622 * If we are forcing speed/duplex, then we simply return since 623 * we have already determined whether we have link or not. 624 */ 625 if (!mac->autoneg) { 626 ret_val = -E1000_ERR_CONFIG; 627 goto out; 628 } 629 630 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); 631 632 /* 633 * Auto-Neg is enabled. Auto Speed Detection takes care 634 * of MAC speed/duplex configuration. So we only need to 635 * configure Collision Distance in the MAC. 636 */ 637 e1000_config_collision_dist_generic(hw); 638 639 /* 640 * Configure Flow Control now that Auto-Neg has completed. 641 * First, we need to restore the desired flow control 642 * settings because we may have had to re-autoneg with a 643 * different link partner. 644 */ 645 ret_val = e1000_config_fc_after_link_up_generic(hw); 646 if (ret_val) { 647 DEBUGOUT("Error configuring flow control\n"); 648 } 649 650 out: 651 return ret_val; 652 } 653 654 /** 655 * e1000_config_dsp_after_link_change_82541 - Config DSP after link 656 * @hw: pointer to the HW structure 657 * @link_up: boolean flag for link up status 658 * 659 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 660 * at any other case. 661 * 662 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 663 * gigabit link is achieved to improve link quality. 664 **/ 665 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 666 bool link_up) 667 { 668 struct e1000_phy_info *phy = &hw->phy; 669 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 670 s32 ret_val; 671 u32 idle_errs = 0; 672 u16 phy_data, phy_saved_data, speed, duplex, i; 673 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 674 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 675 {IGP01E1000_PHY_AGC_PARAM_A, 676 IGP01E1000_PHY_AGC_PARAM_B, 677 IGP01E1000_PHY_AGC_PARAM_C, 678 IGP01E1000_PHY_AGC_PARAM_D}; 679 680 DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 681 682 if (link_up) { 683 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 684 if (ret_val) { 685 DEBUGOUT("Error getting link speed and duplex\n"); 686 goto out; 687 } 688 689 if (speed != SPEED_1000) { 690 ret_val = E1000_SUCCESS; 691 goto out; 692 } 693 694 ret_val = phy->ops.get_cable_length(hw); 695 if (ret_val) 696 goto out; 697 698 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 699 phy->min_cable_length >= 50) { 700 701 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 702 ret_val = phy->ops.read_reg(hw, 703 dsp_reg_array[i], 704 &phy_data); 705 if (ret_val) 706 goto out; 707 708 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 709 710 ret_val = phy->ops.write_reg(hw, 711 dsp_reg_array[i], 712 phy_data); 713 if (ret_val) 714 goto out; 715 } 716 dev_spec->dsp_config = e1000_dsp_config_activated; 717 } 718 719 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 720 (phy->min_cable_length >= 50)) { 721 ret_val = E1000_SUCCESS; 722 goto out; 723 } 724 725 /* clear previous idle error counts */ 726 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 727 if (ret_val) 728 goto out; 729 730 for (i = 0; i < ffe_idle_err_timeout; i++) { 731 usec_delay(1000); 732 ret_val = phy->ops.read_reg(hw, 733 PHY_1000T_STATUS, 734 &phy_data); 735 if (ret_val) 736 goto out; 737 738 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 739 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 740 dev_spec->ffe_config = e1000_ffe_config_active; 741 742 ret_val = phy->ops.write_reg(hw, 743 IGP01E1000_PHY_DSP_FFE, 744 IGP01E1000_PHY_DSP_FFE_CM_CP); 745 if (ret_val) 746 goto out; 747 break; 748 } 749 750 if (idle_errs) 751 ffe_idle_err_timeout = 752 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 753 } 754 } else { 755 if (dev_spec->dsp_config == e1000_dsp_config_activated) { 756 /* 757 * Save off the current value of register 0x2F5B 758 * to be restored at the end of the routines. 759 */ 760 ret_val = phy->ops.read_reg(hw, 761 0x2F5B, 762 &phy_saved_data); 763 if (ret_val) 764 goto out; 765 766 /* Disable the PHY transmitter */ 767 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 768 if (ret_val) 769 goto out; 770 771 msec_delay_irq(20); 772 773 ret_val = phy->ops.write_reg(hw, 774 0x0000, 775 IGP01E1000_IEEE_FORCE_GIG); 776 if (ret_val) 777 goto out; 778 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 779 ret_val = phy->ops.read_reg(hw, 780 dsp_reg_array[i], 781 &phy_data); 782 if (ret_val) 783 goto out; 784 785 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 786 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 787 788 ret_val = phy->ops.write_reg(hw, 789 dsp_reg_array[i], 790 phy_data); 791 if (ret_val) 792 goto out; 793 } 794 795 ret_val = phy->ops.write_reg(hw, 796 0x0000, 797 IGP01E1000_IEEE_RESTART_AUTONEG); 798 if (ret_val) 799 goto out; 800 801 msec_delay_irq(20); 802 803 /* Now enable the transmitter */ 804 ret_val = phy->ops.write_reg(hw, 805 0x2F5B, 806 phy_saved_data); 807 if (ret_val) 808 goto out; 809 810 dev_spec->dsp_config = e1000_dsp_config_enabled; 811 } 812 813 if (dev_spec->ffe_config != e1000_ffe_config_active) { 814 ret_val = E1000_SUCCESS; 815 goto out; 816 } 817 818 /* 819 * Save off the current value of register 0x2F5B 820 * to be restored at the end of the routines. 821 */ 822 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data); 823 if (ret_val) 824 goto out; 825 826 /* Disable the PHY transmitter */ 827 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 828 if (ret_val) 829 goto out; 830 831 msec_delay_irq(20); 832 833 ret_val = phy->ops.write_reg(hw, 834 0x0000, 835 IGP01E1000_IEEE_FORCE_GIG); 836 if (ret_val) 837 goto out; 838 839 ret_val = phy->ops.write_reg(hw, 840 IGP01E1000_PHY_DSP_FFE, 841 IGP01E1000_PHY_DSP_FFE_DEFAULT); 842 if (ret_val) 843 goto out; 844 845 ret_val = phy->ops.write_reg(hw, 846 0x0000, 847 IGP01E1000_IEEE_RESTART_AUTONEG); 848 if (ret_val) 849 goto out; 850 851 msec_delay_irq(20); 852 853 /* Now enable the transmitter */ 854 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data); 855 856 if (ret_val) 857 goto out; 858 859 dev_spec->ffe_config = e1000_ffe_config_enabled; 860 } 861 862 out: 863 return ret_val; 864 } 865 866 /** 867 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 868 * @hw: pointer to the HW structure 869 * 870 * The automatic gain control (agc) normalizes the amplitude of the 871 * received signal, adjusting for the attenuation produced by the 872 * cable. By reading the AGC registers, which represent the 873 * combination of coarse and fine gain value, the value can be put 874 * into a lookup table to obtain the approximate cable length 875 * for each channel. 876 **/ 877 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 878 { 879 struct e1000_phy_info *phy = &hw->phy; 880 s32 ret_val = E1000_SUCCESS; 881 u16 i, data; 882 u16 cur_agc_value, agc_value = 0; 883 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 884 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 885 {IGP01E1000_PHY_AGC_A, 886 IGP01E1000_PHY_AGC_B, 887 IGP01E1000_PHY_AGC_C, 888 IGP01E1000_PHY_AGC_D}; 889 890 DEBUGFUNC("e1000_get_cable_length_igp_82541"); 891 892 /* Read the AGC registers for all channels */ 893 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 894 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data); 895 if (ret_val) 896 goto out; 897 898 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 899 900 /* Bounds checking */ 901 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 902 (cur_agc_value == 0)) { 903 ret_val = -E1000_ERR_PHY; 904 goto out; 905 } 906 907 agc_value += cur_agc_value; 908 909 if (min_agc_value > cur_agc_value) 910 min_agc_value = cur_agc_value; 911 } 912 913 /* Remove the minimal AGC result for length < 50m */ 914 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 915 agc_value -= min_agc_value; 916 /* Average the three remaining channels for the length. */ 917 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 918 } else { 919 /* Average the channels for the length. */ 920 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 921 } 922 923 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 924 IGP01E1000_AGC_RANGE) 925 ? (e1000_igp_cable_length_table[agc_value] - 926 IGP01E1000_AGC_RANGE) 927 : 0; 928 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 929 IGP01E1000_AGC_RANGE; 930 931 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 932 933 out: 934 return ret_val; 935 } 936 937 /** 938 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 939 * @hw: pointer to the HW structure 940 * @active: boolean used to enable/disable lplu 941 * 942 * Success returns 0, Failure returns 1 943 * 944 * The low power link up (lplu) state is set to the power management level D3 945 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 946 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 947 * is used during Dx states where the power conservation is most important. 948 * During driver activity, SmartSpeed should be enabled so performance is 949 * maintained. 950 **/ 951 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 952 { 953 struct e1000_phy_info *phy = &hw->phy; 954 s32 ret_val; 955 u16 data; 956 957 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 958 959 switch (hw->mac.type) { 960 case e1000_82541_rev_2: 961 case e1000_82547_rev_2: 962 break; 963 default: 964 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 965 goto out; 966 break; 967 } 968 969 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); 970 if (ret_val) 971 goto out; 972 973 if (!active) { 974 data &= ~IGP01E1000_GMII_FLEX_SPD; 975 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 976 if (ret_val) 977 goto out; 978 979 /* 980 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 981 * during Dx states where the power conservation is most 982 * important. During driver activity we should enable 983 * SmartSpeed, so performance is maintained. 984 */ 985 if (phy->smart_speed == e1000_smart_speed_on) { 986 ret_val = phy->ops.read_reg(hw, 987 IGP01E1000_PHY_PORT_CONFIG, 988 &data); 989 if (ret_val) 990 goto out; 991 992 data |= IGP01E1000_PSCFR_SMART_SPEED; 993 ret_val = phy->ops.write_reg(hw, 994 IGP01E1000_PHY_PORT_CONFIG, 995 data); 996 if (ret_val) 997 goto out; 998 } else if (phy->smart_speed == e1000_smart_speed_off) { 999 ret_val = phy->ops.read_reg(hw, 1000 IGP01E1000_PHY_PORT_CONFIG, 1001 &data); 1002 if (ret_val) 1003 goto out; 1004 1005 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1006 ret_val = phy->ops.write_reg(hw, 1007 IGP01E1000_PHY_PORT_CONFIG, 1008 data); 1009 if (ret_val) 1010 goto out; 1011 } 1012 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1013 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1014 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1015 data |= IGP01E1000_GMII_FLEX_SPD; 1016 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 1017 if (ret_val) 1018 goto out; 1019 1020 /* When LPLU is enabled, we should disable SmartSpeed */ 1021 ret_val = phy->ops.read_reg(hw, 1022 IGP01E1000_PHY_PORT_CONFIG, 1023 &data); 1024 if (ret_val) 1025 goto out; 1026 1027 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1028 ret_val = phy->ops.write_reg(hw, 1029 IGP01E1000_PHY_PORT_CONFIG, 1030 data); 1031 } 1032 1033 out: 1034 return ret_val; 1035 } 1036 1037 /** 1038 * e1000_setup_led_82541 - Configures SW controllable LED 1039 * @hw: pointer to the HW structure 1040 * 1041 * This prepares the SW controllable LED for use and saves the current state 1042 * of the LED so it can be later restored. 1043 **/ 1044 static s32 e1000_setup_led_82541(struct e1000_hw *hw) 1045 { 1046 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1047 s32 ret_val; 1048 1049 DEBUGFUNC("e1000_setup_led_82541"); 1050 1051 ret_val = hw->phy.ops.read_reg(hw, 1052 IGP01E1000_GMII_FIFO, 1053 &dev_spec->spd_default); 1054 if (ret_val) 1055 goto out; 1056 1057 ret_val = hw->phy.ops.write_reg(hw, 1058 IGP01E1000_GMII_FIFO, 1059 (u16)(dev_spec->spd_default & 1060 ~IGP01E1000_GMII_SPD)); 1061 if (ret_val) 1062 goto out; 1063 1064 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1065 1066 out: 1067 return ret_val; 1068 } 1069 1070 /** 1071 * e1000_cleanup_led_82541 - Set LED config to default operation 1072 * @hw: pointer to the HW structure 1073 * 1074 * Remove the current LED configuration and set the LED configuration 1075 * to the default value, saved from the EEPROM. 1076 **/ 1077 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw) 1078 { 1079 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1080 s32 ret_val; 1081 1082 DEBUGFUNC("e1000_cleanup_led_82541"); 1083 1084 ret_val = hw->phy.ops.write_reg(hw, 1085 IGP01E1000_GMII_FIFO, 1086 dev_spec->spd_default); 1087 if (ret_val) 1088 goto out; 1089 1090 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1091 1092 out: 1093 return ret_val; 1094 } 1095 1096 /** 1097 * e1000_phy_init_script_82541 - Initialize GbE PHY 1098 * @hw: pointer to the HW structure 1099 * 1100 * Initializes the IGP PHY. 1101 **/ 1102 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw) 1103 { 1104 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1105 u32 ret_val; 1106 u16 phy_saved_data; 1107 1108 DEBUGFUNC("e1000_phy_init_script_82541"); 1109 1110 if (!dev_spec->phy_init_script) { 1111 ret_val = E1000_SUCCESS; 1112 goto out; 1113 } 1114 1115 /* Delay after phy reset to enable NVM configuration to load */ 1116 msec_delay(20); 1117 1118 /* 1119 * Save off the current value of register 0x2F5B to be restored at 1120 * the end of this routine. 1121 */ 1122 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); 1123 1124 /* Disabled the PHY transmitter */ 1125 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); 1126 1127 msec_delay(20); 1128 1129 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 1130 1131 msec_delay(5); 1132 1133 switch (hw->mac.type) { 1134 case e1000_82541: 1135 case e1000_82547: 1136 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); 1137 1138 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); 1139 1140 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); 1141 1142 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); 1143 1144 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); 1145 1146 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); 1147 1148 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); 1149 1150 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); 1151 1152 hw->phy.ops.write_reg(hw, 0x2010, 0x0008); 1153 break; 1154 case e1000_82541_rev_2: 1155 case e1000_82547_rev_2: 1156 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); 1157 break; 1158 default: 1159 break; 1160 } 1161 1162 hw->phy.ops.write_reg(hw, 0x0000, 0x3300); 1163 1164 msec_delay(20); 1165 1166 /* Now enable the transmitter */ 1167 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); 1168 1169 if (hw->mac.type == e1000_82547) { 1170 u16 fused, fine, coarse; 1171 1172 /* Move to analog registers page */ 1173 hw->phy.ops.read_reg(hw, 1174 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1175 &fused); 1176 1177 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1178 hw->phy.ops.read_reg(hw, 1179 IGP01E1000_ANALOG_FUSE_STATUS, 1180 &fused); 1181 1182 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1183 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1184 1185 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1186 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1187 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1188 } else if (coarse == 1189 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1190 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1191 1192 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1193 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1194 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1195 1196 hw->phy.ops.write_reg(hw, 1197 IGP01E1000_ANALOG_FUSE_CONTROL, 1198 fused); 1199 hw->phy.ops.write_reg(hw, 1200 IGP01E1000_ANALOG_FUSE_BYPASS, 1201 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1202 } 1203 } 1204 1205 out: 1206 return ret_val; 1207 } 1208 1209 /** 1210 * e1000_init_script_state_82541 - Enable/Disable PHY init script 1211 * @hw: pointer to the HW structure 1212 * @state: boolean value used to enable/disable PHY init script 1213 * 1214 * Allows the driver to enable/disable the PHY init script, if the PHY is an 1215 * IGP PHY. 1216 **/ 1217 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1218 { 1219 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1220 1221 DEBUGFUNC("e1000_init_script_state_82541"); 1222 1223 if (hw->phy.type != e1000_phy_igp) { 1224 DEBUGOUT("Initialization script not necessary.\n"); 1225 goto out; 1226 } 1227 1228 dev_spec->phy_init_script = state; 1229 1230 out: 1231 return; 1232 } 1233 1234 /** 1235 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1236 * @hw: pointer to the HW structure 1237 * 1238 * In the case of a PHY power down to save power, or to turn off link during a 1239 * driver unload, or wake on lan is not enabled, remove the link. 1240 **/ 1241 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1242 { 1243 /* If the management interface is not enabled, then power down */ 1244 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1245 e1000_power_down_phy_copper(hw); 1246 1247 return; 1248 } 1249 1250 /** 1251 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1252 * @hw: pointer to the HW structure 1253 * 1254 * Clears the hardware counters by reading the counter registers. 1255 **/ 1256 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1257 { 1258 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1259 1260 e1000_clear_hw_cntrs_base_generic(hw); 1261 1262 E1000_READ_REG(hw, E1000_PRC64); 1263 E1000_READ_REG(hw, E1000_PRC127); 1264 E1000_READ_REG(hw, E1000_PRC255); 1265 E1000_READ_REG(hw, E1000_PRC511); 1266 E1000_READ_REG(hw, E1000_PRC1023); 1267 E1000_READ_REG(hw, E1000_PRC1522); 1268 E1000_READ_REG(hw, E1000_PTC64); 1269 E1000_READ_REG(hw, E1000_PTC127); 1270 E1000_READ_REG(hw, E1000_PTC255); 1271 E1000_READ_REG(hw, E1000_PTC511); 1272 E1000_READ_REG(hw, E1000_PTC1023); 1273 E1000_READ_REG(hw, E1000_PTC1522); 1274 1275 E1000_READ_REG(hw, E1000_ALGNERRC); 1276 E1000_READ_REG(hw, E1000_RXERRC); 1277 E1000_READ_REG(hw, E1000_TNCRS); 1278 E1000_READ_REG(hw, E1000_CEXTERR); 1279 E1000_READ_REG(hw, E1000_TSCTC); 1280 E1000_READ_REG(hw, E1000_TSCTFC); 1281 1282 E1000_READ_REG(hw, E1000_MGTPRC); 1283 E1000_READ_REG(hw, E1000_MGTPDC); 1284 E1000_READ_REG(hw, E1000_MGTPTC); 1285 } 1286