1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82541EI Gigabit Ethernet Controller 37 * 82541ER Gigabit Ethernet Controller 38 * 82541GI Gigabit Ethernet Controller 39 * 82541PI Gigabit Ethernet Controller 40 * 82547EI Gigabit Ethernet Controller 41 * 82547GI Gigabit Ethernet Controller 42 */ 43 44 #include "e1000_api.h" 45 46 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 47 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 48 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 49 static s32 e1000_reset_hw_82541(struct e1000_hw *hw); 50 static s32 e1000_init_hw_82541(struct e1000_hw *hw); 51 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 52 u16 *duplex); 53 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 54 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 55 static s32 e1000_check_for_link_82541(struct e1000_hw *hw); 56 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 57 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 58 bool active); 59 static s32 e1000_setup_led_82541(struct e1000_hw *hw); 60 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 62 static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw); 63 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 64 bool link_up); 65 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 66 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 67 68 static const u16 e1000_igp_cable_length_table[] = { 69 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10, 70 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30, 71 40, 40, 40, 40, 40, 40, 40, 40, 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 72 60, 60, 60, 60, 60, 60, 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 73 80, 90, 90, 90, 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 74 100, 100, 100, 100, 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 75 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 120, 120, 76 120, 120, 120, 120, 120, 120, 120, 120}; 77 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 78 (sizeof(e1000_igp_cable_length_table) / \ 79 sizeof(e1000_igp_cable_length_table[0])) 80 81 /** 82 * e1000_init_phy_params_82541 - Init PHY func ptrs. 83 * @hw: pointer to the HW structure 84 **/ 85 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw) 86 { 87 struct e1000_phy_info *phy = &hw->phy; 88 s32 ret_val = E1000_SUCCESS; 89 90 DEBUGFUNC("e1000_init_phy_params_82541"); 91 92 phy->addr = 1; 93 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 94 phy->reset_delay_us = 10000; 95 phy->type = e1000_phy_igp; 96 97 /* Function Pointers */ 98 phy->ops.check_polarity = e1000_check_polarity_igp; 99 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 100 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; 101 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 102 phy->ops.get_info = e1000_get_phy_info_igp; 103 phy->ops.read_reg = e1000_read_phy_reg_igp; 104 phy->ops.reset = e1000_phy_hw_reset_82541; 105 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 106 phy->ops.write_reg = e1000_write_phy_reg_igp; 107 phy->ops.power_up = e1000_power_up_phy_copper; 108 phy->ops.power_down = e1000_power_down_phy_copper_82541; 109 110 ret_val = e1000_get_phy_id(hw); 111 if (ret_val) 112 goto out; 113 114 /* Verify phy id */ 115 if (phy->id != IGP01E1000_I_PHY_ID) { 116 ret_val = -E1000_ERR_PHY; 117 goto out; 118 } 119 120 out: 121 return ret_val; 122 } 123 124 /** 125 * e1000_init_nvm_params_82541 - Init NVM func ptrs. 126 * @hw: pointer to the HW structure 127 **/ 128 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) 129 { 130 struct e1000_nvm_info *nvm = &hw->nvm; 131 s32 ret_val = E1000_SUCCESS; 132 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 133 u16 size; 134 135 DEBUGFUNC("e1000_init_nvm_params_82541"); 136 137 switch (nvm->override) { 138 case e1000_nvm_override_spi_large: 139 nvm->type = e1000_nvm_eeprom_spi; 140 eecd |= E1000_EECD_ADDR_BITS; 141 break; 142 case e1000_nvm_override_spi_small: 143 nvm->type = e1000_nvm_eeprom_spi; 144 eecd &= ~E1000_EECD_ADDR_BITS; 145 break; 146 case e1000_nvm_override_microwire_large: 147 nvm->type = e1000_nvm_eeprom_microwire; 148 eecd |= E1000_EECD_SIZE; 149 break; 150 case e1000_nvm_override_microwire_small: 151 nvm->type = e1000_nvm_eeprom_microwire; 152 eecd &= ~E1000_EECD_SIZE; 153 break; 154 default: 155 nvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi 156 : e1000_nvm_eeprom_microwire; 157 break; 158 } 159 160 if (nvm->type == e1000_nvm_eeprom_spi) { 161 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8; 162 nvm->delay_usec = 1; 163 nvm->opcode_bits = 8; 164 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8; 165 166 /* Function Pointers */ 167 nvm->ops.acquire = e1000_acquire_nvm_generic; 168 nvm->ops.read = e1000_read_nvm_spi; 169 nvm->ops.release = e1000_release_nvm_generic; 170 nvm->ops.update = e1000_update_nvm_checksum_generic; 171 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 172 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 173 nvm->ops.write = e1000_write_nvm_spi; 174 175 /* 176 * nvm->word_size must be discovered after the pointers 177 * are set so we can verify the size from the nvm image 178 * itself. Temporarily set it to a dummy value so the 179 * read will work. 180 */ 181 nvm->word_size = 64; 182 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); 183 if (ret_val) 184 goto out; 185 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 186 /* 187 * if size != 0, it can be added to a constant and become 188 * the left-shift value to set the word_size. Otherwise, 189 * word_size stays at 64. 190 */ 191 if (size) { 192 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 193 nvm->word_size = 1 << size; 194 } 195 } else { 196 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 8 : 6; 197 nvm->delay_usec = 50; 198 nvm->opcode_bits = 3; 199 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ? 256 : 64; 200 201 /* Function Pointers */ 202 nvm->ops.acquire = e1000_acquire_nvm_generic; 203 nvm->ops.read = e1000_read_nvm_microwire; 204 nvm->ops.release = e1000_release_nvm_generic; 205 nvm->ops.update = e1000_update_nvm_checksum_generic; 206 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 207 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 208 nvm->ops.write = e1000_write_nvm_microwire; 209 } 210 211 out: 212 return ret_val; 213 } 214 215 /** 216 * e1000_init_mac_params_82541 - Init MAC func ptrs. 217 * @hw: pointer to the HW structure 218 **/ 219 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw) 220 { 221 struct e1000_mac_info *mac = &hw->mac; 222 223 DEBUGFUNC("e1000_init_mac_params_82541"); 224 225 /* Set media type */ 226 hw->phy.media_type = e1000_media_type_copper; 227 /* Set mta register count */ 228 mac->mta_reg_count = 128; 229 /* Set rar entry count */ 230 mac->rar_entry_count = E1000_RAR_ENTRIES; 231 /* Set if part includes ASF firmware */ 232 mac->asf_firmware_present = TRUE; 233 234 /* Function Pointers */ 235 236 /* bus type/speed/width */ 237 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 238 /* function id */ 239 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 240 /* reset */ 241 mac->ops.reset_hw = e1000_reset_hw_82541; 242 /* hw initialization */ 243 mac->ops.init_hw = e1000_init_hw_82541; 244 /* link setup */ 245 mac->ops.setup_link = e1000_setup_link_generic; 246 /* physical interface link setup */ 247 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; 248 /* check for link */ 249 mac->ops.check_for_link = e1000_check_for_link_82541; 250 /* link info */ 251 mac->ops.get_link_up_info = e1000_get_link_up_info_82541; 252 /* multicast address update */ 253 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 254 /* writing VFTA */ 255 mac->ops.write_vfta = e1000_write_vfta_generic; 256 /* clearing VFTA */ 257 mac->ops.clear_vfta = e1000_clear_vfta_generic; 258 /* read mac address */ 259 mac->ops.read_mac_addr = e1000_read_mac_addr_82541; 260 /* ID LED init */ 261 mac->ops.id_led_init = e1000_id_led_init_generic; 262 /* setup LED */ 263 mac->ops.setup_led = e1000_setup_led_82541; 264 /* cleanup LED */ 265 mac->ops.cleanup_led = e1000_cleanup_led_82541; 266 /* turn on/off LED */ 267 mac->ops.led_on = e1000_led_on_generic; 268 mac->ops.led_off = e1000_led_off_generic; 269 /* clear hardware counters */ 270 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 271 272 return E1000_SUCCESS; 273 } 274 275 /** 276 * e1000_init_function_pointers_82541 - Init func ptrs. 277 * @hw: pointer to the HW structure 278 * 279 * Called to initialize all function pointers and parameters. 280 **/ 281 void e1000_init_function_pointers_82541(struct e1000_hw *hw) 282 { 283 DEBUGFUNC("e1000_init_function_pointers_82541"); 284 285 hw->mac.ops.init_params = e1000_init_mac_params_82541; 286 hw->nvm.ops.init_params = e1000_init_nvm_params_82541; 287 hw->phy.ops.init_params = e1000_init_phy_params_82541; 288 } 289 290 /** 291 * e1000_reset_hw_82541 - Reset hardware 292 * @hw: pointer to the HW structure 293 * 294 * This resets the hardware into a known state. 295 **/ 296 static s32 e1000_reset_hw_82541(struct e1000_hw *hw) 297 { 298 u32 ledctl, ctrl, icr, manc; 299 300 DEBUGFUNC("e1000_reset_hw_82541"); 301 302 DEBUGOUT("Masking off all interrupts\n"); 303 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 304 305 E1000_WRITE_REG(hw, E1000_RCTL, 0); 306 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 307 E1000_WRITE_FLUSH(hw); 308 309 /* 310 * Delay to allow any outstanding PCI transactions to complete 311 * before resetting the device. 312 */ 313 msec_delay(10); 314 315 ctrl = E1000_READ_REG(hw, E1000_CTRL); 316 317 /* Must reset the Phy before resetting the MAC */ 318 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 319 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 320 msec_delay(5); 321 } 322 323 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 324 switch (hw->mac.type) { 325 case e1000_82541: 326 case e1000_82541_rev_2: 327 /* 328 * These controllers can't ack the 64-bit write when 329 * issuing the reset, so we use IO-mapping as a 330 * workaround to issue the reset. 331 */ 332 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 333 break; 334 default: 335 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 336 break; 337 } 338 339 /* Wait for NVM reload */ 340 msec_delay(20); 341 342 /* Disable HW ARPs on ASF enabled adapters */ 343 manc = E1000_READ_REG(hw, E1000_MANC); 344 manc &= ~E1000_MANC_ARP_EN; 345 E1000_WRITE_REG(hw, E1000_MANC, manc); 346 347 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 348 e1000_phy_init_script_82541(hw); 349 350 /* Configure activity LED after Phy reset */ 351 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 352 ledctl &= IGP_ACTIVITY_LED_MASK; 353 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 354 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 355 } 356 357 /* Once again, mask the interrupts */ 358 DEBUGOUT("Masking off all interrupts\n"); 359 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 360 361 /* Clear any pending interrupt events. */ 362 icr = E1000_READ_REG(hw, E1000_ICR); 363 364 return E1000_SUCCESS; 365 } 366 367 /** 368 * e1000_init_hw_82541 - Initialize hardware 369 * @hw: pointer to the HW structure 370 * 371 * This inits the hardware readying it for operation. 372 **/ 373 static s32 e1000_init_hw_82541(struct e1000_hw *hw) 374 { 375 struct e1000_mac_info *mac = &hw->mac; 376 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 377 u32 i, txdctl; 378 s32 ret_val; 379 380 DEBUGFUNC("e1000_init_hw_82541"); 381 382 /* Initialize identification LED */ 383 ret_val = mac->ops.id_led_init(hw); 384 if (ret_val) { 385 DEBUGOUT("Error initializing identification LED\n"); 386 /* This is not fatal and we should not stop init due to this */ 387 } 388 389 /* Storing the Speed Power Down value for later use */ 390 ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO, 391 &dev_spec->spd_default); 392 if (ret_val) 393 goto out; 394 395 /* Disabling VLAN filtering */ 396 DEBUGOUT("Initializing the IEEE VLAN\n"); 397 mac->ops.clear_vfta(hw); 398 399 /* Setup the receive address. */ 400 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 401 402 /* Zero out the Multicast HASH table */ 403 DEBUGOUT("Zeroing the MTA\n"); 404 for (i = 0; i < mac->mta_reg_count; i++) { 405 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 406 /* 407 * Avoid back to back register writes by adding the register 408 * read (flush). This is to protect against some strange 409 * bridge configurations that may issue Memory Write Block 410 * (MWB) to our register space. 411 */ 412 E1000_WRITE_FLUSH(hw); 413 } 414 415 /* Setup link and flow control */ 416 ret_val = mac->ops.setup_link(hw); 417 418 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 419 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 420 E1000_TXDCTL_FULL_TX_DESC_WB; 421 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 422 423 /* 424 * Clear all of the statistics registers (clear on read). It is 425 * important that we do this after we have tried to establish link 426 * because the symbol error count will increment wildly if there 427 * is no link. 428 */ 429 e1000_clear_hw_cntrs_82541(hw); 430 431 out: 432 return ret_val; 433 } 434 435 /** 436 * e1000_get_link_up_info_82541 - Report speed and duplex 437 * @hw: pointer to the HW structure 438 * @speed: pointer to speed buffer 439 * @duplex: pointer to duplex buffer 440 * 441 * Retrieve the current speed and duplex configuration. 442 **/ 443 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 444 u16 *duplex) 445 { 446 struct e1000_phy_info *phy = &hw->phy; 447 s32 ret_val; 448 u16 data; 449 450 DEBUGFUNC("e1000_get_link_up_info_82541"); 451 452 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 453 if (ret_val) 454 goto out; 455 456 if (!phy->speed_downgraded) 457 goto out; 458 459 /* 460 * IGP01 PHY may advertise full duplex operation after speed 461 * downgrade even if it is operating at half duplex. 462 * Here we set the duplex settings to match the duplex in the 463 * link partner's capabilities. 464 */ 465 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); 466 if (ret_val) 467 goto out; 468 469 if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 470 *duplex = HALF_DUPLEX; 471 } else { 472 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); 473 if (ret_val) 474 goto out; 475 476 if (*speed == SPEED_100) { 477 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 478 *duplex = HALF_DUPLEX; 479 } else if (*speed == SPEED_10) { 480 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 481 *duplex = HALF_DUPLEX; 482 } 483 } 484 485 out: 486 return ret_val; 487 } 488 489 /** 490 * e1000_phy_hw_reset_82541 - PHY hardware reset 491 * @hw: pointer to the HW structure 492 * 493 * Verify the reset block is not blocking us from resetting. Acquire 494 * semaphore (if necessary) and read/set/write the device control reset 495 * bit in the PHY. Wait the appropriate delay time for the device to 496 * reset and release the semaphore (if necessary). 497 **/ 498 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 499 { 500 s32 ret_val; 501 u32 ledctl; 502 503 DEBUGFUNC("e1000_phy_hw_reset_82541"); 504 505 ret_val = e1000_phy_hw_reset_generic(hw); 506 if (ret_val) 507 goto out; 508 509 e1000_phy_init_script_82541(hw); 510 511 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 512 /* Configure activity LED after PHY reset */ 513 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 514 ledctl &= IGP_ACTIVITY_LED_MASK; 515 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 516 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 517 } 518 519 out: 520 return ret_val; 521 } 522 523 /** 524 * e1000_setup_copper_link_82541 - Configure copper link settings 525 * @hw: pointer to the HW structure 526 * 527 * Calls the appropriate function to configure the link for auto-neg or forced 528 * speed and duplex. Then we check for link, once link is established calls 529 * to configure collision distance and flow control are called. If link is 530 * not established, we return -E1000_ERR_PHY (-2). 531 **/ 532 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) 533 { 534 struct e1000_phy_info *phy = &hw->phy; 535 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 536 s32 ret_val; 537 u32 ctrl, ledctl; 538 539 DEBUGFUNC("e1000_setup_copper_link_82541"); 540 541 ctrl = E1000_READ_REG(hw, E1000_CTRL); 542 ctrl |= E1000_CTRL_SLU; 543 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 544 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 545 546 547 /* Earlier revs of the IGP phy require us to force MDI. */ 548 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 549 dev_spec->dsp_config = e1000_dsp_config_disabled; 550 phy->mdix = 1; 551 } else { 552 dev_spec->dsp_config = e1000_dsp_config_enabled; 553 } 554 555 ret_val = e1000_copper_link_setup_igp(hw); 556 if (ret_val) 557 goto out; 558 559 if (hw->mac.autoneg) { 560 if (dev_spec->ffe_config == e1000_ffe_config_active) 561 dev_spec->ffe_config = e1000_ffe_config_enabled; 562 } 563 564 /* Configure activity LED after Phy reset */ 565 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 566 ledctl &= IGP_ACTIVITY_LED_MASK; 567 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 568 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 569 570 ret_val = e1000_setup_copper_link_generic(hw); 571 572 out: 573 return ret_val; 574 } 575 576 /** 577 * e1000_check_for_link_82541 - Check/Store link connection 578 * @hw: pointer to the HW structure 579 * 580 * This checks the link condition of the adapter and stores the 581 * results in the hw->mac structure. 582 **/ 583 static s32 e1000_check_for_link_82541(struct e1000_hw *hw) 584 { 585 struct e1000_mac_info *mac = &hw->mac; 586 s32 ret_val; 587 bool link; 588 589 DEBUGFUNC("e1000_check_for_link_82541"); 590 591 /* 592 * We only want to go out to the PHY registers to see if Auto-Neg 593 * has completed and/or if our link status has changed. The 594 * get_link_status flag is set upon receiving a Link Status 595 * Change or Rx Sequence Error interrupt. 596 */ 597 if (!mac->get_link_status) { 598 ret_val = E1000_SUCCESS; 599 goto out; 600 } 601 602 /* 603 * First we want to see if the MII Status Register reports 604 * link. If so, then we want to get the current speed/duplex 605 * of the PHY. 606 */ 607 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 608 if (ret_val) 609 goto out; 610 611 if (!link) { 612 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); 613 goto out; /* No link detected */ 614 } 615 616 mac->get_link_status = FALSE; 617 618 /* 619 * Check if there was DownShift, must be checked 620 * immediately after link-up 621 */ 622 e1000_check_downshift_generic(hw); 623 624 /* 625 * If we are forcing speed/duplex, then we simply return since 626 * we have already determined whether we have link or not. 627 */ 628 if (!mac->autoneg) { 629 ret_val = -E1000_ERR_CONFIG; 630 goto out; 631 } 632 633 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); 634 635 /* 636 * Auto-Neg is enabled. Auto Speed Detection takes care 637 * of MAC speed/duplex configuration. So we only need to 638 * configure Collision Distance in the MAC. 639 */ 640 mac->ops.config_collision_dist(hw); 641 642 /* 643 * Configure Flow Control now that Auto-Neg has completed. 644 * First, we need to restore the desired flow control 645 * settings because we may have had to re-autoneg with a 646 * different link partner. 647 */ 648 ret_val = e1000_config_fc_after_link_up_generic(hw); 649 if (ret_val) 650 DEBUGOUT("Error configuring flow control\n"); 651 652 out: 653 return ret_val; 654 } 655 656 /** 657 * e1000_config_dsp_after_link_change_82541 - Config DSP after link 658 * @hw: pointer to the HW structure 659 * @link_up: boolean flag for link up status 660 * 661 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 662 * at any other case. 663 * 664 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 665 * gigabit link is achieved to improve link quality. 666 **/ 667 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 668 bool link_up) 669 { 670 struct e1000_phy_info *phy = &hw->phy; 671 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 672 s32 ret_val; 673 u32 idle_errs = 0; 674 u16 phy_data, phy_saved_data, speed, duplex, i; 675 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 676 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { 677 IGP01E1000_PHY_AGC_PARAM_A, 678 IGP01E1000_PHY_AGC_PARAM_B, 679 IGP01E1000_PHY_AGC_PARAM_C, 680 IGP01E1000_PHY_AGC_PARAM_D}; 681 682 DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 683 684 if (link_up) { 685 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 686 if (ret_val) { 687 DEBUGOUT("Error getting link speed and duplex\n"); 688 goto out; 689 } 690 691 if (speed != SPEED_1000) { 692 ret_val = E1000_SUCCESS; 693 goto out; 694 } 695 696 ret_val = phy->ops.get_cable_length(hw); 697 if (ret_val) 698 goto out; 699 700 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 701 phy->min_cable_length >= 50) { 702 703 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 704 ret_val = phy->ops.read_reg(hw, 705 dsp_reg_array[i], 706 &phy_data); 707 if (ret_val) 708 goto out; 709 710 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 711 712 ret_val = phy->ops.write_reg(hw, 713 dsp_reg_array[i], 714 phy_data); 715 if (ret_val) 716 goto out; 717 } 718 dev_spec->dsp_config = e1000_dsp_config_activated; 719 } 720 721 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 722 (phy->min_cable_length >= 50)) { 723 ret_val = E1000_SUCCESS; 724 goto out; 725 } 726 727 /* clear previous idle error counts */ 728 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 729 if (ret_val) 730 goto out; 731 732 for (i = 0; i < ffe_idle_err_timeout; i++) { 733 usec_delay(1000); 734 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, 735 &phy_data); 736 if (ret_val) 737 goto out; 738 739 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 740 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 741 dev_spec->ffe_config = e1000_ffe_config_active; 742 743 ret_val = phy->ops.write_reg(hw, 744 IGP01E1000_PHY_DSP_FFE, 745 IGP01E1000_PHY_DSP_FFE_CM_CP); 746 if (ret_val) 747 goto out; 748 break; 749 } 750 751 if (idle_errs) 752 ffe_idle_err_timeout = 753 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 754 } 755 } else { 756 if (dev_spec->dsp_config == e1000_dsp_config_activated) { 757 /* 758 * Save off the current value of register 0x2F5B 759 * to be restored at the end of the routines. 760 */ 761 ret_val = phy->ops.read_reg(hw, 0x2F5B, 762 &phy_saved_data); 763 if (ret_val) 764 goto out; 765 766 /* Disable the PHY transmitter */ 767 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 768 if (ret_val) 769 goto out; 770 771 msec_delay_irq(20); 772 773 ret_val = phy->ops.write_reg(hw, 0x0000, 774 IGP01E1000_IEEE_FORCE_GIG); 775 if (ret_val) 776 goto out; 777 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 778 ret_val = phy->ops.read_reg(hw, 779 dsp_reg_array[i], 780 &phy_data); 781 if (ret_val) 782 goto out; 783 784 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 785 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 786 787 ret_val = phy->ops.write_reg(hw, 788 dsp_reg_array[i], 789 phy_data); 790 if (ret_val) 791 goto out; 792 } 793 794 ret_val = phy->ops.write_reg(hw, 0x0000, 795 IGP01E1000_IEEE_RESTART_AUTONEG); 796 if (ret_val) 797 goto out; 798 799 msec_delay_irq(20); 800 801 /* Now enable the transmitter */ 802 ret_val = phy->ops.write_reg(hw, 0x2F5B, 803 phy_saved_data); 804 if (ret_val) 805 goto out; 806 807 dev_spec->dsp_config = e1000_dsp_config_enabled; 808 } 809 810 if (dev_spec->ffe_config != e1000_ffe_config_active) { 811 ret_val = E1000_SUCCESS; 812 goto out; 813 } 814 815 /* 816 * Save off the current value of register 0x2F5B 817 * to be restored at the end of the routines. 818 */ 819 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data); 820 if (ret_val) 821 goto out; 822 823 /* Disable the PHY transmitter */ 824 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 825 if (ret_val) 826 goto out; 827 828 msec_delay_irq(20); 829 830 ret_val = phy->ops.write_reg(hw, 0x0000, 831 IGP01E1000_IEEE_FORCE_GIG); 832 if (ret_val) 833 goto out; 834 835 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE, 836 IGP01E1000_PHY_DSP_FFE_DEFAULT); 837 if (ret_val) 838 goto out; 839 840 ret_val = phy->ops.write_reg(hw, 0x0000, 841 IGP01E1000_IEEE_RESTART_AUTONEG); 842 if (ret_val) 843 goto out; 844 845 msec_delay_irq(20); 846 847 /* Now enable the transmitter */ 848 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data); 849 850 if (ret_val) 851 goto out; 852 853 dev_spec->ffe_config = e1000_ffe_config_enabled; 854 } 855 856 out: 857 return ret_val; 858 } 859 860 /** 861 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 862 * @hw: pointer to the HW structure 863 * 864 * The automatic gain control (agc) normalizes the amplitude of the 865 * received signal, adjusting for the attenuation produced by the 866 * cable. By reading the AGC registers, which represent the 867 * combination of coarse and fine gain value, the value can be put 868 * into a lookup table to obtain the approximate cable length 869 * for each channel. 870 **/ 871 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 872 { 873 struct e1000_phy_info *phy = &hw->phy; 874 s32 ret_val = E1000_SUCCESS; 875 u16 i, data; 876 u16 cur_agc_value, agc_value = 0; 877 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 878 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A, 879 IGP01E1000_PHY_AGC_B, 880 IGP01E1000_PHY_AGC_C, 881 IGP01E1000_PHY_AGC_D}; 882 883 DEBUGFUNC("e1000_get_cable_length_igp_82541"); 884 885 /* Read the AGC registers for all channels */ 886 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 887 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data); 888 if (ret_val) 889 goto out; 890 891 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 892 893 /* Bounds checking */ 894 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 895 (cur_agc_value == 0)) { 896 ret_val = -E1000_ERR_PHY; 897 goto out; 898 } 899 900 agc_value += cur_agc_value; 901 902 if (min_agc_value > cur_agc_value) 903 min_agc_value = cur_agc_value; 904 } 905 906 /* Remove the minimal AGC result for length < 50m */ 907 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 908 agc_value -= min_agc_value; 909 /* Average the three remaining channels for the length. */ 910 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 911 } else { 912 /* Average the channels for the length. */ 913 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 914 } 915 916 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 917 IGP01E1000_AGC_RANGE) 918 ? (e1000_igp_cable_length_table[agc_value] - 919 IGP01E1000_AGC_RANGE) 920 : 0; 921 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 922 IGP01E1000_AGC_RANGE; 923 924 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 925 926 out: 927 return ret_val; 928 } 929 930 /** 931 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 932 * @hw: pointer to the HW structure 933 * @active: boolean used to enable/disable lplu 934 * 935 * Success returns 0, Failure returns 1 936 * 937 * The low power link up (lplu) state is set to the power management level D3 938 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 939 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 940 * is used during Dx states where the power conservation is most important. 941 * During driver activity, SmartSpeed should be enabled so performance is 942 * maintained. 943 **/ 944 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 945 { 946 struct e1000_phy_info *phy = &hw->phy; 947 s32 ret_val; 948 u16 data; 949 950 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 951 952 switch (hw->mac.type) { 953 case e1000_82541_rev_2: 954 case e1000_82547_rev_2: 955 break; 956 default: 957 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 958 goto out; 959 break; 960 } 961 962 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); 963 if (ret_val) 964 goto out; 965 966 if (!active) { 967 data &= ~IGP01E1000_GMII_FLEX_SPD; 968 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 969 if (ret_val) 970 goto out; 971 972 /* 973 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 974 * during Dx states where the power conservation is most 975 * important. During driver activity we should enable 976 * SmartSpeed, so performance is maintained. 977 */ 978 if (phy->smart_speed == e1000_smart_speed_on) { 979 ret_val = phy->ops.read_reg(hw, 980 IGP01E1000_PHY_PORT_CONFIG, 981 &data); 982 if (ret_val) 983 goto out; 984 985 data |= IGP01E1000_PSCFR_SMART_SPEED; 986 ret_val = phy->ops.write_reg(hw, 987 IGP01E1000_PHY_PORT_CONFIG, 988 data); 989 if (ret_val) 990 goto out; 991 } else if (phy->smart_speed == e1000_smart_speed_off) { 992 ret_val = phy->ops.read_reg(hw, 993 IGP01E1000_PHY_PORT_CONFIG, 994 &data); 995 if (ret_val) 996 goto out; 997 998 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 999 ret_val = phy->ops.write_reg(hw, 1000 IGP01E1000_PHY_PORT_CONFIG, 1001 data); 1002 if (ret_val) 1003 goto out; 1004 } 1005 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1006 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1007 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1008 data |= IGP01E1000_GMII_FLEX_SPD; 1009 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 1010 if (ret_val) 1011 goto out; 1012 1013 /* When LPLU is enabled, we should disable SmartSpeed */ 1014 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1015 &data); 1016 if (ret_val) 1017 goto out; 1018 1019 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1020 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1021 data); 1022 } 1023 1024 out: 1025 return ret_val; 1026 } 1027 1028 /** 1029 * e1000_setup_led_82541 - Configures SW controllable LED 1030 * @hw: pointer to the HW structure 1031 * 1032 * This prepares the SW controllable LED for use and saves the current state 1033 * of the LED so it can be later restored. 1034 **/ 1035 static s32 e1000_setup_led_82541(struct e1000_hw *hw) 1036 { 1037 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1038 s32 ret_val; 1039 1040 DEBUGFUNC("e1000_setup_led_82541"); 1041 1042 ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO, 1043 &dev_spec->spd_default); 1044 if (ret_val) 1045 goto out; 1046 1047 ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO, 1048 (u16)(dev_spec->spd_default & 1049 ~IGP01E1000_GMII_SPD)); 1050 if (ret_val) 1051 goto out; 1052 1053 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1054 1055 out: 1056 return ret_val; 1057 } 1058 1059 /** 1060 * e1000_cleanup_led_82541 - Set LED config to default operation 1061 * @hw: pointer to the HW structure 1062 * 1063 * Remove the current LED configuration and set the LED configuration 1064 * to the default value, saved from the EEPROM. 1065 **/ 1066 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw) 1067 { 1068 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1069 s32 ret_val; 1070 1071 DEBUGFUNC("e1000_cleanup_led_82541"); 1072 1073 ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO, 1074 dev_spec->spd_default); 1075 if (ret_val) 1076 goto out; 1077 1078 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1079 1080 out: 1081 return ret_val; 1082 } 1083 1084 /** 1085 * e1000_phy_init_script_82541 - Initialize GbE PHY 1086 * @hw: pointer to the HW structure 1087 * 1088 * Initializes the IGP PHY. 1089 **/ 1090 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw) 1091 { 1092 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1093 u32 ret_val; 1094 u16 phy_saved_data; 1095 1096 DEBUGFUNC("e1000_phy_init_script_82541"); 1097 1098 if (!dev_spec->phy_init_script) { 1099 ret_val = E1000_SUCCESS; 1100 goto out; 1101 } 1102 1103 /* Delay after phy reset to enable NVM configuration to load */ 1104 msec_delay(20); 1105 1106 /* 1107 * Save off the current value of register 0x2F5B to be restored at 1108 * the end of this routine. 1109 */ 1110 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); 1111 1112 /* Disabled the PHY transmitter */ 1113 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); 1114 1115 msec_delay(20); 1116 1117 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 1118 1119 msec_delay(5); 1120 1121 switch (hw->mac.type) { 1122 case e1000_82541: 1123 case e1000_82547: 1124 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); 1125 1126 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); 1127 1128 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); 1129 1130 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); 1131 1132 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); 1133 1134 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); 1135 1136 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); 1137 1138 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); 1139 1140 hw->phy.ops.write_reg(hw, 0x2010, 0x0008); 1141 break; 1142 case e1000_82541_rev_2: 1143 case e1000_82547_rev_2: 1144 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); 1145 break; 1146 default: 1147 break; 1148 } 1149 1150 hw->phy.ops.write_reg(hw, 0x0000, 0x3300); 1151 1152 msec_delay(20); 1153 1154 /* Now enable the transmitter */ 1155 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); 1156 1157 if (hw->mac.type == e1000_82547) { 1158 u16 fused, fine, coarse; 1159 1160 /* Move to analog registers page */ 1161 hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1162 &fused); 1163 1164 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1165 hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, 1166 &fused); 1167 1168 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1169 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1170 1171 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1172 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1173 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1174 } else if (coarse == 1175 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1176 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1177 1178 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1179 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1180 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1181 1182 hw->phy.ops.write_reg(hw, 1183 IGP01E1000_ANALOG_FUSE_CONTROL, 1184 fused); 1185 hw->phy.ops.write_reg(hw, 1186 IGP01E1000_ANALOG_FUSE_BYPASS, 1187 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1188 } 1189 } 1190 1191 out: 1192 return ret_val; 1193 } 1194 1195 /** 1196 * e1000_init_script_state_82541 - Enable/Disable PHY init script 1197 * @hw: pointer to the HW structure 1198 * @state: boolean value used to enable/disable PHY init script 1199 * 1200 * Allows the driver to enable/disable the PHY init script, if the PHY is an 1201 * IGP PHY. 1202 **/ 1203 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1204 { 1205 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1206 1207 DEBUGFUNC("e1000_init_script_state_82541"); 1208 1209 if (hw->phy.type != e1000_phy_igp) { 1210 DEBUGOUT("Initialization script not necessary.\n"); 1211 goto out; 1212 } 1213 1214 dev_spec->phy_init_script = state; 1215 1216 out: 1217 return; 1218 } 1219 1220 /** 1221 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1222 * @hw: pointer to the HW structure 1223 * 1224 * In the case of a PHY power down to save power, or to turn off link during a 1225 * driver unload, or wake on lan is not enabled, remove the link. 1226 **/ 1227 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1228 { 1229 /* If the management interface is not enabled, then power down */ 1230 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1231 e1000_power_down_phy_copper(hw); 1232 1233 return; 1234 } 1235 1236 /** 1237 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1238 * @hw: pointer to the HW structure 1239 * 1240 * Clears the hardware counters by reading the counter registers. 1241 **/ 1242 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1243 { 1244 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1245 1246 e1000_clear_hw_cntrs_base_generic(hw); 1247 1248 E1000_READ_REG(hw, E1000_PRC64); 1249 E1000_READ_REG(hw, E1000_PRC127); 1250 E1000_READ_REG(hw, E1000_PRC255); 1251 E1000_READ_REG(hw, E1000_PRC511); 1252 E1000_READ_REG(hw, E1000_PRC1023); 1253 E1000_READ_REG(hw, E1000_PRC1522); 1254 E1000_READ_REG(hw, E1000_PTC64); 1255 E1000_READ_REG(hw, E1000_PTC127); 1256 E1000_READ_REG(hw, E1000_PTC255); 1257 E1000_READ_REG(hw, E1000_PTC511); 1258 E1000_READ_REG(hw, E1000_PTC1023); 1259 E1000_READ_REG(hw, E1000_PTC1522); 1260 1261 E1000_READ_REG(hw, E1000_ALGNERRC); 1262 E1000_READ_REG(hw, E1000_RXERRC); 1263 E1000_READ_REG(hw, E1000_TNCRS); 1264 E1000_READ_REG(hw, E1000_CEXTERR); 1265 E1000_READ_REG(hw, E1000_TSCTC); 1266 E1000_READ_REG(hw, E1000_TSCTFC); 1267 1268 E1000_READ_REG(hw, E1000_MGTPRC); 1269 E1000_READ_REG(hw, E1000_MGTPDC); 1270 E1000_READ_REG(hw, E1000_MGTPTC); 1271 } 1272 1273 /** 1274 * e1000_read_mac_addr_82541 - Read device MAC address 1275 * @hw: pointer to the HW structure 1276 * 1277 * Reads the device MAC address from the EEPROM and stores the value. 1278 **/ 1279 static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw) 1280 { 1281 s32 ret_val = E1000_SUCCESS; 1282 u16 offset, nvm_data, i; 1283 1284 DEBUGFUNC("e1000_read_mac_addr"); 1285 1286 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 1287 offset = i >> 1; 1288 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 1289 if (ret_val) { 1290 DEBUGOUT("NVM Read Error\n"); 1291 goto out; 1292 } 1293 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 1294 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 1295 } 1296 1297 for (i = 0; i < ETH_ADDR_LEN; i++) 1298 hw->mac.addr[i] = hw->mac.perm_addr[i]; 1299 1300 out: 1301 return ret_val; 1302 } 1303 1304