1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 /* 37 * 82540EM Gigabit Ethernet Controller 38 * 82540EP Gigabit Ethernet Controller 39 * 82545EM Gigabit Ethernet Controller (Copper) 40 * 82545EM Gigabit Ethernet Controller (Fiber) 41 * 82545GM Gigabit Ethernet Controller 42 * 82546EB Gigabit Ethernet Controller (Copper) 43 * 82546EB Gigabit Ethernet Controller (Fiber) 44 * 82546GB Gigabit Ethernet Controller 45 */ 46 47 #include "e1000_api.h" 48 49 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw); 50 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw); 51 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw); 52 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw); 53 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw); 54 static s32 e1000_init_hw_82540(struct e1000_hw *hw); 55 static s32 e1000_reset_hw_82540(struct e1000_hw *hw); 56 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw); 57 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw); 58 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw); 59 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw); 60 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw); 61 static s32 e1000_read_mac_addr_82540(struct e1000_hw *hw); 62 63 /** 64 * e1000_init_phy_params_82540 - Init PHY func ptrs. 65 * @hw: pointer to the HW structure 66 **/ 67 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw) 68 { 69 struct e1000_phy_info *phy = &hw->phy; 70 s32 ret_val; 71 72 phy->addr = 1; 73 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 74 phy->reset_delay_us = 10000; 75 phy->type = e1000_phy_m88; 76 77 /* Function Pointers */ 78 phy->ops.check_polarity = e1000_check_polarity_m88; 79 phy->ops.commit = e1000_phy_sw_reset_generic; 80 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 81 phy->ops.get_cable_length = e1000_get_cable_length_m88; 82 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 83 phy->ops.read_reg = e1000_read_phy_reg_m88; 84 phy->ops.reset = e1000_phy_hw_reset_generic; 85 phy->ops.write_reg = e1000_write_phy_reg_m88; 86 phy->ops.get_info = e1000_get_phy_info_m88; 87 phy->ops.power_up = e1000_power_up_phy_copper; 88 phy->ops.power_down = e1000_power_down_phy_copper_82540; 89 90 ret_val = e1000_get_phy_id(hw); 91 if (ret_val) 92 goto out; 93 94 /* Verify phy id */ 95 switch (hw->mac.type) { 96 case e1000_82540: 97 case e1000_82545: 98 case e1000_82545_rev_3: 99 case e1000_82546: 100 case e1000_82546_rev_3: 101 if (phy->id == M88E1011_I_PHY_ID) 102 break; 103 /* FALLTHROUGH */ 104 default: 105 ret_val = -E1000_ERR_PHY; 106 goto out; 107 break; 108 } 109 110 out: 111 return ret_val; 112 } 113 114 /** 115 * e1000_init_nvm_params_82540 - Init NVM func ptrs. 116 * @hw: pointer to the HW structure 117 **/ 118 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw) 119 { 120 struct e1000_nvm_info *nvm = &hw->nvm; 121 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 122 123 DEBUGFUNC("e1000_init_nvm_params_82540"); 124 125 nvm->type = e1000_nvm_eeprom_microwire; 126 nvm->delay_usec = 50; 127 nvm->opcode_bits = 3; 128 switch (nvm->override) { 129 case e1000_nvm_override_microwire_large: 130 nvm->address_bits = 8; 131 nvm->word_size = 256; 132 break; 133 case e1000_nvm_override_microwire_small: 134 nvm->address_bits = 6; 135 nvm->word_size = 64; 136 break; 137 default: 138 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6; 139 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64; 140 break; 141 } 142 143 /* Function Pointers */ 144 nvm->ops.acquire = e1000_acquire_nvm_generic; 145 nvm->ops.read = e1000_read_nvm_microwire; 146 nvm->ops.release = e1000_release_nvm_generic; 147 nvm->ops.update = e1000_update_nvm_checksum_generic; 148 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 149 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 150 nvm->ops.write = e1000_write_nvm_microwire; 151 152 return E1000_SUCCESS; 153 } 154 155 /** 156 * e1000_init_mac_params_82540 - Init MAC func ptrs. 157 * @hw: pointer to the HW structure 158 **/ 159 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw) 160 { 161 struct e1000_mac_info *mac = &hw->mac; 162 s32 ret_val = E1000_SUCCESS; 163 164 DEBUGFUNC("e1000_init_mac_params_82540"); 165 166 /* Set media type */ 167 switch (hw->device_id) { 168 case E1000_DEV_ID_82545EM_FIBER: 169 case E1000_DEV_ID_82545GM_FIBER: 170 case E1000_DEV_ID_82546EB_FIBER: 171 case E1000_DEV_ID_82546GB_FIBER: 172 hw->phy.media_type = e1000_media_type_fiber; 173 break; 174 case E1000_DEV_ID_82545GM_SERDES: 175 case E1000_DEV_ID_82546GB_SERDES: 176 hw->phy.media_type = e1000_media_type_internal_serdes; 177 break; 178 default: 179 hw->phy.media_type = e1000_media_type_copper; 180 break; 181 } 182 183 /* Set mta register count */ 184 mac->mta_reg_count = 128; 185 /* Set rar entry count */ 186 mac->rar_entry_count = E1000_RAR_ENTRIES; 187 188 /* Function pointers */ 189 190 /* bus type/speed/width */ 191 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 192 /* function id */ 193 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 194 /* reset */ 195 mac->ops.reset_hw = e1000_reset_hw_82540; 196 /* hw initialization */ 197 mac->ops.init_hw = e1000_init_hw_82540; 198 /* link setup */ 199 mac->ops.setup_link = e1000_setup_link_generic; 200 /* physical interface setup */ 201 mac->ops.setup_physical_interface = 202 (hw->phy.media_type == e1000_media_type_copper) 203 ? e1000_setup_copper_link_82540 204 : e1000_setup_fiber_serdes_link_82540; 205 /* check for link */ 206 switch (hw->phy.media_type) { 207 case e1000_media_type_copper: 208 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 209 break; 210 case e1000_media_type_fiber: 211 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 212 break; 213 case e1000_media_type_internal_serdes: 214 mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 215 break; 216 default: 217 ret_val = -E1000_ERR_CONFIG; 218 goto out; 219 break; 220 } 221 /* link info */ 222 mac->ops.get_link_up_info = 223 (hw->phy.media_type == e1000_media_type_copper) 224 ? e1000_get_speed_and_duplex_copper_generic 225 : e1000_get_speed_and_duplex_fiber_serdes_generic; 226 /* multicast address update */ 227 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 228 /* writing VFTA */ 229 mac->ops.write_vfta = e1000_write_vfta_generic; 230 /* clearing VFTA */ 231 mac->ops.clear_vfta = e1000_clear_vfta_generic; 232 /* read mac address */ 233 mac->ops.read_mac_addr = e1000_read_mac_addr_82540; 234 /* ID LED init */ 235 mac->ops.id_led_init = e1000_id_led_init_generic; 236 /* setup LED */ 237 mac->ops.setup_led = e1000_setup_led_generic; 238 /* cleanup LED */ 239 mac->ops.cleanup_led = e1000_cleanup_led_generic; 240 /* turn on/off LED */ 241 mac->ops.led_on = e1000_led_on_generic; 242 mac->ops.led_off = e1000_led_off_generic; 243 /* clear hardware counters */ 244 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540; 245 246 out: 247 return ret_val; 248 } 249 250 /** 251 * e1000_init_function_pointers_82540 - Init func ptrs. 252 * @hw: pointer to the HW structure 253 * 254 * Called to initialize all function pointers and parameters. 255 **/ 256 void e1000_init_function_pointers_82540(struct e1000_hw *hw) 257 { 258 DEBUGFUNC("e1000_init_function_pointers_82540"); 259 260 hw->mac.ops.init_params = e1000_init_mac_params_82540; 261 hw->nvm.ops.init_params = e1000_init_nvm_params_82540; 262 hw->phy.ops.init_params = e1000_init_phy_params_82540; 263 } 264 265 /** 266 * e1000_reset_hw_82540 - Reset hardware 267 * @hw: pointer to the HW structure 268 * 269 * This resets the hardware into a known state. 270 **/ 271 static s32 e1000_reset_hw_82540(struct e1000_hw *hw) 272 { 273 u32 ctrl, manc; 274 s32 ret_val = E1000_SUCCESS; 275 276 DEBUGFUNC("e1000_reset_hw_82540"); 277 278 DEBUGOUT("Masking off all interrupts\n"); 279 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 280 281 E1000_WRITE_REG(hw, E1000_RCTL, 0); 282 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 283 E1000_WRITE_FLUSH(hw); 284 285 /* 286 * Delay to allow any outstanding PCI transactions to complete 287 * before resetting the device. 288 */ 289 msec_delay(10); 290 291 ctrl = E1000_READ_REG(hw, E1000_CTRL); 292 293 DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n"); 294 switch (hw->mac.type) { 295 case e1000_82545_rev_3: 296 case e1000_82546_rev_3: 297 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST); 298 break; 299 default: 300 /* 301 * These controllers can't ack the 64-bit write when 302 * issuing the reset, so we use IO-mapping as a 303 * workaround to issue the reset. 304 */ 305 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 306 break; 307 } 308 309 /* Wait for EEPROM reload */ 310 msec_delay(5); 311 312 /* Disable HW ARPs on ASF enabled adapters */ 313 manc = E1000_READ_REG(hw, E1000_MANC); 314 manc &= ~E1000_MANC_ARP_EN; 315 E1000_WRITE_REG(hw, E1000_MANC, manc); 316 317 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 318 E1000_READ_REG(hw, E1000_ICR); 319 320 return ret_val; 321 } 322 323 /** 324 * e1000_init_hw_82540 - Initialize hardware 325 * @hw: pointer to the HW structure 326 * 327 * This inits the hardware readying it for operation. 328 **/ 329 static s32 e1000_init_hw_82540(struct e1000_hw *hw) 330 { 331 struct e1000_mac_info *mac = &hw->mac; 332 u32 txdctl, ctrl_ext; 333 s32 ret_val; 334 u16 i; 335 336 DEBUGFUNC("e1000_init_hw_82540"); 337 338 /* Initialize identification LED */ 339 ret_val = mac->ops.id_led_init(hw); 340 if (ret_val) { 341 DEBUGOUT("Error initializing identification LED\n"); 342 /* This is not fatal and we should not stop init due to this */ 343 } 344 345 /* Disabling VLAN filtering */ 346 DEBUGOUT("Initializing the IEEE VLAN\n"); 347 if (mac->type < e1000_82545_rev_3) 348 E1000_WRITE_REG(hw, E1000_VET, 0); 349 350 mac->ops.clear_vfta(hw); 351 352 /* Setup the receive address. */ 353 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 354 355 /* Zero out the Multicast HASH table */ 356 DEBUGOUT("Zeroing the MTA\n"); 357 for (i = 0; i < mac->mta_reg_count; i++) { 358 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 359 /* 360 * Avoid back to back register writes by adding the register 361 * read (flush). This is to protect against some strange 362 * bridge configurations that may issue Memory Write Block 363 * (MWB) to our register space. The *_rev_3 hardware at 364 * least doesn't respond correctly to every other dword in an 365 * MWB to our register space. 366 */ 367 E1000_WRITE_FLUSH(hw); 368 } 369 370 if (mac->type < e1000_82545_rev_3) 371 e1000_pcix_mmrbc_workaround_generic(hw); 372 373 /* Setup link and flow control */ 374 ret_val = mac->ops.setup_link(hw); 375 376 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 377 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 378 E1000_TXDCTL_FULL_TX_DESC_WB; 379 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 380 381 /* 382 * Clear all of the statistics registers (clear on read). It is 383 * important that we do this after we have tried to establish link 384 * because the symbol error count will increment wildly if there 385 * is no link. 386 */ 387 e1000_clear_hw_cntrs_82540(hw); 388 389 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) || 390 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) { 391 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 392 /* 393 * Relaxed ordering must be disabled to avoid a parity 394 * error crash in a PCI slot. 395 */ 396 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 397 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 398 } 399 400 return ret_val; 401 } 402 403 /** 404 * e1000_setup_copper_link_82540 - Configure copper link settings 405 * @hw: pointer to the HW structure 406 * 407 * Calls the appropriate function to configure the link for auto-neg or forced 408 * speed and duplex. Then we check for link, once link is established calls 409 * to configure collision distance and flow control are called. If link is 410 * not established, we return -E1000_ERR_PHY (-2). 411 **/ 412 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw) 413 { 414 u32 ctrl; 415 s32 ret_val; 416 u16 data; 417 418 DEBUGFUNC("e1000_setup_copper_link_82540"); 419 420 ctrl = E1000_READ_REG(hw, E1000_CTRL); 421 ctrl |= E1000_CTRL_SLU; 422 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 423 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 424 425 ret_val = e1000_set_phy_mode_82540(hw); 426 if (ret_val) 427 goto out; 428 429 if (hw->mac.type == e1000_82545_rev_3 || 430 hw->mac.type == e1000_82546_rev_3) { 431 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 432 &data); 433 if (ret_val) 434 goto out; 435 data |= 0x00000008; 436 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 437 data); 438 if (ret_val) 439 goto out; 440 } 441 442 ret_val = e1000_copper_link_setup_m88(hw); 443 if (ret_val) 444 goto out; 445 446 ret_val = e1000_setup_copper_link_generic(hw); 447 448 out: 449 return ret_val; 450 } 451 452 /** 453 * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes 454 * @hw: pointer to the HW structure 455 * 456 * Set the output amplitude to the value in the EEPROM and adjust the VCO 457 * speed to improve Bit Error Rate (BER) performance. Configures collision 458 * distance and flow control for fiber and serdes links. Upon successful 459 * setup, poll for link. 460 **/ 461 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw) 462 { 463 struct e1000_mac_info *mac = &hw->mac; 464 s32 ret_val = E1000_SUCCESS; 465 466 DEBUGFUNC("e1000_setup_fiber_serdes_link_82540"); 467 468 switch (mac->type) { 469 case e1000_82545_rev_3: 470 case e1000_82546_rev_3: 471 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 472 /* 473 * If we're on serdes media, adjust the output 474 * amplitude to value set in the EEPROM. 475 */ 476 ret_val = e1000_adjust_serdes_amplitude_82540(hw); 477 if (ret_val) 478 goto out; 479 } 480 /* Adjust VCO speed to improve BER performance */ 481 ret_val = e1000_set_vco_speed_82540(hw); 482 if (ret_val) 483 goto out; 484 default: 485 break; 486 } 487 488 ret_val = e1000_setup_fiber_serdes_link_generic(hw); 489 490 out: 491 return ret_val; 492 } 493 494 /** 495 * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM 496 * @hw: pointer to the HW structure 497 * 498 * Adjust the SERDES output amplitude based on the EEPROM settings. 499 **/ 500 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw) 501 { 502 s32 ret_val; 503 u16 nvm_data; 504 505 DEBUGFUNC("e1000_adjust_serdes_amplitude_82540"); 506 507 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data); 508 if (ret_val) 509 goto out; 510 511 if (nvm_data != NVM_RESERVED_WORD) { 512 /* Adjust serdes output amplitude only. */ 513 nvm_data &= NVM_SERDES_AMPLITUDE_MASK; 514 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL, 515 nvm_data); 516 if (ret_val) 517 goto out; 518 } 519 520 out: 521 return ret_val; 522 } 523 524 /** 525 * e1000_set_vco_speed_82540 - Set VCO speed for better performance 526 * @hw: pointer to the HW structure 527 * 528 * Set the VCO speed to improve Bit Error Rate (BER) performance. 529 **/ 530 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw) 531 { 532 s32 ret_val; 533 u16 default_page = 0; 534 u16 phy_data; 535 536 DEBUGFUNC("e1000_set_vco_speed_82540"); 537 538 /* Set PHY register 30, page 5, bit 8 to 0 */ 539 540 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT, 541 &default_page); 542 if (ret_val) 543 goto out; 544 545 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 546 if (ret_val) 547 goto out; 548 549 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 550 if (ret_val) 551 goto out; 552 553 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 554 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 555 if (ret_val) 556 goto out; 557 558 /* Set PHY register 30, page 4, bit 11 to 1 */ 559 560 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 561 if (ret_val) 562 goto out; 563 564 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 565 if (ret_val) 566 goto out; 567 568 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 569 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 570 if (ret_val) 571 goto out; 572 573 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 574 default_page); 575 576 out: 577 return ret_val; 578 } 579 580 /** 581 * e1000_set_phy_mode_82540 - Set PHY to class A mode 582 * @hw: pointer to the HW structure 583 * 584 * Sets the PHY to class A mode and assumes the following operations will 585 * follow to enable the new class mode: 586 * 1. Do a PHY soft reset. 587 * 2. Restart auto-negotiation or force link. 588 **/ 589 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw) 590 { 591 s32 ret_val = E1000_SUCCESS; 592 u16 nvm_data; 593 594 DEBUGFUNC("e1000_set_phy_mode_82540"); 595 596 if (hw->mac.type != e1000_82545_rev_3) 597 goto out; 598 599 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data); 600 if (ret_val) { 601 ret_val = -E1000_ERR_PHY; 602 goto out; 603 } 604 605 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) { 606 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 607 0x000B); 608 if (ret_val) { 609 ret_val = -E1000_ERR_PHY; 610 goto out; 611 } 612 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 613 0x8104); 614 if (ret_val) { 615 ret_val = -E1000_ERR_PHY; 616 goto out; 617 } 618 619 } 620 621 out: 622 return ret_val; 623 } 624 625 /** 626 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down 627 * @hw: pointer to the HW structure 628 * 629 * In the case of a PHY power down to save power, or to turn off link during a 630 * driver unload, or wake on lan is not enabled, remove the link. 631 **/ 632 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw) 633 { 634 /* If the management interface is not enabled, then power down */ 635 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 636 e1000_power_down_phy_copper(hw); 637 638 return; 639 } 640 641 /** 642 * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters 643 * @hw: pointer to the HW structure 644 * 645 * Clears the hardware counters by reading the counter registers. 646 **/ 647 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw) 648 { 649 DEBUGFUNC("e1000_clear_hw_cntrs_82540"); 650 651 e1000_clear_hw_cntrs_base_generic(hw); 652 653 E1000_READ_REG(hw, E1000_PRC64); 654 E1000_READ_REG(hw, E1000_PRC127); 655 E1000_READ_REG(hw, E1000_PRC255); 656 E1000_READ_REG(hw, E1000_PRC511); 657 E1000_READ_REG(hw, E1000_PRC1023); 658 E1000_READ_REG(hw, E1000_PRC1522); 659 E1000_READ_REG(hw, E1000_PTC64); 660 E1000_READ_REG(hw, E1000_PTC127); 661 E1000_READ_REG(hw, E1000_PTC255); 662 E1000_READ_REG(hw, E1000_PTC511); 663 E1000_READ_REG(hw, E1000_PTC1023); 664 E1000_READ_REG(hw, E1000_PTC1522); 665 666 E1000_READ_REG(hw, E1000_ALGNERRC); 667 E1000_READ_REG(hw, E1000_RXERRC); 668 E1000_READ_REG(hw, E1000_TNCRS); 669 E1000_READ_REG(hw, E1000_CEXTERR); 670 E1000_READ_REG(hw, E1000_TSCTC); 671 E1000_READ_REG(hw, E1000_TSCTFC); 672 673 E1000_READ_REG(hw, E1000_MGTPRC); 674 E1000_READ_REG(hw, E1000_MGTPDC); 675 E1000_READ_REG(hw, E1000_MGTPTC); 676 } 677 678 /** 679 * e1000_read_mac_addr_82540 - Read device MAC address 680 * @hw: pointer to the HW structure 681 * 682 * Reads the device MAC address from the EEPROM and stores the value. 683 * Since devices with two ports use the same EEPROM, we increment the 684 * last bit in the MAC address for the second port. 685 * 686 * This version is being used over generic because of customer issues 687 * with VmWare and Virtual Box when using generic. It seems in 688 * the emulated 82545, RAR[0] does NOT have a valid address after a 689 * reset, this older method works and using this breaks nothing for 690 * these legacy adapters. 691 **/ 692 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw) 693 { 694 s32 ret_val = E1000_SUCCESS; 695 u16 offset, nvm_data, i; 696 697 DEBUGFUNC("e1000_read_mac_addr"); 698 699 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 700 offset = i >> 1; 701 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 702 if (ret_val) { 703 DEBUGOUT("NVM Read Error\n"); 704 goto out; 705 } 706 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 707 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 708 } 709 710 /* Flip last bit of mac address if we're on second port */ 711 if (hw->bus.func == E1000_FUNC_1) 712 hw->mac.perm_addr[5] ^= 1; 713 714 for (i = 0; i < ETHER_ADDR_LEN; i++) 715 hw->mac.addr[i] = hw->mac.perm_addr[i]; 716 717 out: 718 return ret_val; 719 } 720