1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2015, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 /* 80003ES2LAN Gigabit Ethernet Controller (Copper) 37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 38 */ 39 40 #include "e1000_api.h" 41 42 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 43 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 44 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 45 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 46 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 47 u32 offset, 48 u16 *data); 49 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 50 u32 offset, 51 u16 data); 52 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 53 u16 words, u16 *data); 54 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 55 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 56 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 57 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 58 u16 *duplex); 59 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 60 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 61 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 62 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 63 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 64 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 65 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 66 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); 67 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 68 u16 *data); 69 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 70 u16 data); 71 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 72 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 73 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); 74 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 75 76 /* A table for the GG82563 cable length where the range is defined 77 * with a lower bound at "index" and the upper bound at 78 * "index + 5". 79 */ 80 static const u16 e1000_gg82563_cable_length_table[] = { 81 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 82 #define GG82563_CABLE_LENGTH_TABLE_SIZE \ 83 (sizeof(e1000_gg82563_cable_length_table) / \ 84 sizeof(e1000_gg82563_cable_length_table[0])) 85 86 /** 87 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 88 * @hw: pointer to the HW structure 89 **/ 90 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 91 { 92 struct e1000_phy_info *phy = &hw->phy; 93 s32 ret_val; 94 95 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 96 97 if (hw->phy.media_type != e1000_media_type_copper) { 98 phy->type = e1000_phy_none; 99 return E1000_SUCCESS; 100 } else { 101 phy->ops.power_up = e1000_power_up_phy_copper; 102 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 103 } 104 105 phy->addr = 1; 106 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 107 phy->reset_delay_us = 100; 108 phy->type = e1000_phy_gg82563; 109 110 phy->ops.acquire = e1000_acquire_phy_80003es2lan; 111 phy->ops.check_polarity = e1000_check_polarity_m88; 112 phy->ops.check_reset_block = e1000_check_reset_block_generic; 113 phy->ops.commit = e1000_phy_sw_reset_generic; 114 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; 115 phy->ops.get_info = e1000_get_phy_info_m88; 116 phy->ops.release = e1000_release_phy_80003es2lan; 117 phy->ops.reset = e1000_phy_hw_reset_generic; 118 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 119 120 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 121 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; 122 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; 123 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; 124 125 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; 126 127 /* This can only be done after all function pointers are setup. */ 128 ret_val = e1000_get_phy_id(hw); 129 130 /* Verify phy id */ 131 if (phy->id != GG82563_E_PHY_ID) 132 return -E1000_ERR_PHY; 133 134 return ret_val; 135 } 136 137 /** 138 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 139 * @hw: pointer to the HW structure 140 **/ 141 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 142 { 143 struct e1000_nvm_info *nvm = &hw->nvm; 144 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 145 u16 size; 146 147 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 148 149 nvm->opcode_bits = 8; 150 nvm->delay_usec = 1; 151 switch (nvm->override) { 152 case e1000_nvm_override_spi_large: 153 nvm->page_size = 32; 154 nvm->address_bits = 16; 155 break; 156 case e1000_nvm_override_spi_small: 157 nvm->page_size = 8; 158 nvm->address_bits = 8; 159 break; 160 default: 161 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 162 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 163 break; 164 } 165 166 nvm->type = e1000_nvm_eeprom_spi; 167 168 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 169 E1000_EECD_SIZE_EX_SHIFT); 170 171 /* Added to a constant, "size" becomes the left-shift value 172 * for setting word_size. 173 */ 174 size += NVM_WORD_SIZE_BASE_SHIFT; 175 176 /* EEPROM access above 16k is unsupported */ 177 if (size > 14) 178 size = 14; 179 nvm->word_size = 1 << size; 180 181 /* Function Pointers */ 182 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; 183 nvm->ops.read = e1000_read_nvm_eerd; 184 nvm->ops.release = e1000_release_nvm_80003es2lan; 185 nvm->ops.update = e1000_update_nvm_checksum_generic; 186 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 187 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 188 nvm->ops.write = e1000_write_nvm_80003es2lan; 189 190 return E1000_SUCCESS; 191 } 192 193 /** 194 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 195 * @hw: pointer to the HW structure 196 **/ 197 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 198 { 199 struct e1000_mac_info *mac = &hw->mac; 200 201 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 202 203 /* Set media type and media-dependent function pointers */ 204 switch (hw->device_id) { 205 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 206 hw->phy.media_type = e1000_media_type_internal_serdes; 207 mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 208 mac->ops.setup_physical_interface = 209 e1000_setup_fiber_serdes_link_generic; 210 break; 211 default: 212 hw->phy.media_type = e1000_media_type_copper; 213 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 214 mac->ops.setup_physical_interface = 215 e1000_setup_copper_link_80003es2lan; 216 break; 217 } 218 219 /* Set mta register count */ 220 mac->mta_reg_count = 128; 221 /* Set rar entry count */ 222 mac->rar_entry_count = E1000_RAR_ENTRIES; 223 /* Set if part includes ASF firmware */ 224 mac->asf_firmware_present = TRUE; 225 /* FWSM register */ 226 mac->has_fwsm = TRUE; 227 /* ARC supported; valid only if manageability features are enabled. */ 228 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & 229 E1000_FWSM_MODE_MASK); 230 /* Adaptive IFS not supported */ 231 mac->adaptive_ifs = FALSE; 232 233 /* Function pointers */ 234 235 /* bus type/speed/width */ 236 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 237 /* reset */ 238 mac->ops.reset_hw = e1000_reset_hw_80003es2lan; 239 /* hw initialization */ 240 mac->ops.init_hw = e1000_init_hw_80003es2lan; 241 /* link setup */ 242 mac->ops.setup_link = e1000_setup_link_generic; 243 /* check management mode */ 244 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 245 /* multicast address update */ 246 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 247 /* writing VFTA */ 248 mac->ops.write_vfta = e1000_write_vfta_generic; 249 /* clearing VFTA */ 250 mac->ops.clear_vfta = e1000_clear_vfta_generic; 251 /* read mac address */ 252 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; 253 /* ID LED init */ 254 mac->ops.id_led_init = e1000_id_led_init_generic; 255 /* blink LED */ 256 mac->ops.blink_led = e1000_blink_led_generic; 257 /* setup LED */ 258 mac->ops.setup_led = e1000_setup_led_generic; 259 /* cleanup LED */ 260 mac->ops.cleanup_led = e1000_cleanup_led_generic; 261 /* turn on/off LED */ 262 mac->ops.led_on = e1000_led_on_generic; 263 mac->ops.led_off = e1000_led_off_generic; 264 /* clear hardware counters */ 265 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 266 /* link info */ 267 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; 268 269 /* set lan id for port to determine which phy lock to use */ 270 hw->mac.ops.set_lan_id(hw); 271 272 return E1000_SUCCESS; 273 } 274 275 /** 276 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 277 * @hw: pointer to the HW structure 278 * 279 * Called to initialize all function pointers and parameters. 280 **/ 281 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 282 { 283 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 284 285 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; 286 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; 287 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; 288 } 289 290 /** 291 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 292 * @hw: pointer to the HW structure 293 * 294 * A wrapper to acquire access rights to the correct PHY. 295 **/ 296 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 297 { 298 u16 mask; 299 300 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 301 302 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 303 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 304 } 305 306 /** 307 * e1000_release_phy_80003es2lan - Release rights to access PHY 308 * @hw: pointer to the HW structure 309 * 310 * A wrapper to release access rights to the correct PHY. 311 **/ 312 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 313 { 314 u16 mask; 315 316 DEBUGFUNC("e1000_release_phy_80003es2lan"); 317 318 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 319 e1000_release_swfw_sync_80003es2lan(hw, mask); 320 } 321 322 /** 323 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register 324 * @hw: pointer to the HW structure 325 * 326 * Acquire the semaphore to access the Kumeran interface. 327 * 328 **/ 329 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) 330 { 331 u16 mask; 332 333 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan"); 334 335 mask = E1000_SWFW_CSR_SM; 336 337 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 338 } 339 340 /** 341 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register 342 * @hw: pointer to the HW structure 343 * 344 * Release the semaphore used to access the Kumeran interface 345 **/ 346 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) 347 { 348 u16 mask; 349 350 DEBUGFUNC("e1000_release_mac_csr_80003es2lan"); 351 352 mask = E1000_SWFW_CSR_SM; 353 354 e1000_release_swfw_sync_80003es2lan(hw, mask); 355 } 356 357 /** 358 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 359 * @hw: pointer to the HW structure 360 * 361 * Acquire the semaphore to access the EEPROM. 362 **/ 363 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 364 { 365 s32 ret_val; 366 367 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 368 369 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 370 if (ret_val) 371 return ret_val; 372 373 ret_val = e1000_acquire_nvm_generic(hw); 374 375 if (ret_val) 376 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 377 378 return ret_val; 379 } 380 381 /** 382 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 383 * @hw: pointer to the HW structure 384 * 385 * Release the semaphore used to access the EEPROM. 386 **/ 387 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 388 { 389 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 390 391 e1000_release_nvm_generic(hw); 392 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 393 } 394 395 /** 396 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 397 * @hw: pointer to the HW structure 398 * @mask: specifies which semaphore to acquire 399 * 400 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 401 * will also specify which port we're acquiring the lock for. 402 **/ 403 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 404 { 405 u32 swfw_sync; 406 u32 swmask = mask; 407 u32 fwmask = mask << 16; 408 s32 i = 0; 409 s32 timeout = 50; 410 411 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 412 413 while (i < timeout) { 414 if (e1000_get_hw_semaphore_generic(hw)) 415 return -E1000_ERR_SWFW_SYNC; 416 417 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 418 if (!(swfw_sync & (fwmask | swmask))) 419 break; 420 421 /* Firmware currently using resource (fwmask) 422 * or other software thread using resource (swmask) 423 */ 424 e1000_put_hw_semaphore_generic(hw); 425 msec_delay_irq(5); 426 i++; 427 } 428 429 if (i == timeout) { 430 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 431 return -E1000_ERR_SWFW_SYNC; 432 } 433 434 swfw_sync |= swmask; 435 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 436 437 e1000_put_hw_semaphore_generic(hw); 438 439 return E1000_SUCCESS; 440 } 441 442 /** 443 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 444 * @hw: pointer to the HW structure 445 * @mask: specifies which semaphore to acquire 446 * 447 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 448 * will also specify which port we're releasing the lock for. 449 **/ 450 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 451 { 452 u32 swfw_sync; 453 454 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 455 456 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 457 ; /* Empty */ 458 459 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 460 swfw_sync &= ~mask; 461 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 462 463 e1000_put_hw_semaphore_generic(hw); 464 } 465 466 /** 467 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 468 * @hw: pointer to the HW structure 469 * @offset: offset of the register to read 470 * @data: pointer to the data returned from the operation 471 * 472 * Read the GG82563 PHY register. 473 **/ 474 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 475 u32 offset, u16 *data) 476 { 477 s32 ret_val; 478 u32 page_select; 479 u16 temp; 480 481 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 482 483 ret_val = e1000_acquire_phy_80003es2lan(hw); 484 if (ret_val) 485 return ret_val; 486 487 /* Select Configuration Page */ 488 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 489 page_select = GG82563_PHY_PAGE_SELECT; 490 } else { 491 /* Use Alternative Page Select register to access 492 * registers 30 and 31 493 */ 494 page_select = GG82563_PHY_PAGE_SELECT_ALT; 495 } 496 497 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 498 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 499 if (ret_val) { 500 e1000_release_phy_80003es2lan(hw); 501 return ret_val; 502 } 503 504 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 505 /* The "ready" bit in the MDIC register may be incorrectly set 506 * before the device has completed the "Page Select" MDI 507 * transaction. So we wait 200us after each MDI command... 508 */ 509 usec_delay(200); 510 511 /* ...and verify the command was successful. */ 512 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 513 514 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 515 e1000_release_phy_80003es2lan(hw); 516 return -E1000_ERR_PHY; 517 } 518 519 usec_delay(200); 520 521 ret_val = e1000_read_phy_reg_mdic(hw, 522 MAX_PHY_REG_ADDRESS & offset, 523 data); 524 525 usec_delay(200); 526 } else { 527 ret_val = e1000_read_phy_reg_mdic(hw, 528 MAX_PHY_REG_ADDRESS & offset, 529 data); 530 } 531 532 e1000_release_phy_80003es2lan(hw); 533 534 return ret_val; 535 } 536 537 /** 538 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 539 * @hw: pointer to the HW structure 540 * @offset: offset of the register to read 541 * @data: value to write to the register 542 * 543 * Write to the GG82563 PHY register. 544 **/ 545 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 546 u32 offset, u16 data) 547 { 548 s32 ret_val; 549 u32 page_select; 550 u16 temp; 551 552 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 553 554 ret_val = e1000_acquire_phy_80003es2lan(hw); 555 if (ret_val) 556 return ret_val; 557 558 /* Select Configuration Page */ 559 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 560 page_select = GG82563_PHY_PAGE_SELECT; 561 } else { 562 /* Use Alternative Page Select register to access 563 * registers 30 and 31 564 */ 565 page_select = GG82563_PHY_PAGE_SELECT_ALT; 566 } 567 568 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 569 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 570 if (ret_val) { 571 e1000_release_phy_80003es2lan(hw); 572 return ret_val; 573 } 574 575 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 576 /* The "ready" bit in the MDIC register may be incorrectly set 577 * before the device has completed the "Page Select" MDI 578 * transaction. So we wait 200us after each MDI command... 579 */ 580 usec_delay(200); 581 582 /* ...and verify the command was successful. */ 583 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 584 585 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 586 e1000_release_phy_80003es2lan(hw); 587 return -E1000_ERR_PHY; 588 } 589 590 usec_delay(200); 591 592 ret_val = e1000_write_phy_reg_mdic(hw, 593 MAX_PHY_REG_ADDRESS & offset, 594 data); 595 596 usec_delay(200); 597 } else { 598 ret_val = e1000_write_phy_reg_mdic(hw, 599 MAX_PHY_REG_ADDRESS & offset, 600 data); 601 } 602 603 e1000_release_phy_80003es2lan(hw); 604 605 return ret_val; 606 } 607 608 /** 609 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 610 * @hw: pointer to the HW structure 611 * @offset: offset of the register to read 612 * @words: number of words to write 613 * @data: buffer of data to write to the NVM 614 * 615 * Write "words" of data to the ESB2 NVM. 616 **/ 617 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 618 u16 words, u16 *data) 619 { 620 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 621 622 return e1000_write_nvm_spi(hw, offset, words, data); 623 } 624 625 /** 626 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 627 * @hw: pointer to the HW structure 628 * 629 * Wait a specific amount of time for manageability processes to complete. 630 * This is a function pointer entry point called by the phy module. 631 **/ 632 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 633 { 634 s32 timeout = PHY_CFG_TIMEOUT; 635 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 636 637 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 638 639 if (hw->bus.func == 1) 640 mask = E1000_NVM_CFG_DONE_PORT_1; 641 642 while (timeout) { 643 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 644 break; 645 msec_delay(1); 646 timeout--; 647 } 648 if (!timeout) { 649 DEBUGOUT("MNG configuration cycle has not completed.\n"); 650 return -E1000_ERR_RESET; 651 } 652 653 return E1000_SUCCESS; 654 } 655 656 /** 657 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 658 * @hw: pointer to the HW structure 659 * 660 * Force the speed and duplex settings onto the PHY. This is a 661 * function pointer entry point called by the phy module. 662 **/ 663 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 664 { 665 s32 ret_val; 666 u16 phy_data; 667 bool link; 668 669 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 670 671 if (!(hw->phy.ops.read_reg)) 672 return E1000_SUCCESS; 673 674 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 675 * forced whenever speed and duplex are forced. 676 */ 677 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 678 if (ret_val) 679 return ret_val; 680 681 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 682 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 683 if (ret_val) 684 return ret_val; 685 686 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 687 688 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); 689 if (ret_val) 690 return ret_val; 691 692 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 693 694 /* Reset the phy to commit changes. */ 695 phy_data |= MII_CR_RESET; 696 697 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); 698 if (ret_val) 699 return ret_val; 700 701 usec_delay(1); 702 703 if (hw->phy.autoneg_wait_to_complete) { 704 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n"); 705 706 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 707 100000, &link); 708 if (ret_val) 709 return ret_val; 710 711 if (!link) { 712 /* We didn't get link. 713 * Reset the DSP and cross our fingers. 714 */ 715 ret_val = e1000_phy_reset_dsp_generic(hw); 716 if (ret_val) 717 return ret_val; 718 } 719 720 /* Try once more */ 721 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 722 100000, &link); 723 if (ret_val) 724 return ret_val; 725 } 726 727 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 728 &phy_data); 729 if (ret_val) 730 return ret_val; 731 732 /* Resetting the phy means we need to verify the TX_CLK corresponds 733 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 734 */ 735 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 736 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 737 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 738 else 739 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 740 741 /* In addition, we must re-enable CRS on Tx for both half and full 742 * duplex. 743 */ 744 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 745 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 746 phy_data); 747 748 return ret_val; 749 } 750 751 /** 752 * e1000_get_cable_length_80003es2lan - Set approximate cable length 753 * @hw: pointer to the HW structure 754 * 755 * Find the approximate cable length as measured by the GG82563 PHY. 756 * This is a function pointer entry point called by the phy module. 757 **/ 758 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 759 { 760 struct e1000_phy_info *phy = &hw->phy; 761 s32 ret_val; 762 u16 phy_data, index; 763 764 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 765 766 if (!(hw->phy.ops.read_reg)) 767 return E1000_SUCCESS; 768 769 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 770 if (ret_val) 771 return ret_val; 772 773 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 774 775 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) 776 return -E1000_ERR_PHY; 777 778 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 779 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; 780 781 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 782 783 return E1000_SUCCESS; 784 } 785 786 /** 787 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 788 * @hw: pointer to the HW structure 789 * @speed: pointer to speed buffer 790 * @duplex: pointer to duplex buffer 791 * 792 * Retrieve the current speed and duplex configuration. 793 **/ 794 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 795 u16 *duplex) 796 { 797 s32 ret_val; 798 799 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 800 801 if (hw->phy.media_type == e1000_media_type_copper) { 802 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 803 duplex); 804 hw->phy.ops.cfg_on_link_up(hw); 805 } else { 806 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 807 speed, 808 duplex); 809 } 810 811 return ret_val; 812 } 813 814 /** 815 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 816 * @hw: pointer to the HW structure 817 * 818 * Perform a global reset to the ESB2 controller. 819 **/ 820 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 821 { 822 u32 ctrl; 823 s32 ret_val; 824 u16 kum_reg_data; 825 826 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 827 828 /* Prevent the PCI-E bus from sticking if there is no TLP connection 829 * on the last TLP read/write transaction when MAC is reset. 830 */ 831 ret_val = e1000_disable_pcie_master_generic(hw); 832 if (ret_val) 833 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 834 835 DEBUGOUT("Masking off all interrupts\n"); 836 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 837 838 E1000_WRITE_REG(hw, E1000_RCTL, 0); 839 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 840 E1000_WRITE_FLUSH(hw); 841 842 msec_delay(10); 843 844 ctrl = E1000_READ_REG(hw, E1000_CTRL); 845 846 ret_val = e1000_acquire_phy_80003es2lan(hw); 847 if (ret_val) 848 return ret_val; 849 850 DEBUGOUT("Issuing a global reset to MAC\n"); 851 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 852 e1000_release_phy_80003es2lan(hw); 853 854 /* Disable IBIST slave mode (far-end loopback) */ 855 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 856 E1000_KMRNCTRLSTA_INBAND_PARAM, &kum_reg_data); 857 if (!ret_val) { 858 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 859 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 860 E1000_KMRNCTRLSTA_INBAND_PARAM, 861 kum_reg_data); 862 if (ret_val) 863 DEBUGOUT("Error disabling far-end loopback\n"); 864 } else 865 DEBUGOUT("Error disabling far-end loopback\n"); 866 867 ret_val = e1000_get_auto_rd_done_generic(hw); 868 if (ret_val) 869 /* We don't want to continue accessing MAC registers. */ 870 return ret_val; 871 872 /* Clear any pending interrupt events. */ 873 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 874 E1000_READ_REG(hw, E1000_ICR); 875 876 return e1000_check_alt_mac_addr_generic(hw); 877 } 878 879 /** 880 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 881 * @hw: pointer to the HW structure 882 * 883 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 884 **/ 885 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 886 { 887 struct e1000_mac_info *mac = &hw->mac; 888 u32 reg_data; 889 s32 ret_val; 890 u16 kum_reg_data; 891 u16 i; 892 893 DEBUGFUNC("e1000_init_hw_80003es2lan"); 894 895 e1000_initialize_hw_bits_80003es2lan(hw); 896 897 /* Initialize identification LED */ 898 ret_val = mac->ops.id_led_init(hw); 899 /* An error is not fatal and we should not stop init due to this */ 900 if (ret_val) 901 DEBUGOUT("Error initializing identification LED\n"); 902 903 /* Disabling VLAN filtering */ 904 DEBUGOUT("Initializing the IEEE VLAN\n"); 905 mac->ops.clear_vfta(hw); 906 907 /* Setup the receive address. */ 908 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 909 910 /* Zero out the Multicast HASH table */ 911 DEBUGOUT("Zeroing the MTA\n"); 912 for (i = 0; i < mac->mta_reg_count; i++) 913 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 914 915 /* Setup link and flow control */ 916 ret_val = mac->ops.setup_link(hw); 917 if (ret_val) 918 return ret_val; 919 920 /* Disable IBIST slave mode (far-end loopback) */ 921 ret_val = 922 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 923 &kum_reg_data); 924 if (!ret_val) { 925 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 926 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 927 E1000_KMRNCTRLSTA_INBAND_PARAM, 928 kum_reg_data); 929 if (ret_val) 930 DEBUGOUT("Error disabling far-end loopback\n"); 931 } else 932 DEBUGOUT("Error disabling far-end loopback\n"); 933 934 /* Set the transmit descriptor write-back policy */ 935 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 936 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 937 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 938 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 939 940 /* ...for both queues. */ 941 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 942 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 943 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 944 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 945 946 /* Enable retransmit on late collisions */ 947 reg_data = E1000_READ_REG(hw, E1000_TCTL); 948 reg_data |= E1000_TCTL_RTLC; 949 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 950 951 /* Configure Gigabit Carry Extend Padding */ 952 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 953 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 954 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 955 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 956 957 /* Configure Transmit Inter-Packet Gap */ 958 reg_data = E1000_READ_REG(hw, E1000_TIPG); 959 reg_data &= ~E1000_TIPG_IPGT_MASK; 960 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 961 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 962 963 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 964 reg_data &= ~0x00100000; 965 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 966 967 /* default to TRUE to enable the MDIC W/A */ 968 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE; 969 970 ret_val = 971 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >> 972 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i); 973 if (!ret_val) { 974 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == 975 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) 976 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE; 977 } 978 979 /* Clear all of the statistics registers (clear on read). It is 980 * important that we do this after we have tried to establish link 981 * because the symbol error count will increment wildly if there 982 * is no link. 983 */ 984 e1000_clear_hw_cntrs_80003es2lan(hw); 985 986 return ret_val; 987 } 988 989 /** 990 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 991 * @hw: pointer to the HW structure 992 * 993 * Initializes required hardware-dependent bits needed for normal operation. 994 **/ 995 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 996 { 997 u32 reg; 998 999 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 1000 1001 /* Transmit Descriptor Control 0 */ 1002 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1003 reg |= (1 << 22); 1004 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1005 1006 /* Transmit Descriptor Control 1 */ 1007 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1008 reg |= (1 << 22); 1009 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1010 1011 /* Transmit Arbitration Control 0 */ 1012 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1013 reg &= ~(0xF << 27); /* 30:27 */ 1014 if (hw->phy.media_type != e1000_media_type_copper) 1015 reg &= ~(1 << 20); 1016 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1017 1018 /* Transmit Arbitration Control 1 */ 1019 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1020 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1021 reg &= ~(1 << 28); 1022 else 1023 reg |= (1 << 28); 1024 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1025 1026 /* Disable IPv6 extension header parsing because some malformed 1027 * IPv6 headers can hang the Rx. 1028 */ 1029 reg = E1000_READ_REG(hw, E1000_RFCTL); 1030 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1031 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 1032 1033 return; 1034 } 1035 1036 /** 1037 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 1038 * @hw: pointer to the HW structure 1039 * 1040 * Setup some GG82563 PHY registers for obtaining link 1041 **/ 1042 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 1043 { 1044 struct e1000_phy_info *phy = &hw->phy; 1045 s32 ret_val; 1046 u32 reg; 1047 u16 data; 1048 1049 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 1050 1051 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); 1052 if (ret_val) 1053 return ret_val; 1054 1055 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1056 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1057 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1058 1059 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); 1060 if (ret_val) 1061 return ret_val; 1062 1063 /* Options: 1064 * MDI/MDI-X = 0 (default) 1065 * 0 - Auto for all speeds 1066 * 1 - MDI mode 1067 * 2 - MDI-X mode 1068 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1069 */ 1070 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1071 if (ret_val) 1072 return ret_val; 1073 1074 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1075 1076 switch (phy->mdix) { 1077 case 1: 1078 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1079 break; 1080 case 2: 1081 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1082 break; 1083 case 0: 1084 default: 1085 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1086 break; 1087 } 1088 1089 /* Options: 1090 * disable_polarity_correction = 0 (default) 1091 * Automatic Correction for Reversed Cable Polarity 1092 * 0 - Disabled 1093 * 1 - Enabled 1094 */ 1095 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1096 if (phy->disable_polarity_correction) 1097 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1098 1099 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1100 if (ret_val) 1101 return ret_val; 1102 1103 /* SW Reset the PHY so all changes take effect */ 1104 ret_val = hw->phy.ops.commit(hw); 1105 if (ret_val) { 1106 DEBUGOUT("Error Resetting the PHY\n"); 1107 return ret_val; 1108 } 1109 1110 /* Bypass Rx and Tx FIFO's */ 1111 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL; 1112 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1113 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1114 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 1115 if (ret_val) 1116 return ret_val; 1117 1118 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE; 1119 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data); 1120 if (ret_val) 1121 return ret_val; 1122 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1123 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 1124 if (ret_val) 1125 return ret_val; 1126 1127 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1128 if (ret_val) 1129 return ret_val; 1130 1131 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1132 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1133 if (ret_val) 1134 return ret_val; 1135 1136 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1137 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1138 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1139 1140 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1141 if (ret_val) 1142 return ret_val; 1143 1144 /* Do not init these registers when the HW is in IAMT mode, since the 1145 * firmware will have already initialized them. We only initialize 1146 * them if the HW is not in IAMT mode. 1147 */ 1148 if (!hw->mac.ops.check_mng_mode(hw)) { 1149 /* Enable Electrical Idle on the PHY */ 1150 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1151 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1152 data); 1153 if (ret_val) 1154 return ret_val; 1155 1156 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1157 &data); 1158 if (ret_val) 1159 return ret_val; 1160 1161 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1162 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1163 data); 1164 if (ret_val) 1165 return ret_val; 1166 } 1167 1168 /* Workaround: Disable padding in Kumeran interface in the MAC 1169 * and in the PHY to avoid CRC errors. 1170 */ 1171 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1172 if (ret_val) 1173 return ret_val; 1174 1175 data |= GG82563_ICR_DIS_PADDING; 1176 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1177 if (ret_val) 1178 return ret_val; 1179 1180 return E1000_SUCCESS; 1181 } 1182 1183 /** 1184 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1185 * @hw: pointer to the HW structure 1186 * 1187 * Essentially a wrapper for setting up all things "copper" related. 1188 * This is a function pointer entry point called by the mac module. 1189 **/ 1190 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1191 { 1192 u32 ctrl; 1193 s32 ret_val; 1194 u16 reg_data; 1195 1196 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1197 1198 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1199 ctrl |= E1000_CTRL_SLU; 1200 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1201 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1202 1203 /* Set the mac to wait the maximum time between each 1204 * iteration and increase the max iterations when 1205 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1206 */ 1207 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1208 0xFFFF); 1209 if (ret_val) 1210 return ret_val; 1211 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1212 ®_data); 1213 if (ret_val) 1214 return ret_val; 1215 reg_data |= 0x3F; 1216 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1217 reg_data); 1218 if (ret_val) 1219 return ret_val; 1220 ret_val = 1221 e1000_read_kmrn_reg_80003es2lan(hw, 1222 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1223 ®_data); 1224 if (ret_val) 1225 return ret_val; 1226 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1227 ret_val = 1228 e1000_write_kmrn_reg_80003es2lan(hw, 1229 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1230 reg_data); 1231 if (ret_val) 1232 return ret_val; 1233 1234 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1235 if (ret_val) 1236 return ret_val; 1237 1238 return e1000_setup_copper_link_generic(hw); 1239 } 1240 1241 /** 1242 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up 1243 * @hw: pointer to the HW structure 1244 * @duplex: current duplex setting 1245 * 1246 * Configure the KMRN interface by applying last minute quirks for 1247 * 10/100 operation. 1248 **/ 1249 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) 1250 { 1251 s32 ret_val = E1000_SUCCESS; 1252 u16 speed; 1253 u16 duplex; 1254 1255 DEBUGFUNC("e1000_configure_on_link_up"); 1256 1257 if (hw->phy.media_type == e1000_media_type_copper) { 1258 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed, 1259 &duplex); 1260 if (ret_val) 1261 return ret_val; 1262 1263 if (speed == SPEED_1000) 1264 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 1265 else 1266 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); 1267 } 1268 1269 return ret_val; 1270 } 1271 1272 /** 1273 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1274 * @hw: pointer to the HW structure 1275 * @duplex: current duplex setting 1276 * 1277 * Configure the KMRN interface by applying last minute quirks for 1278 * 10/100 operation. 1279 **/ 1280 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1281 { 1282 s32 ret_val; 1283 u32 tipg; 1284 u32 i = 0; 1285 u16 reg_data, reg_data2; 1286 1287 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1288 1289 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1290 ret_val = 1291 e1000_write_kmrn_reg_80003es2lan(hw, 1292 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1293 reg_data); 1294 if (ret_val) 1295 return ret_val; 1296 1297 /* Configure Transmit Inter-Packet Gap */ 1298 tipg = E1000_READ_REG(hw, E1000_TIPG); 1299 tipg &= ~E1000_TIPG_IPGT_MASK; 1300 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1301 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1302 1303 do { 1304 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1305 ®_data); 1306 if (ret_val) 1307 return ret_val; 1308 1309 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1310 ®_data2); 1311 if (ret_val) 1312 return ret_val; 1313 i++; 1314 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1315 1316 if (duplex == HALF_DUPLEX) 1317 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1318 else 1319 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1320 1321 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1322 } 1323 1324 /** 1325 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1326 * @hw: pointer to the HW structure 1327 * 1328 * Configure the KMRN interface by applying last minute quirks for 1329 * gigabit operation. 1330 **/ 1331 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1332 { 1333 s32 ret_val; 1334 u16 reg_data, reg_data2; 1335 u32 tipg; 1336 u32 i = 0; 1337 1338 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1339 1340 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1341 ret_val = 1342 e1000_write_kmrn_reg_80003es2lan(hw, 1343 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1344 reg_data); 1345 if (ret_val) 1346 return ret_val; 1347 1348 /* Configure Transmit Inter-Packet Gap */ 1349 tipg = E1000_READ_REG(hw, E1000_TIPG); 1350 tipg &= ~E1000_TIPG_IPGT_MASK; 1351 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1352 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1353 1354 do { 1355 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1356 ®_data); 1357 if (ret_val) 1358 return ret_val; 1359 1360 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1361 ®_data2); 1362 if (ret_val) 1363 return ret_val; 1364 i++; 1365 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1366 1367 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1368 1369 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1370 } 1371 1372 /** 1373 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register 1374 * @hw: pointer to the HW structure 1375 * @offset: register offset to be read 1376 * @data: pointer to the read data 1377 * 1378 * Acquire semaphore, then read the PHY register at offset 1379 * using the kumeran interface. The information retrieved is stored in data. 1380 * Release the semaphore before exiting. 1381 **/ 1382 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1383 u16 *data) 1384 { 1385 u32 kmrnctrlsta; 1386 s32 ret_val; 1387 1388 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan"); 1389 1390 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1391 if (ret_val) 1392 return ret_val; 1393 1394 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1395 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1396 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1397 E1000_WRITE_FLUSH(hw); 1398 1399 usec_delay(2); 1400 1401 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 1402 *data = (u16)kmrnctrlsta; 1403 1404 e1000_release_mac_csr_80003es2lan(hw); 1405 1406 return ret_val; 1407 } 1408 1409 /** 1410 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register 1411 * @hw: pointer to the HW structure 1412 * @offset: register offset to write to 1413 * @data: data to write at register offset 1414 * 1415 * Acquire semaphore, then write the data to PHY register 1416 * at the offset using the kumeran interface. Release semaphore 1417 * before exiting. 1418 **/ 1419 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1420 u16 data) 1421 { 1422 u32 kmrnctrlsta; 1423 s32 ret_val; 1424 1425 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan"); 1426 1427 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1428 if (ret_val) 1429 return ret_val; 1430 1431 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1432 E1000_KMRNCTRLSTA_OFFSET) | data; 1433 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1434 E1000_WRITE_FLUSH(hw); 1435 1436 usec_delay(2); 1437 1438 e1000_release_mac_csr_80003es2lan(hw); 1439 1440 return ret_val; 1441 } 1442 1443 /** 1444 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1445 * @hw: pointer to the HW structure 1446 **/ 1447 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1448 { 1449 s32 ret_val; 1450 1451 DEBUGFUNC("e1000_read_mac_addr_80003es2lan"); 1452 1453 /* If there's an alternate MAC address place it in RAR0 1454 * so that it will override the Si installed default perm 1455 * address. 1456 */ 1457 ret_val = e1000_check_alt_mac_addr_generic(hw); 1458 if (ret_val) 1459 return ret_val; 1460 1461 return e1000_read_mac_addr_generic(hw); 1462 } 1463 1464 /** 1465 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1466 * @hw: pointer to the HW structure 1467 * 1468 * In the case of a PHY power down to save power, or to turn off link during a 1469 * driver unload, or wake on lan is not enabled, remove the link. 1470 **/ 1471 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1472 { 1473 /* If the management interface is not enabled, then power down */ 1474 if (!(hw->mac.ops.check_mng_mode(hw) || 1475 hw->phy.ops.check_reset_block(hw))) 1476 e1000_power_down_phy_copper(hw); 1477 1478 return; 1479 } 1480 1481 /** 1482 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1483 * @hw: pointer to the HW structure 1484 * 1485 * Clears the hardware counters by reading the counter registers. 1486 **/ 1487 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1488 { 1489 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1490 1491 e1000_clear_hw_cntrs_base_generic(hw); 1492 1493 E1000_READ_REG(hw, E1000_PRC64); 1494 E1000_READ_REG(hw, E1000_PRC127); 1495 E1000_READ_REG(hw, E1000_PRC255); 1496 E1000_READ_REG(hw, E1000_PRC511); 1497 E1000_READ_REG(hw, E1000_PRC1023); 1498 E1000_READ_REG(hw, E1000_PRC1522); 1499 E1000_READ_REG(hw, E1000_PTC64); 1500 E1000_READ_REG(hw, E1000_PTC127); 1501 E1000_READ_REG(hw, E1000_PTC255); 1502 E1000_READ_REG(hw, E1000_PTC511); 1503 E1000_READ_REG(hw, E1000_PTC1023); 1504 E1000_READ_REG(hw, E1000_PTC1522); 1505 1506 E1000_READ_REG(hw, E1000_ALGNERRC); 1507 E1000_READ_REG(hw, E1000_RXERRC); 1508 E1000_READ_REG(hw, E1000_TNCRS); 1509 E1000_READ_REG(hw, E1000_CEXTERR); 1510 E1000_READ_REG(hw, E1000_TSCTC); 1511 E1000_READ_REG(hw, E1000_TSCTFC); 1512 1513 E1000_READ_REG(hw, E1000_MGTPRC); 1514 E1000_READ_REG(hw, E1000_MGTPDC); 1515 E1000_READ_REG(hw, E1000_MGTPTC); 1516 1517 E1000_READ_REG(hw, E1000_IAC); 1518 E1000_READ_REG(hw, E1000_ICRXOC); 1519 1520 E1000_READ_REG(hw, E1000_ICRXPTC); 1521 E1000_READ_REG(hw, E1000_ICRXATC); 1522 E1000_READ_REG(hw, E1000_ICTXPTC); 1523 E1000_READ_REG(hw, E1000_ICTXATC); 1524 E1000_READ_REG(hw, E1000_ICTXQEC); 1525 E1000_READ_REG(hw, E1000_ICTXQMTC); 1526 E1000_READ_REG(hw, E1000_ICRXDMTC); 1527 } 1528