1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2015, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 /* 80003ES2LAN Gigabit Ethernet Controller (Copper) 37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 38 */ 39 40 #include "e1000_api.h" 41 42 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 43 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 44 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 45 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 46 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 47 u32 offset, 48 u16 *data); 49 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 50 u32 offset, 51 u16 data); 52 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 53 u16 words, u16 *data); 54 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 55 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 56 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 57 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 58 u16 *duplex); 59 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 60 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 61 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 62 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 63 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 64 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 65 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); 66 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 67 u16 *data); 68 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 69 u16 data); 70 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 71 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); 72 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 73 74 /* A table for the GG82563 cable length where the range is defined 75 * with a lower bound at "index" and the upper bound at 76 * "index + 5". 77 */ 78 static const u16 e1000_gg82563_cable_length_table[] = { 79 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 80 #define GG82563_CABLE_LENGTH_TABLE_SIZE \ 81 (sizeof(e1000_gg82563_cable_length_table) / \ 82 sizeof(e1000_gg82563_cable_length_table[0])) 83 84 /** 85 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 86 * @hw: pointer to the HW structure 87 **/ 88 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 89 { 90 struct e1000_phy_info *phy = &hw->phy; 91 s32 ret_val; 92 93 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 94 95 if (hw->phy.media_type != e1000_media_type_copper) { 96 phy->type = e1000_phy_none; 97 return E1000_SUCCESS; 98 } else { 99 phy->ops.power_up = e1000_power_up_phy_copper; 100 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 101 } 102 103 phy->addr = 1; 104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 105 phy->reset_delay_us = 100; 106 phy->type = e1000_phy_gg82563; 107 108 phy->ops.acquire = e1000_acquire_phy_80003es2lan; 109 phy->ops.check_polarity = e1000_check_polarity_m88; 110 phy->ops.check_reset_block = e1000_check_reset_block_generic; 111 phy->ops.commit = e1000_phy_sw_reset_generic; 112 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; 113 phy->ops.get_info = e1000_get_phy_info_m88; 114 phy->ops.release = e1000_release_phy_80003es2lan; 115 phy->ops.reset = e1000_phy_hw_reset_generic; 116 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 117 118 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 119 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; 120 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; 121 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; 122 123 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; 124 125 /* This can only be done after all function pointers are setup. */ 126 ret_val = e1000_get_phy_id(hw); 127 128 /* Verify phy id */ 129 if (phy->id != GG82563_E_PHY_ID) 130 return -E1000_ERR_PHY; 131 132 return ret_val; 133 } 134 135 /** 136 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 137 * @hw: pointer to the HW structure 138 **/ 139 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 140 { 141 struct e1000_nvm_info *nvm = &hw->nvm; 142 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 143 u16 size; 144 145 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 146 147 nvm->opcode_bits = 8; 148 nvm->delay_usec = 1; 149 switch (nvm->override) { 150 case e1000_nvm_override_spi_large: 151 nvm->page_size = 32; 152 nvm->address_bits = 16; 153 break; 154 case e1000_nvm_override_spi_small: 155 nvm->page_size = 8; 156 nvm->address_bits = 8; 157 break; 158 default: 159 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 160 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 161 break; 162 } 163 164 nvm->type = e1000_nvm_eeprom_spi; 165 166 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 167 E1000_EECD_SIZE_EX_SHIFT); 168 169 /* Added to a constant, "size" becomes the left-shift value 170 * for setting word_size. 171 */ 172 size += NVM_WORD_SIZE_BASE_SHIFT; 173 174 /* EEPROM access above 16k is unsupported */ 175 if (size > 14) 176 size = 14; 177 nvm->word_size = 1 << size; 178 179 /* Function Pointers */ 180 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; 181 nvm->ops.read = e1000_read_nvm_eerd; 182 nvm->ops.release = e1000_release_nvm_80003es2lan; 183 nvm->ops.update = e1000_update_nvm_checksum_generic; 184 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 185 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 186 nvm->ops.write = e1000_write_nvm_80003es2lan; 187 188 return E1000_SUCCESS; 189 } 190 191 /** 192 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 193 * @hw: pointer to the HW structure 194 **/ 195 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 196 { 197 struct e1000_mac_info *mac = &hw->mac; 198 199 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 200 201 /* Set media type and media-dependent function pointers */ 202 switch (hw->device_id) { 203 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 204 hw->phy.media_type = e1000_media_type_internal_serdes; 205 mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 206 mac->ops.setup_physical_interface = 207 e1000_setup_fiber_serdes_link_generic; 208 break; 209 default: 210 hw->phy.media_type = e1000_media_type_copper; 211 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 212 mac->ops.setup_physical_interface = 213 e1000_setup_copper_link_80003es2lan; 214 break; 215 } 216 217 /* Set mta register count */ 218 mac->mta_reg_count = 128; 219 /* Set rar entry count */ 220 mac->rar_entry_count = E1000_RAR_ENTRIES; 221 /* Set if part includes ASF firmware */ 222 mac->asf_firmware_present = TRUE; 223 /* FWSM register */ 224 mac->has_fwsm = TRUE; 225 /* ARC supported; valid only if manageability features are enabled. */ 226 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & 227 E1000_FWSM_MODE_MASK); 228 /* Adaptive IFS not supported */ 229 mac->adaptive_ifs = FALSE; 230 231 /* Function pointers */ 232 233 /* bus type/speed/width */ 234 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 235 /* reset */ 236 mac->ops.reset_hw = e1000_reset_hw_80003es2lan; 237 /* hw initialization */ 238 mac->ops.init_hw = e1000_init_hw_80003es2lan; 239 /* link setup */ 240 mac->ops.setup_link = e1000_setup_link_generic; 241 /* check management mode */ 242 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 243 /* multicast address update */ 244 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 245 /* writing VFTA */ 246 mac->ops.write_vfta = e1000_write_vfta_generic; 247 /* clearing VFTA */ 248 mac->ops.clear_vfta = e1000_clear_vfta_generic; 249 /* read mac address */ 250 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; 251 /* ID LED init */ 252 mac->ops.id_led_init = e1000_id_led_init_generic; 253 /* blink LED */ 254 mac->ops.blink_led = e1000_blink_led_generic; 255 /* setup LED */ 256 mac->ops.setup_led = e1000_setup_led_generic; 257 /* cleanup LED */ 258 mac->ops.cleanup_led = e1000_cleanup_led_generic; 259 /* turn on/off LED */ 260 mac->ops.led_on = e1000_led_on_generic; 261 mac->ops.led_off = e1000_led_off_generic; 262 /* clear hardware counters */ 263 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 264 /* link info */ 265 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; 266 267 /* set lan id for port to determine which phy lock to use */ 268 hw->mac.ops.set_lan_id(hw); 269 270 return E1000_SUCCESS; 271 } 272 273 /** 274 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 275 * @hw: pointer to the HW structure 276 * 277 * Called to initialize all function pointers and parameters. 278 **/ 279 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 280 { 281 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 282 283 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; 284 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; 285 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; 286 } 287 288 /** 289 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 290 * @hw: pointer to the HW structure 291 * 292 * A wrapper to acquire access rights to the correct PHY. 293 **/ 294 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 295 { 296 u16 mask; 297 298 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 299 300 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 301 return e1000_acquire_swfw_sync(hw, mask); 302 } 303 304 /** 305 * e1000_release_phy_80003es2lan - Release rights to access PHY 306 * @hw: pointer to the HW structure 307 * 308 * A wrapper to release access rights to the correct PHY. 309 **/ 310 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 311 { 312 u16 mask; 313 314 DEBUGFUNC("e1000_release_phy_80003es2lan"); 315 316 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 317 e1000_release_swfw_sync(hw, mask); 318 } 319 320 /** 321 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register 322 * @hw: pointer to the HW structure 323 * 324 * Acquire the semaphore to access the Kumeran interface. 325 * 326 **/ 327 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) 328 { 329 u16 mask; 330 331 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan"); 332 333 mask = E1000_SWFW_CSR_SM; 334 335 return e1000_acquire_swfw_sync(hw, mask); 336 } 337 338 /** 339 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register 340 * @hw: pointer to the HW structure 341 * 342 * Release the semaphore used to access the Kumeran interface 343 **/ 344 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) 345 { 346 u16 mask; 347 348 DEBUGFUNC("e1000_release_mac_csr_80003es2lan"); 349 350 mask = E1000_SWFW_CSR_SM; 351 352 e1000_release_swfw_sync(hw, mask); 353 } 354 355 /** 356 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 357 * @hw: pointer to the HW structure 358 * 359 * Acquire the semaphore to access the EEPROM. 360 **/ 361 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 362 { 363 s32 ret_val; 364 365 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 366 367 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); 368 if (ret_val) 369 return ret_val; 370 371 ret_val = e1000_acquire_nvm_generic(hw); 372 373 if (ret_val) 374 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM); 375 376 return ret_val; 377 } 378 379 /** 380 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 381 * @hw: pointer to the HW structure 382 * 383 * Release the semaphore used to access the EEPROM. 384 **/ 385 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 386 { 387 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 388 389 e1000_release_nvm_generic(hw); 390 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM); 391 } 392 393 /** 394 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 395 * @hw: pointer to the HW structure 396 * @offset: offset of the register to read 397 * @data: pointer to the data returned from the operation 398 * 399 * Read the GG82563 PHY register. 400 **/ 401 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 402 u32 offset, u16 *data) 403 { 404 s32 ret_val; 405 u32 page_select; 406 u16 temp; 407 408 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 409 410 ret_val = e1000_acquire_phy_80003es2lan(hw); 411 if (ret_val) 412 return ret_val; 413 414 /* Select Configuration Page */ 415 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 416 page_select = GG82563_PHY_PAGE_SELECT; 417 } else { 418 /* Use Alternative Page Select register to access 419 * registers 30 and 31 420 */ 421 page_select = GG82563_PHY_PAGE_SELECT_ALT; 422 } 423 424 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 425 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 426 if (ret_val) { 427 e1000_release_phy_80003es2lan(hw); 428 return ret_val; 429 } 430 431 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 432 /* The "ready" bit in the MDIC register may be incorrectly set 433 * before the device has completed the "Page Select" MDI 434 * transaction. So we wait 200us after each MDI command... 435 */ 436 usec_delay(200); 437 438 /* ...and verify the command was successful. */ 439 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 440 441 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 442 e1000_release_phy_80003es2lan(hw); 443 return -E1000_ERR_PHY; 444 } 445 446 usec_delay(200); 447 448 ret_val = e1000_read_phy_reg_mdic(hw, 449 MAX_PHY_REG_ADDRESS & offset, 450 data); 451 452 usec_delay(200); 453 } else { 454 ret_val = e1000_read_phy_reg_mdic(hw, 455 MAX_PHY_REG_ADDRESS & offset, 456 data); 457 } 458 459 e1000_release_phy_80003es2lan(hw); 460 461 return ret_val; 462 } 463 464 /** 465 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 466 * @hw: pointer to the HW structure 467 * @offset: offset of the register to read 468 * @data: value to write to the register 469 * 470 * Write to the GG82563 PHY register. 471 **/ 472 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 473 u32 offset, u16 data) 474 { 475 s32 ret_val; 476 u32 page_select; 477 u16 temp; 478 479 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 480 481 ret_val = e1000_acquire_phy_80003es2lan(hw); 482 if (ret_val) 483 return ret_val; 484 485 /* Select Configuration Page */ 486 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 487 page_select = GG82563_PHY_PAGE_SELECT; 488 } else { 489 /* Use Alternative Page Select register to access 490 * registers 30 and 31 491 */ 492 page_select = GG82563_PHY_PAGE_SELECT_ALT; 493 } 494 495 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 496 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 497 if (ret_val) { 498 e1000_release_phy_80003es2lan(hw); 499 return ret_val; 500 } 501 502 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 503 /* The "ready" bit in the MDIC register may be incorrectly set 504 * before the device has completed the "Page Select" MDI 505 * transaction. So we wait 200us after each MDI command... 506 */ 507 usec_delay(200); 508 509 /* ...and verify the command was successful. */ 510 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 511 512 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 513 e1000_release_phy_80003es2lan(hw); 514 return -E1000_ERR_PHY; 515 } 516 517 usec_delay(200); 518 519 ret_val = e1000_write_phy_reg_mdic(hw, 520 MAX_PHY_REG_ADDRESS & offset, 521 data); 522 523 usec_delay(200); 524 } else { 525 ret_val = e1000_write_phy_reg_mdic(hw, 526 MAX_PHY_REG_ADDRESS & offset, 527 data); 528 } 529 530 e1000_release_phy_80003es2lan(hw); 531 532 return ret_val; 533 } 534 535 /** 536 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 537 * @hw: pointer to the HW structure 538 * @offset: offset of the register to read 539 * @words: number of words to write 540 * @data: buffer of data to write to the NVM 541 * 542 * Write "words" of data to the ESB2 NVM. 543 **/ 544 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 545 u16 words, u16 *data) 546 { 547 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 548 549 return e1000_write_nvm_spi(hw, offset, words, data); 550 } 551 552 /** 553 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 554 * @hw: pointer to the HW structure 555 * 556 * Wait a specific amount of time for manageability processes to complete. 557 * This is a function pointer entry point called by the phy module. 558 **/ 559 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 560 { 561 s32 timeout = PHY_CFG_TIMEOUT; 562 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 563 564 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 565 566 if (hw->bus.func == 1) 567 mask = E1000_NVM_CFG_DONE_PORT_1; 568 569 while (timeout) { 570 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 571 break; 572 msec_delay(1); 573 timeout--; 574 } 575 if (!timeout) { 576 DEBUGOUT("MNG configuration cycle has not completed.\n"); 577 return -E1000_ERR_RESET; 578 } 579 580 return E1000_SUCCESS; 581 } 582 583 /** 584 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 585 * @hw: pointer to the HW structure 586 * 587 * Force the speed and duplex settings onto the PHY. This is a 588 * function pointer entry point called by the phy module. 589 **/ 590 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 591 { 592 s32 ret_val; 593 u16 phy_data; 594 bool link; 595 596 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 597 598 if (!(hw->phy.ops.read_reg)) 599 return E1000_SUCCESS; 600 601 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 602 * forced whenever speed and duplex are forced. 603 */ 604 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 605 if (ret_val) 606 return ret_val; 607 608 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 609 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 610 if (ret_val) 611 return ret_val; 612 613 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 614 615 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); 616 if (ret_val) 617 return ret_val; 618 619 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 620 621 /* Reset the phy to commit changes. */ 622 phy_data |= MII_CR_RESET; 623 624 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); 625 if (ret_val) 626 return ret_val; 627 628 usec_delay(1); 629 630 if (hw->phy.autoneg_wait_to_complete) { 631 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n"); 632 633 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 634 100000, &link); 635 if (ret_val) 636 return ret_val; 637 638 if (!link) { 639 /* We didn't get link. 640 * Reset the DSP and cross our fingers. 641 */ 642 ret_val = e1000_phy_reset_dsp_generic(hw); 643 if (ret_val) 644 return ret_val; 645 } 646 647 /* Try once more */ 648 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 649 100000, &link); 650 if (ret_val) 651 return ret_val; 652 } 653 654 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 655 &phy_data); 656 if (ret_val) 657 return ret_val; 658 659 /* Resetting the phy means we need to verify the TX_CLK corresponds 660 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 661 */ 662 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 663 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 664 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 665 else 666 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 667 668 /* In addition, we must re-enable CRS on Tx for both half and full 669 * duplex. 670 */ 671 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 672 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 673 phy_data); 674 675 return ret_val; 676 } 677 678 /** 679 * e1000_get_cable_length_80003es2lan - Set approximate cable length 680 * @hw: pointer to the HW structure 681 * 682 * Find the approximate cable length as measured by the GG82563 PHY. 683 * This is a function pointer entry point called by the phy module. 684 **/ 685 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 686 { 687 struct e1000_phy_info *phy = &hw->phy; 688 s32 ret_val; 689 u16 phy_data, index; 690 691 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 692 693 if (!(hw->phy.ops.read_reg)) 694 return E1000_SUCCESS; 695 696 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 697 if (ret_val) 698 return ret_val; 699 700 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 701 702 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) 703 return -E1000_ERR_PHY; 704 705 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 706 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; 707 708 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 709 710 return E1000_SUCCESS; 711 } 712 713 /** 714 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 715 * @hw: pointer to the HW structure 716 * @speed: pointer to speed buffer 717 * @duplex: pointer to duplex buffer 718 * 719 * Retrieve the current speed and duplex configuration. 720 **/ 721 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 722 u16 *duplex) 723 { 724 s32 ret_val; 725 726 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 727 728 if (hw->phy.media_type == e1000_media_type_copper) { 729 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 730 duplex); 731 hw->phy.ops.cfg_on_link_up(hw); 732 } else { 733 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 734 speed, 735 duplex); 736 } 737 738 return ret_val; 739 } 740 741 /** 742 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 743 * @hw: pointer to the HW structure 744 * 745 * Perform a global reset to the ESB2 controller. 746 **/ 747 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 748 { 749 u32 ctrl; 750 s32 ret_val; 751 u16 kum_reg_data; 752 753 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 754 755 /* Prevent the PCI-E bus from sticking if there is no TLP connection 756 * on the last TLP read/write transaction when MAC is reset. 757 */ 758 ret_val = e1000_disable_pcie_master_generic(hw); 759 if (ret_val) 760 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 761 762 DEBUGOUT("Masking off all interrupts\n"); 763 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 764 765 E1000_WRITE_REG(hw, E1000_RCTL, 0); 766 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 767 E1000_WRITE_FLUSH(hw); 768 769 msec_delay(10); 770 771 ctrl = E1000_READ_REG(hw, E1000_CTRL); 772 773 ret_val = e1000_acquire_phy_80003es2lan(hw); 774 if (ret_val) 775 return ret_val; 776 777 DEBUGOUT("Issuing a global reset to MAC\n"); 778 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 779 e1000_release_phy_80003es2lan(hw); 780 781 /* Disable IBIST slave mode (far-end loopback) */ 782 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 783 E1000_KMRNCTRLSTA_INBAND_PARAM, &kum_reg_data); 784 if (!ret_val) { 785 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 786 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 787 E1000_KMRNCTRLSTA_INBAND_PARAM, 788 kum_reg_data); 789 if (ret_val) 790 DEBUGOUT("Error disabling far-end loopback\n"); 791 } else 792 DEBUGOUT("Error disabling far-end loopback\n"); 793 794 ret_val = e1000_get_auto_rd_done_generic(hw); 795 if (ret_val) 796 /* We don't want to continue accessing MAC registers. */ 797 return ret_val; 798 799 /* Clear any pending interrupt events. */ 800 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 801 E1000_READ_REG(hw, E1000_ICR); 802 803 return e1000_check_alt_mac_addr_generic(hw); 804 } 805 806 /** 807 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 808 * @hw: pointer to the HW structure 809 * 810 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 811 **/ 812 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 813 { 814 struct e1000_mac_info *mac = &hw->mac; 815 u32 reg_data; 816 s32 ret_val; 817 u16 kum_reg_data; 818 u16 i; 819 820 DEBUGFUNC("e1000_init_hw_80003es2lan"); 821 822 e1000_initialize_hw_bits_80003es2lan(hw); 823 824 /* Initialize identification LED */ 825 ret_val = mac->ops.id_led_init(hw); 826 /* An error is not fatal and we should not stop init due to this */ 827 if (ret_val) 828 DEBUGOUT("Error initializing identification LED\n"); 829 830 /* Disabling VLAN filtering */ 831 DEBUGOUT("Initializing the IEEE VLAN\n"); 832 mac->ops.clear_vfta(hw); 833 834 /* Setup the receive address. */ 835 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 836 837 /* Zero out the Multicast HASH table */ 838 DEBUGOUT("Zeroing the MTA\n"); 839 for (i = 0; i < mac->mta_reg_count; i++) 840 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 841 842 /* Setup link and flow control */ 843 ret_val = mac->ops.setup_link(hw); 844 if (ret_val) 845 return ret_val; 846 847 /* Disable IBIST slave mode (far-end loopback) */ 848 ret_val = 849 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 850 &kum_reg_data); 851 if (!ret_val) { 852 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 853 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 854 E1000_KMRNCTRLSTA_INBAND_PARAM, 855 kum_reg_data); 856 if (ret_val) 857 DEBUGOUT("Error disabling far-end loopback\n"); 858 } else 859 DEBUGOUT("Error disabling far-end loopback\n"); 860 861 /* Set the transmit descriptor write-back policy */ 862 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 863 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 864 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 865 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 866 867 /* ...for both queues. */ 868 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 869 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 870 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 871 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 872 873 /* Enable retransmit on late collisions */ 874 reg_data = E1000_READ_REG(hw, E1000_TCTL); 875 reg_data |= E1000_TCTL_RTLC; 876 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 877 878 /* Configure Gigabit Carry Extend Padding */ 879 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 880 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 881 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 882 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 883 884 /* Configure Transmit Inter-Packet Gap */ 885 reg_data = E1000_READ_REG(hw, E1000_TIPG); 886 reg_data &= ~E1000_TIPG_IPGT_MASK; 887 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 888 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 889 890 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 891 reg_data &= ~0x00100000; 892 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 893 894 /* default to TRUE to enable the MDIC W/A */ 895 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE; 896 897 ret_val = 898 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >> 899 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i); 900 if (!ret_val) { 901 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == 902 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) 903 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE; 904 } 905 906 /* Clear all of the statistics registers (clear on read). It is 907 * important that we do this after we have tried to establish link 908 * because the symbol error count will increment wildly if there 909 * is no link. 910 */ 911 e1000_clear_hw_cntrs_80003es2lan(hw); 912 913 return ret_val; 914 } 915 916 /** 917 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 918 * @hw: pointer to the HW structure 919 * 920 * Initializes required hardware-dependent bits needed for normal operation. 921 **/ 922 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 923 { 924 u32 reg; 925 926 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 927 928 /* Transmit Descriptor Control 0 */ 929 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 930 reg |= (1 << 22); 931 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 932 933 /* Transmit Descriptor Control 1 */ 934 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 935 reg |= (1 << 22); 936 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 937 938 /* Transmit Arbitration Control 0 */ 939 reg = E1000_READ_REG(hw, E1000_TARC(0)); 940 reg &= ~(0xF << 27); /* 30:27 */ 941 if (hw->phy.media_type != e1000_media_type_copper) 942 reg &= ~(1 << 20); 943 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 944 945 /* Transmit Arbitration Control 1 */ 946 reg = E1000_READ_REG(hw, E1000_TARC(1)); 947 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 948 reg &= ~(1 << 28); 949 else 950 reg |= (1 << 28); 951 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 952 953 /* Disable IPv6 extension header parsing because some malformed 954 * IPv6 headers can hang the Rx. 955 */ 956 reg = E1000_READ_REG(hw, E1000_RFCTL); 957 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 958 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 959 960 return; 961 } 962 963 /** 964 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 965 * @hw: pointer to the HW structure 966 * 967 * Setup some GG82563 PHY registers for obtaining link 968 **/ 969 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 970 { 971 struct e1000_phy_info *phy = &hw->phy; 972 s32 ret_val; 973 u32 reg; 974 u16 data; 975 976 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 977 978 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); 979 if (ret_val) 980 return ret_val; 981 982 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 983 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 984 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 985 986 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); 987 if (ret_val) 988 return ret_val; 989 990 /* Options: 991 * MDI/MDI-X = 0 (default) 992 * 0 - Auto for all speeds 993 * 1 - MDI mode 994 * 2 - MDI-X mode 995 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 996 */ 997 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 998 if (ret_val) 999 return ret_val; 1000 1001 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1002 1003 switch (phy->mdix) { 1004 case 1: 1005 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1006 break; 1007 case 2: 1008 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1009 break; 1010 case 0: 1011 default: 1012 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1013 break; 1014 } 1015 1016 /* Options: 1017 * disable_polarity_correction = 0 (default) 1018 * Automatic Correction for Reversed Cable Polarity 1019 * 0 - Disabled 1020 * 1 - Enabled 1021 */ 1022 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1023 if (phy->disable_polarity_correction) 1024 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1025 1026 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1027 if (ret_val) 1028 return ret_val; 1029 1030 /* SW Reset the PHY so all changes take effect */ 1031 ret_val = hw->phy.ops.commit(hw); 1032 if (ret_val) { 1033 DEBUGOUT("Error Resetting the PHY\n"); 1034 return ret_val; 1035 } 1036 1037 /* Bypass Rx and Tx FIFO's */ 1038 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL; 1039 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1040 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1041 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 1042 if (ret_val) 1043 return ret_val; 1044 1045 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE; 1046 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data); 1047 if (ret_val) 1048 return ret_val; 1049 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1050 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 1051 if (ret_val) 1052 return ret_val; 1053 1054 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1055 if (ret_val) 1056 return ret_val; 1057 1058 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1059 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1060 if (ret_val) 1061 return ret_val; 1062 1063 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1064 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1065 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1066 1067 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1068 if (ret_val) 1069 return ret_val; 1070 1071 /* Do not init these registers when the HW is in IAMT mode, since the 1072 * firmware will have already initialized them. We only initialize 1073 * them if the HW is not in IAMT mode. 1074 */ 1075 if (!hw->mac.ops.check_mng_mode(hw)) { 1076 /* Enable Electrical Idle on the PHY */ 1077 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1078 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1079 data); 1080 if (ret_val) 1081 return ret_val; 1082 1083 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1084 &data); 1085 if (ret_val) 1086 return ret_val; 1087 1088 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1089 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1090 data); 1091 if (ret_val) 1092 return ret_val; 1093 } 1094 1095 /* Workaround: Disable padding in Kumeran interface in the MAC 1096 * and in the PHY to avoid CRC errors. 1097 */ 1098 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1099 if (ret_val) 1100 return ret_val; 1101 1102 data |= GG82563_ICR_DIS_PADDING; 1103 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1104 if (ret_val) 1105 return ret_val; 1106 1107 return E1000_SUCCESS; 1108 } 1109 1110 /** 1111 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1112 * @hw: pointer to the HW structure 1113 * 1114 * Essentially a wrapper for setting up all things "copper" related. 1115 * This is a function pointer entry point called by the mac module. 1116 **/ 1117 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1118 { 1119 u32 ctrl; 1120 s32 ret_val; 1121 u16 reg_data; 1122 1123 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1124 1125 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1126 ctrl |= E1000_CTRL_SLU; 1127 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1128 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1129 1130 /* Set the mac to wait the maximum time between each 1131 * iteration and increase the max iterations when 1132 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1133 */ 1134 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1135 0xFFFF); 1136 if (ret_val) 1137 return ret_val; 1138 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1139 ®_data); 1140 if (ret_val) 1141 return ret_val; 1142 reg_data |= 0x3F; 1143 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1144 reg_data); 1145 if (ret_val) 1146 return ret_val; 1147 ret_val = 1148 e1000_read_kmrn_reg_80003es2lan(hw, 1149 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1150 ®_data); 1151 if (ret_val) 1152 return ret_val; 1153 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1154 ret_val = 1155 e1000_write_kmrn_reg_80003es2lan(hw, 1156 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1157 reg_data); 1158 if (ret_val) 1159 return ret_val; 1160 1161 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1162 if (ret_val) 1163 return ret_val; 1164 1165 return e1000_setup_copper_link_generic(hw); 1166 } 1167 1168 /** 1169 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up 1170 * @hw: pointer to the HW structure 1171 * @duplex: current duplex setting 1172 * 1173 * Configure the KMRN interface by applying last minute quirks for 1174 * 10/100 operation. 1175 **/ 1176 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) 1177 { 1178 s32 ret_val = E1000_SUCCESS; 1179 u16 speed; 1180 u16 duplex; 1181 1182 DEBUGFUNC("e1000_configure_on_link_up"); 1183 1184 if (hw->phy.media_type == e1000_media_type_copper) { 1185 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed, 1186 &duplex); 1187 if (ret_val) 1188 return ret_val; 1189 1190 if (speed == SPEED_1000) 1191 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 1192 else 1193 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); 1194 } 1195 1196 return ret_val; 1197 } 1198 1199 /** 1200 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1201 * @hw: pointer to the HW structure 1202 * @duplex: current duplex setting 1203 * 1204 * Configure the KMRN interface by applying last minute quirks for 1205 * 10/100 operation. 1206 **/ 1207 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1208 { 1209 s32 ret_val; 1210 u32 tipg; 1211 u32 i = 0; 1212 u16 reg_data, reg_data2; 1213 1214 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1215 1216 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1217 ret_val = 1218 e1000_write_kmrn_reg_80003es2lan(hw, 1219 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1220 reg_data); 1221 if (ret_val) 1222 return ret_val; 1223 1224 /* Configure Transmit Inter-Packet Gap */ 1225 tipg = E1000_READ_REG(hw, E1000_TIPG); 1226 tipg &= ~E1000_TIPG_IPGT_MASK; 1227 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1228 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1229 1230 do { 1231 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1232 ®_data); 1233 if (ret_val) 1234 return ret_val; 1235 1236 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1237 ®_data2); 1238 if (ret_val) 1239 return ret_val; 1240 i++; 1241 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1242 1243 if (duplex == HALF_DUPLEX) 1244 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1245 else 1246 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1247 1248 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1249 } 1250 1251 /** 1252 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1253 * @hw: pointer to the HW structure 1254 * 1255 * Configure the KMRN interface by applying last minute quirks for 1256 * gigabit operation. 1257 **/ 1258 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1259 { 1260 s32 ret_val; 1261 u16 reg_data, reg_data2; 1262 u32 tipg; 1263 u32 i = 0; 1264 1265 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1266 1267 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1268 ret_val = 1269 e1000_write_kmrn_reg_80003es2lan(hw, 1270 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1271 reg_data); 1272 if (ret_val) 1273 return ret_val; 1274 1275 /* Configure Transmit Inter-Packet Gap */ 1276 tipg = E1000_READ_REG(hw, E1000_TIPG); 1277 tipg &= ~E1000_TIPG_IPGT_MASK; 1278 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1279 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1280 1281 do { 1282 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1283 ®_data); 1284 if (ret_val) 1285 return ret_val; 1286 1287 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1288 ®_data2); 1289 if (ret_val) 1290 return ret_val; 1291 i++; 1292 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1293 1294 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1295 1296 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1297 } 1298 1299 /** 1300 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register 1301 * @hw: pointer to the HW structure 1302 * @offset: register offset to be read 1303 * @data: pointer to the read data 1304 * 1305 * Acquire semaphore, then read the PHY register at offset 1306 * using the kumeran interface. The information retrieved is stored in data. 1307 * Release the semaphore before exiting. 1308 **/ 1309 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1310 u16 *data) 1311 { 1312 u32 kmrnctrlsta; 1313 s32 ret_val; 1314 1315 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan"); 1316 1317 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1318 if (ret_val) 1319 return ret_val; 1320 1321 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1322 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1323 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1324 E1000_WRITE_FLUSH(hw); 1325 1326 usec_delay(2); 1327 1328 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 1329 *data = (u16)kmrnctrlsta; 1330 1331 e1000_release_mac_csr_80003es2lan(hw); 1332 1333 return ret_val; 1334 } 1335 1336 /** 1337 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register 1338 * @hw: pointer to the HW structure 1339 * @offset: register offset to write to 1340 * @data: data to write at register offset 1341 * 1342 * Acquire semaphore, then write the data to PHY register 1343 * at the offset using the kumeran interface. Release semaphore 1344 * before exiting. 1345 **/ 1346 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1347 u16 data) 1348 { 1349 u32 kmrnctrlsta; 1350 s32 ret_val; 1351 1352 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan"); 1353 1354 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1355 if (ret_val) 1356 return ret_val; 1357 1358 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1359 E1000_KMRNCTRLSTA_OFFSET) | data; 1360 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1361 E1000_WRITE_FLUSH(hw); 1362 1363 usec_delay(2); 1364 1365 e1000_release_mac_csr_80003es2lan(hw); 1366 1367 return ret_val; 1368 } 1369 1370 /** 1371 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1372 * @hw: pointer to the HW structure 1373 **/ 1374 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1375 { 1376 s32 ret_val; 1377 1378 DEBUGFUNC("e1000_read_mac_addr_80003es2lan"); 1379 1380 /* If there's an alternate MAC address place it in RAR0 1381 * so that it will override the Si installed default perm 1382 * address. 1383 */ 1384 ret_val = e1000_check_alt_mac_addr_generic(hw); 1385 if (ret_val) 1386 return ret_val; 1387 1388 return e1000_read_mac_addr_generic(hw); 1389 } 1390 1391 /** 1392 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1393 * @hw: pointer to the HW structure 1394 * 1395 * In the case of a PHY power down to save power, or to turn off link during a 1396 * driver unload, or wake on lan is not enabled, remove the link. 1397 **/ 1398 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1399 { 1400 /* If the management interface is not enabled, then power down */ 1401 if (!(hw->mac.ops.check_mng_mode(hw) || 1402 hw->phy.ops.check_reset_block(hw))) 1403 e1000_power_down_phy_copper(hw); 1404 1405 return; 1406 } 1407 1408 /** 1409 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1410 * @hw: pointer to the HW structure 1411 * 1412 * Clears the hardware counters by reading the counter registers. 1413 **/ 1414 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1415 { 1416 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1417 1418 e1000_clear_hw_cntrs_base_generic(hw); 1419 1420 E1000_READ_REG(hw, E1000_PRC64); 1421 E1000_READ_REG(hw, E1000_PRC127); 1422 E1000_READ_REG(hw, E1000_PRC255); 1423 E1000_READ_REG(hw, E1000_PRC511); 1424 E1000_READ_REG(hw, E1000_PRC1023); 1425 E1000_READ_REG(hw, E1000_PRC1522); 1426 E1000_READ_REG(hw, E1000_PTC64); 1427 E1000_READ_REG(hw, E1000_PTC127); 1428 E1000_READ_REG(hw, E1000_PTC255); 1429 E1000_READ_REG(hw, E1000_PTC511); 1430 E1000_READ_REG(hw, E1000_PTC1023); 1431 E1000_READ_REG(hw, E1000_PTC1522); 1432 1433 E1000_READ_REG(hw, E1000_ALGNERRC); 1434 E1000_READ_REG(hw, E1000_RXERRC); 1435 E1000_READ_REG(hw, E1000_TNCRS); 1436 E1000_READ_REG(hw, E1000_CEXTERR); 1437 E1000_READ_REG(hw, E1000_TSCTC); 1438 E1000_READ_REG(hw, E1000_TSCTFC); 1439 1440 E1000_READ_REG(hw, E1000_MGTPRC); 1441 E1000_READ_REG(hw, E1000_MGTPDC); 1442 E1000_READ_REG(hw, E1000_MGTPTC); 1443 1444 E1000_READ_REG(hw, E1000_IAC); 1445 E1000_READ_REG(hw, E1000_ICRXOC); 1446 1447 E1000_READ_REG(hw, E1000_ICRXPTC); 1448 E1000_READ_REG(hw, E1000_ICRXATC); 1449 E1000_READ_REG(hw, E1000_ICTXPTC); 1450 E1000_READ_REG(hw, E1000_ICTXATC); 1451 E1000_READ_REG(hw, E1000_ICTXQEC); 1452 E1000_READ_REG(hw, E1000_ICTXQMTC); 1453 E1000_READ_REG(hw, E1000_ICRXDMTC); 1454 } 1455