1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * 4 * This software was developed by SRI International and the University of 5 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 6 * ("CTSRD"), as part of the DARPA CRASH research programme. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Ethernet media access controller (EMAC) 32 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 33 * 34 * EMAC is an instance of the Synopsys DesignWare 3504-0 35 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 36 */ 37 38 #ifndef __IF_DWCVAR_H__ 39 #define __IF_DWCVAR_H__ 40 41 /* 42 * Driver data and defines. 43 */ 44 #define RX_DESC_COUNT 1024 45 #define RX_DESC_SIZE (sizeof(struct dwc_hwdesc) * RX_DESC_COUNT) 46 #define TX_DESC_COUNT 1024 47 #define TX_MAP_COUNT TX_DESC_COUNT 48 #define TX_DESC_SIZE (sizeof(struct dwc_hwdesc) * TX_DESC_COUNT) 49 #define TX_MAP_MAX_SEGS 32 50 51 #define DMA_DEFAULT_PBL 8 52 53 struct dwc_bufmap { 54 bus_dmamap_t map; 55 struct mbuf *mbuf; 56 /* Only used for TX descirptors */ 57 int last_desc_idx; 58 }; 59 60 struct dwc_softc { 61 struct resource *res[2]; 62 device_t dev; 63 phandle_t node; 64 int mii_clk; 65 device_t miibus; 66 struct mii_data * mii_softc; 67 if_t ifp; 68 int if_flags; 69 struct mtx mtx; 70 void * intr_cookie; 71 struct callout dwc_callout; 72 bool link_is_up; 73 bool is_attached; 74 bool is_detaching; 75 int tx_watchdog_count; 76 int stats_harvest_count; 77 int phy_mode; 78 79 /* clocks and reset */ 80 clk_t clk_stmmaceth; 81 clk_t clk_pclk; 82 hwreset_t rst_stmmaceth; 83 hwreset_t rst_ahb; 84 85 /* DMA config */ 86 uint32_t txpbl; /* TX Burst lenght */ 87 uint32_t rxpbl; /* RX Burst lenght */ 88 bool nopblx8; 89 bool fixed_burst; 90 bool mixed_burst; 91 bool aal; 92 bool dma_ext_desc; 93 94 /* RX */ 95 bus_dma_tag_t rxdesc_tag; 96 bus_dmamap_t rxdesc_map; 97 struct dwc_hwdesc *rxdesc_ring; 98 bus_addr_t rxdesc_ring_paddr; 99 bus_dma_tag_t rxbuf_tag; 100 struct dwc_bufmap rxbuf_map[RX_DESC_COUNT]; 101 uint32_t rx_idx; 102 103 /* TX */ 104 bus_dma_tag_t txdesc_tag; 105 bus_dmamap_t txdesc_map; 106 struct dwc_hwdesc *txdesc_ring; 107 bus_addr_t txdesc_ring_paddr; 108 bus_dma_tag_t txbuf_tag; 109 struct dwc_bufmap txbuf_map[TX_DESC_COUNT]; 110 uint32_t tx_desc_head; 111 uint32_t tx_desc_tail; 112 uint32_t tx_map_head; 113 uint32_t tx_map_tail; 114 int tx_desccount; 115 int tx_mapcount; 116 }; 117 118 #define READ4(_sc, _reg) \ 119 bus_read_4((_sc)->res[0], _reg) 120 #define WRITE4(_sc, _reg, _val) \ 121 bus_write_4((_sc)->res[0], _reg, _val) 122 123 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) 124 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 125 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 126 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 127 128 #endif /* __IF_DWCVAR_H__ */ 129