1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Ethernet media access controller (EMAC) 33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 * 35 * EMAC is an instance of the Synopsys DesignWare 3504-0 36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/malloc.h> 48 #include <sys/rman.h> 49 #include <sys/timeet.h> 50 #include <sys/timetc.h> 51 #include <sys/endian.h> 52 #include <sys/lock.h> 53 #include <sys/mbuf.h> 54 #include <sys/mutex.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 59 #include <dev/fdt/fdt_common.h> 60 #include <dev/ofw/openfirm.h> 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 64 #include <net/bpf.h> 65 #include <net/if.h> 66 #include <net/ethernet.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_types.h> 70 #include <net/if_var.h> 71 #include <net/if_vlan_var.h> 72 73 #include <machine/bus.h> 74 #include <machine/fdt.h> 75 #include <machine/cpu.h> 76 #include <machine/intr.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include "miibus_if.h" 81 82 #define READ4(_sc, _reg) \ 83 bus_read_4((_sc)->res[0], _reg) 84 #define WRITE4(_sc, _reg, _val) \ 85 bus_write_4((_sc)->res[0], _reg, _val) 86 87 #define WATCHDOG_TIMEOUT_SECS 5 88 #define STATS_HARVEST_INTERVAL 2 89 #define MII_CLK_VAL 2 90 91 #include <dev/dwc/if_dwc.h> 92 93 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) 94 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 95 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 96 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 97 98 #define DDESC_TDES0_OWN (1 << 31) 99 #define DDESC_TDES0_TXINT (1 << 30) 100 #define DDESC_TDES0_TXLAST (1 << 29) 101 #define DDESC_TDES0_TXFIRST (1 << 28) 102 #define DDESC_TDES0_TXCRCDIS (1 << 27) 103 #define DDESC_TDES0_TXRINGEND (1 << 21) 104 #define DDESC_TDES0_TXCHAIN (1 << 20) 105 106 #define DDESC_RDES0_OWN (1 << 31) 107 #define DDESC_RDES0_FL_MASK 0x3fff 108 #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ 109 #define DDESC_RDES1_CHAINED (1 << 14) 110 111 struct dwc_bufmap { 112 bus_dmamap_t map; 113 struct mbuf *mbuf; 114 }; 115 116 /* 117 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 118 * layout, but the bits in the flags field have different meanings. 119 */ 120 struct dwc_hwdesc 121 { 122 uint32_t tdes0; 123 uint32_t tdes1; 124 uint32_t addr; /* pointer to buffer data */ 125 uint32_t addr_next; /* link to next descriptor */ 126 }; 127 128 /* 129 * Driver data and defines. 130 */ 131 #define RX_DESC_COUNT 1024 132 #define RX_DESC_SIZE (sizeof(struct dwc_hwdesc) * RX_DESC_COUNT) 133 #define TX_DESC_COUNT 1024 134 #define TX_DESC_SIZE (sizeof(struct dwc_hwdesc) * TX_DESC_COUNT) 135 136 /* 137 * The hardware imposes alignment restrictions on various objects involved in 138 * DMA transfers. These values are expressed in bytes (not bits). 139 */ 140 #define DWC_DESC_RING_ALIGN 2048 141 142 struct dwc_softc { 143 struct resource *res[2]; 144 bus_space_tag_t bst; 145 bus_space_handle_t bsh; 146 device_t dev; 147 int mii_clk; 148 device_t miibus; 149 struct mii_data * mii_softc; 150 struct ifnet *ifp; 151 int if_flags; 152 struct mtx mtx; 153 void * intr_cookie; 154 struct callout dwc_callout; 155 uint8_t phy_conn_type; 156 uint8_t mactype; 157 boolean_t link_is_up; 158 boolean_t is_attached; 159 boolean_t is_detaching; 160 int tx_watchdog_count; 161 int stats_harvest_count; 162 163 /* RX */ 164 bus_dma_tag_t rxdesc_tag; 165 bus_dmamap_t rxdesc_map; 166 struct dwc_hwdesc *rxdesc_ring; 167 bus_addr_t rxdesc_ring_paddr; 168 bus_dma_tag_t rxbuf_tag; 169 struct dwc_bufmap rxbuf_map[RX_DESC_COUNT]; 170 uint32_t rx_idx; 171 172 /* TX */ 173 bus_dma_tag_t txdesc_tag; 174 bus_dmamap_t txdesc_map; 175 struct dwc_hwdesc *txdesc_ring; 176 bus_addr_t txdesc_ring_paddr; 177 bus_dma_tag_t txbuf_tag; 178 struct dwc_bufmap txbuf_map[RX_DESC_COUNT]; 179 uint32_t tx_idx_head; 180 uint32_t tx_idx_tail; 181 int txcount; 182 }; 183 184 static struct resource_spec dwc_spec[] = { 185 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 186 { SYS_RES_IRQ, 0, RF_ACTIVE }, 187 { -1, 0 } 188 }; 189 190 static void dwc_txfinish_locked(struct dwc_softc *sc); 191 static void dwc_rxfinish_locked(struct dwc_softc *sc); 192 static void dwc_stop_locked(struct dwc_softc *sc); 193 static void dwc_setup_rxfilter(struct dwc_softc *sc); 194 195 static inline uint32_t 196 next_rxidx(struct dwc_softc *sc, uint32_t curidx) 197 { 198 199 return ((curidx + 1) % RX_DESC_COUNT); 200 } 201 202 static inline uint32_t 203 next_txidx(struct dwc_softc *sc, uint32_t curidx) 204 { 205 206 return ((curidx + 1) % TX_DESC_COUNT); 207 } 208 209 static void 210 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 211 { 212 213 if (error != 0) 214 return; 215 *(bus_addr_t *)arg = segs[0].ds_addr; 216 } 217 218 inline static uint32_t 219 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, 220 uint32_t len) 221 { 222 uint32_t flags; 223 uint32_t nidx; 224 225 nidx = next_txidx(sc, idx); 226 227 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 228 if (paddr == 0 || len == 0) { 229 flags = 0; 230 --sc->txcount; 231 } else { 232 flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST 233 | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT; 234 ++sc->txcount; 235 } 236 237 sc->txdesc_ring[idx].addr = (uint32_t)(paddr); 238 sc->txdesc_ring[idx].tdes0 = flags; 239 sc->txdesc_ring[idx].tdes1 = len; 240 241 if (paddr && len) { 242 wmb(); 243 sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN; 244 wmb(); 245 } 246 247 return (nidx); 248 } 249 250 static int 251 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) 252 { 253 struct bus_dma_segment seg; 254 int error, nsegs; 255 struct mbuf * m; 256 257 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 258 return (ENOMEM); 259 *mp = m; 260 261 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 262 m, &seg, &nsegs, 0); 263 if (error != 0) { 264 return (ENOMEM); 265 } 266 267 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 268 269 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 270 BUS_DMASYNC_PREWRITE); 271 272 sc->txbuf_map[idx].mbuf = m; 273 274 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 275 276 return (0); 277 } 278 279 static void 280 dwc_txstart_locked(struct dwc_softc *sc) 281 { 282 struct ifnet *ifp; 283 struct mbuf *m; 284 int enqueued; 285 286 DWC_ASSERT_LOCKED(sc); 287 288 if (!sc->link_is_up) 289 return; 290 291 ifp = sc->ifp; 292 293 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 294 return; 295 } 296 297 enqueued = 0; 298 299 for (;;) { 300 if (sc->txcount == (TX_DESC_COUNT-1)) { 301 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 302 break; 303 } 304 305 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 306 if (m == NULL) 307 break; 308 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 309 IFQ_DRV_PREPEND(&ifp->if_snd, m); 310 break; 311 } 312 BPF_MTAP(ifp, m); 313 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 314 ++enqueued; 315 } 316 317 if (enqueued != 0) { 318 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 319 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 320 } 321 } 322 323 static void 324 dwc_txstart(struct ifnet *ifp) 325 { 326 struct dwc_softc *sc = ifp->if_softc; 327 328 DWC_LOCK(sc); 329 dwc_txstart_locked(sc); 330 DWC_UNLOCK(sc); 331 } 332 333 static void 334 dwc_stop_locked(struct dwc_softc *sc) 335 { 336 struct ifnet *ifp; 337 int reg; 338 339 DWC_ASSERT_LOCKED(sc); 340 341 ifp = sc->ifp; 342 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 343 sc->tx_watchdog_count = 0; 344 sc->stats_harvest_count = 0; 345 346 callout_stop(&sc->dwc_callout); 347 348 /* Stop DMA TX */ 349 reg = READ4(sc, OPERATION_MODE); 350 reg &= ~(MODE_ST); 351 WRITE4(sc, OPERATION_MODE, reg); 352 353 /* Flush TX */ 354 reg = READ4(sc, OPERATION_MODE); 355 reg |= (MODE_FTF); 356 WRITE4(sc, OPERATION_MODE, reg); 357 358 /* Stop transmitters */ 359 reg = READ4(sc, MAC_CONFIGURATION); 360 reg &= ~(CONF_TE | CONF_RE); 361 WRITE4(sc, MAC_CONFIGURATION, reg); 362 363 /* Stop DMA RX */ 364 reg = READ4(sc, OPERATION_MODE); 365 reg &= ~(MODE_SR); 366 WRITE4(sc, OPERATION_MODE, reg); 367 } 368 369 static void dwc_clear_stats(struct dwc_softc *sc) 370 { 371 int reg; 372 373 reg = READ4(sc, MMC_CONTROL); 374 reg |= (MMC_CONTROL_CNTRST); 375 WRITE4(sc, MMC_CONTROL, reg); 376 } 377 378 static void 379 dwc_harvest_stats(struct dwc_softc *sc) 380 { 381 struct ifnet *ifp; 382 383 /* We don't need to harvest too often. */ 384 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 385 return; 386 387 sc->stats_harvest_count = 0; 388 ifp = sc->ifp; 389 390 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); 391 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); 392 if_inc_counter(ifp, IFCOUNTER_IERRORS, 393 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + 394 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + 395 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + 396 READ4(sc, RXLENGTHERROR)); 397 398 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); 399 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); 400 if_inc_counter(ifp, IFCOUNTER_OERRORS, 401 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + 402 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); 403 404 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 405 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); 406 407 dwc_clear_stats(sc); 408 } 409 410 static void 411 dwc_tick(void *arg) 412 { 413 struct dwc_softc *sc; 414 struct ifnet *ifp; 415 int link_was_up; 416 417 sc = arg; 418 419 DWC_ASSERT_LOCKED(sc); 420 421 ifp = sc->ifp; 422 423 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 424 return; 425 426 /* 427 * Typical tx watchdog. If this fires it indicates that we enqueued 428 * packets for output and never got a txdone interrupt for them. Maybe 429 * it's a missed interrupt somehow, just pretend we got one. 430 */ 431 if (sc->tx_watchdog_count > 0) { 432 if (--sc->tx_watchdog_count == 0) { 433 dwc_txfinish_locked(sc); 434 } 435 } 436 437 /* Gather stats from hardware counters. */ 438 dwc_harvest_stats(sc); 439 440 /* Check the media status. */ 441 link_was_up = sc->link_is_up; 442 mii_tick(sc->mii_softc); 443 if (sc->link_is_up && !link_was_up) 444 dwc_txstart_locked(sc); 445 446 /* Schedule another check one second from now. */ 447 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 448 } 449 450 static void 451 dwc_init_locked(struct dwc_softc *sc) 452 { 453 struct ifnet *ifp = sc->ifp; 454 int reg; 455 456 DWC_ASSERT_LOCKED(sc); 457 458 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 459 return; 460 461 ifp->if_drv_flags |= IFF_DRV_RUNNING; 462 463 dwc_setup_rxfilter(sc); 464 465 /* Initializa DMA and enable transmitters */ 466 reg = READ4(sc, OPERATION_MODE); 467 reg |= (MODE_TSF | MODE_OSF | MODE_FUF); 468 reg &= ~(MODE_RSF); 469 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); 470 WRITE4(sc, OPERATION_MODE, reg); 471 472 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 473 474 /* Start DMA */ 475 reg = READ4(sc, OPERATION_MODE); 476 reg |= (MODE_ST | MODE_SR); 477 WRITE4(sc, OPERATION_MODE, reg); 478 479 /* Enable transmitters */ 480 reg = READ4(sc, MAC_CONFIGURATION); 481 reg |= (CONF_JD | CONF_ACS | CONF_BE); 482 reg |= (CONF_TE | CONF_RE); 483 WRITE4(sc, MAC_CONFIGURATION, reg); 484 485 /* 486 * Call mii_mediachg() which will call back into dwc_miibus_statchg() 487 * to set up the remaining config registers based on current media. 488 */ 489 mii_mediachg(sc->mii_softc); 490 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 491 } 492 493 static void 494 dwc_init(void *if_softc) 495 { 496 struct dwc_softc *sc = if_softc; 497 498 DWC_LOCK(sc); 499 dwc_init_locked(sc); 500 DWC_UNLOCK(sc); 501 } 502 503 inline static uint32_t 504 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) 505 { 506 uint32_t nidx; 507 508 sc->rxdesc_ring[idx].addr = (uint32_t)paddr; 509 nidx = next_rxidx(sc, idx); 510 sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \ 511 (nidx * sizeof(struct dwc_hwdesc)); 512 sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; 513 514 wmb(); 515 sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; 516 wmb(); 517 518 return (nidx); 519 } 520 521 static int 522 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) 523 { 524 struct bus_dma_segment seg; 525 int error, nsegs; 526 527 m_adj(m, ETHER_ALIGN); 528 529 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 530 m, &seg, &nsegs, 0); 531 if (error != 0) { 532 return (error); 533 } 534 535 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 536 537 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 538 BUS_DMASYNC_PREREAD); 539 540 sc->rxbuf_map[idx].mbuf = m; 541 dwc_setup_rxdesc(sc, idx, seg.ds_addr); 542 543 return (0); 544 } 545 546 static struct mbuf * 547 dwc_alloc_mbufcl(struct dwc_softc *sc) 548 { 549 struct mbuf *m; 550 551 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 552 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 553 554 return (m); 555 } 556 557 static void 558 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 559 { 560 struct dwc_softc *sc; 561 struct mii_data *mii; 562 563 sc = ifp->if_softc; 564 mii = sc->mii_softc; 565 DWC_LOCK(sc); 566 mii_pollstat(mii); 567 ifmr->ifm_active = mii->mii_media_active; 568 ifmr->ifm_status = mii->mii_media_status; 569 DWC_UNLOCK(sc); 570 } 571 572 static int 573 dwc_media_change_locked(struct dwc_softc *sc) 574 { 575 576 return (mii_mediachg(sc->mii_softc)); 577 } 578 579 static int 580 dwc_media_change(struct ifnet * ifp) 581 { 582 struct dwc_softc *sc; 583 int error; 584 585 sc = ifp->if_softc; 586 587 DWC_LOCK(sc); 588 error = dwc_media_change_locked(sc); 589 DWC_UNLOCK(sc); 590 return (error); 591 } 592 593 static const uint8_t nibbletab[] = { 594 /* 0x0 0000 -> 0000 */ 0x0, 595 /* 0x1 0001 -> 1000 */ 0x8, 596 /* 0x2 0010 -> 0100 */ 0x4, 597 /* 0x3 0011 -> 1100 */ 0xc, 598 /* 0x4 0100 -> 0010 */ 0x2, 599 /* 0x5 0101 -> 1010 */ 0xa, 600 /* 0x6 0110 -> 0110 */ 0x6, 601 /* 0x7 0111 -> 1110 */ 0xe, 602 /* 0x8 1000 -> 0001 */ 0x1, 603 /* 0x9 1001 -> 1001 */ 0x9, 604 /* 0xa 1010 -> 0101 */ 0x5, 605 /* 0xb 1011 -> 1101 */ 0xd, 606 /* 0xc 1100 -> 0011 */ 0x3, 607 /* 0xd 1101 -> 1011 */ 0xb, 608 /* 0xe 1110 -> 0111 */ 0x7, 609 /* 0xf 1111 -> 1111 */ 0xf, }; 610 611 static uint8_t 612 bitreverse(uint8_t x) 613 { 614 615 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; 616 } 617 618 static void 619 dwc_setup_rxfilter(struct dwc_softc *sc) 620 { 621 struct ifmultiaddr *ifma; 622 struct ifnet *ifp; 623 uint8_t *eaddr; 624 uint32_t crc; 625 uint8_t val; 626 int hashbit; 627 int hashreg; 628 int ffval; 629 int reg; 630 int lo; 631 int hi; 632 633 DWC_ASSERT_LOCKED(sc); 634 635 ifp = sc->ifp; 636 637 /* 638 * Set the multicast (group) filter hash. 639 */ 640 if ((ifp->if_flags & IFF_ALLMULTI)) 641 ffval = (FRAME_FILTER_PM); 642 else { 643 ffval = (FRAME_FILTER_HMC); 644 if_maddr_rlock(ifp); 645 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 646 if (ifma->ifma_addr->sa_family != AF_LINK) 647 continue; 648 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 649 ifma->ifma_addr), ETHER_ADDR_LEN); 650 651 /* Take lower 8 bits and reverse it */ 652 val = bitreverse(~crc & 0xff); 653 hashreg = (val >> 5); 654 hashbit = (val & 31); 655 656 reg = READ4(sc, HASH_TABLE_REG(hashreg)); 657 reg |= (1 << hashbit); 658 WRITE4(sc, HASH_TABLE_REG(hashreg), reg); 659 } 660 if_maddr_runlock(ifp); 661 } 662 663 /* 664 * Set the individual address filter hash. 665 */ 666 if (ifp->if_flags & IFF_PROMISC) 667 ffval |= (FRAME_FILTER_PR); 668 669 /* 670 * Set the primary address. 671 */ 672 eaddr = IF_LLADDR(ifp); 673 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 674 (eaddr[3] << 24); 675 hi = eaddr[4] | (eaddr[5] << 8); 676 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); 677 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); 678 WRITE4(sc, MAC_FRAME_FILTER, ffval); 679 } 680 681 static int 682 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 683 { 684 struct dwc_softc *sc; 685 struct mii_data *mii; 686 struct ifreq *ifr; 687 int mask, error; 688 689 sc = ifp->if_softc; 690 ifr = (struct ifreq *)data; 691 692 error = 0; 693 switch (cmd) { 694 case SIOCSIFFLAGS: 695 DWC_LOCK(sc); 696 if (ifp->if_flags & IFF_UP) { 697 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 698 if ((ifp->if_flags ^ sc->if_flags) & 699 (IFF_PROMISC | IFF_ALLMULTI)) 700 dwc_setup_rxfilter(sc); 701 } else { 702 if (!sc->is_detaching) 703 dwc_init_locked(sc); 704 } 705 } else { 706 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 707 dwc_stop_locked(sc); 708 } 709 sc->if_flags = ifp->if_flags; 710 DWC_UNLOCK(sc); 711 break; 712 case SIOCADDMULTI: 713 case SIOCDELMULTI: 714 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 715 DWC_LOCK(sc); 716 dwc_setup_rxfilter(sc); 717 DWC_UNLOCK(sc); 718 } 719 break; 720 case SIOCSIFMEDIA: 721 case SIOCGIFMEDIA: 722 mii = sc->mii_softc; 723 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 724 break; 725 case SIOCSIFCAP: 726 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 727 if (mask & IFCAP_VLAN_MTU) { 728 /* No work to do except acknowledge the change took */ 729 ifp->if_capenable ^= IFCAP_VLAN_MTU; 730 } 731 break; 732 733 default: 734 error = ether_ioctl(ifp, cmd, data); 735 break; 736 } 737 738 return (error); 739 } 740 741 static void 742 dwc_txfinish_locked(struct dwc_softc *sc) 743 { 744 struct dwc_bufmap *bmap; 745 struct dwc_hwdesc *desc; 746 struct ifnet *ifp; 747 748 DWC_ASSERT_LOCKED(sc); 749 750 ifp = sc->ifp; 751 752 while (sc->tx_idx_tail != sc->tx_idx_head) { 753 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 754 if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) 755 break; 756 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 757 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 758 BUS_DMASYNC_POSTWRITE); 759 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 760 m_freem(bmap->mbuf); 761 bmap->mbuf = NULL; 762 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 763 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 764 } 765 766 /* If there are no buffers outstanding, muzzle the watchdog. */ 767 if (sc->tx_idx_tail == sc->tx_idx_head) { 768 sc->tx_watchdog_count = 0; 769 } 770 } 771 772 static void 773 dwc_rxfinish_locked(struct dwc_softc *sc) 774 { 775 struct ifnet *ifp; 776 struct mbuf *m0; 777 struct mbuf *m; 778 int error; 779 int rdes0; 780 int idx; 781 int len; 782 783 ifp = sc->ifp; 784 785 for (;;) { 786 idx = sc->rx_idx; 787 788 rdes0 = sc->rxdesc_ring[idx].tdes0; 789 if ((rdes0 & DDESC_RDES0_OWN) != 0) 790 break; 791 792 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 793 BUS_DMASYNC_POSTREAD); 794 bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); 795 796 len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; 797 if (len != 0) { 798 m = sc->rxbuf_map[idx].mbuf; 799 m->m_pkthdr.rcvif = ifp; 800 m->m_pkthdr.len = len; 801 m->m_len = len; 802 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 803 804 DWC_UNLOCK(sc); 805 (*ifp->if_input)(ifp, m); 806 DWC_LOCK(sc); 807 } else { 808 /* XXX Zero-length packet ? */ 809 } 810 811 if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) { 812 if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { 813 /* 814 * XXX Now what? 815 * We've got a hole in the rx ring. 816 */ 817 } 818 } else 819 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 820 821 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 822 } 823 } 824 825 static void 826 dwc_intr(void *arg) 827 { 828 struct dwc_softc *sc; 829 uint32_t reg; 830 831 sc = arg; 832 833 DWC_LOCK(sc); 834 835 reg = READ4(sc, INTERRUPT_STATUS); 836 if (reg) { 837 mii_mediachg(sc->mii_softc); 838 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); 839 } 840 841 reg = READ4(sc, DMA_STATUS); 842 if (reg & DMA_STATUS_NIS) { 843 if (reg & DMA_STATUS_RI) 844 dwc_rxfinish_locked(sc); 845 846 if (reg & DMA_STATUS_TI) 847 dwc_txfinish_locked(sc); 848 } 849 850 if (reg & DMA_STATUS_AIS) { 851 if (reg & DMA_STATUS_FBI) { 852 /* Fatal bus error */ 853 device_printf(sc->dev, 854 "Ethernet DMA error, restarting controller.\n"); 855 dwc_stop_locked(sc); 856 dwc_init_locked(sc); 857 } 858 } 859 860 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 861 DWC_UNLOCK(sc); 862 } 863 864 static int 865 setup_dma(struct dwc_softc *sc) 866 { 867 struct mbuf *m; 868 int error; 869 int nidx; 870 int idx; 871 872 /* 873 * Set up TX descriptor ring, descriptors, and dma maps. 874 */ 875 error = bus_dma_tag_create( 876 bus_get_dma_tag(sc->dev), /* Parent tag. */ 877 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 878 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 879 BUS_SPACE_MAXADDR, /* highaddr */ 880 NULL, NULL, /* filter, filterarg */ 881 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 882 TX_DESC_SIZE, /* maxsegsize */ 883 0, /* flags */ 884 NULL, NULL, /* lockfunc, lockarg */ 885 &sc->txdesc_tag); 886 if (error != 0) { 887 device_printf(sc->dev, 888 "could not create TX ring DMA tag.\n"); 889 goto out; 890 } 891 892 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 893 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 894 &sc->txdesc_map); 895 if (error != 0) { 896 device_printf(sc->dev, 897 "could not allocate TX descriptor ring.\n"); 898 goto out; 899 } 900 901 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, 902 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, 903 &sc->txdesc_ring_paddr, 0); 904 if (error != 0) { 905 device_printf(sc->dev, 906 "could not load TX descriptor ring map.\n"); 907 goto out; 908 } 909 910 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 911 sc->txdesc_ring[idx].tdes0 = DDESC_TDES0_TXCHAIN; 912 sc->txdesc_ring[idx].tdes1 = 0; 913 nidx = next_txidx(sc, idx); 914 sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + \ 915 (nidx * sizeof(struct dwc_hwdesc)); 916 } 917 918 error = bus_dma_tag_create( 919 bus_get_dma_tag(sc->dev), /* Parent tag. */ 920 1, 0, /* alignment, boundary */ 921 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 922 BUS_SPACE_MAXADDR, /* highaddr */ 923 NULL, NULL, /* filter, filterarg */ 924 MCLBYTES, 1, /* maxsize, nsegments */ 925 MCLBYTES, /* maxsegsize */ 926 0, /* flags */ 927 NULL, NULL, /* lockfunc, lockarg */ 928 &sc->txbuf_tag); 929 if (error != 0) { 930 device_printf(sc->dev, 931 "could not create TX ring DMA tag.\n"); 932 goto out; 933 } 934 935 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 936 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, 937 &sc->txbuf_map[idx].map); 938 if (error != 0) { 939 device_printf(sc->dev, 940 "could not create TX buffer DMA map.\n"); 941 goto out; 942 } 943 dwc_setup_txdesc(sc, idx, 0, 0); 944 } 945 946 /* 947 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 948 */ 949 error = bus_dma_tag_create( 950 bus_get_dma_tag(sc->dev), /* Parent tag. */ 951 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 952 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 953 BUS_SPACE_MAXADDR, /* highaddr */ 954 NULL, NULL, /* filter, filterarg */ 955 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 956 RX_DESC_SIZE, /* maxsegsize */ 957 0, /* flags */ 958 NULL, NULL, /* lockfunc, lockarg */ 959 &sc->rxdesc_tag); 960 if (error != 0) { 961 device_printf(sc->dev, 962 "could not create RX ring DMA tag.\n"); 963 goto out; 964 } 965 966 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 967 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 968 &sc->rxdesc_map); 969 if (error != 0) { 970 device_printf(sc->dev, 971 "could not allocate RX descriptor ring.\n"); 972 goto out; 973 } 974 975 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, 976 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, 977 &sc->rxdesc_ring_paddr, 0); 978 if (error != 0) { 979 device_printf(sc->dev, 980 "could not load RX descriptor ring map.\n"); 981 goto out; 982 } 983 984 error = bus_dma_tag_create( 985 bus_get_dma_tag(sc->dev), /* Parent tag. */ 986 1, 0, /* alignment, boundary */ 987 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 988 BUS_SPACE_MAXADDR, /* highaddr */ 989 NULL, NULL, /* filter, filterarg */ 990 MCLBYTES, 1, /* maxsize, nsegments */ 991 MCLBYTES, /* maxsegsize */ 992 0, /* flags */ 993 NULL, NULL, /* lockfunc, lockarg */ 994 &sc->rxbuf_tag); 995 if (error != 0) { 996 device_printf(sc->dev, 997 "could not create RX buf DMA tag.\n"); 998 goto out; 999 } 1000 1001 for (idx = 0; idx < RX_DESC_COUNT; idx++) { 1002 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, 1003 &sc->rxbuf_map[idx].map); 1004 if (error != 0) { 1005 device_printf(sc->dev, 1006 "could not create RX buffer DMA map.\n"); 1007 goto out; 1008 } 1009 if ((m = dwc_alloc_mbufcl(sc)) == NULL) { 1010 device_printf(sc->dev, "Could not alloc mbuf\n"); 1011 error = ENOMEM; 1012 goto out; 1013 } 1014 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { 1015 device_printf(sc->dev, 1016 "could not create new RX buffer.\n"); 1017 goto out; 1018 } 1019 } 1020 1021 out: 1022 if (error != 0) 1023 return (ENXIO); 1024 1025 return (0); 1026 } 1027 1028 static int 1029 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) 1030 { 1031 int rnd; 1032 int lo; 1033 int hi; 1034 1035 /* 1036 * Try to recover a MAC address from the running hardware. If there's 1037 * something non-zero there, assume the bootloader did the right thing 1038 * and just use it. 1039 * 1040 * Otherwise, set the address to a convenient locally assigned address, 1041 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 1042 * assigned bit set, and the broadcast/multicast bit clear. 1043 */ 1044 lo = READ4(sc, MAC_ADDRESS_LOW(0)); 1045 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; 1046 if ((lo != 0xffffffff) || (hi != 0xffff)) { 1047 hwaddr[0] = (lo >> 0) & 0xff; 1048 hwaddr[1] = (lo >> 8) & 0xff; 1049 hwaddr[2] = (lo >> 16) & 0xff; 1050 hwaddr[3] = (lo >> 24) & 0xff; 1051 hwaddr[4] = (hi >> 0) & 0xff; 1052 hwaddr[5] = (hi >> 8) & 0xff; 1053 } else { 1054 rnd = arc4random() & 0x00ffffff; 1055 hwaddr[0] = 'b'; 1056 hwaddr[1] = 's'; 1057 hwaddr[2] = 'd'; 1058 hwaddr[3] = rnd >> 16; 1059 hwaddr[4] = rnd >> 8; 1060 hwaddr[5] = rnd >> 0; 1061 } 1062 1063 return (0); 1064 } 1065 1066 static int 1067 dwc_probe(device_t dev) 1068 { 1069 1070 if (!ofw_bus_status_okay(dev)) 1071 return (ENXIO); 1072 1073 if (!ofw_bus_is_compatible(dev, "snps,dwmac")) 1074 return (ENXIO); 1075 1076 device_set_desc(dev, "Gigabit Ethernet Controller"); 1077 return (BUS_PROBE_DEFAULT); 1078 } 1079 1080 static int 1081 dwc_attach(device_t dev) 1082 { 1083 uint8_t macaddr[ETHER_ADDR_LEN]; 1084 struct dwc_softc *sc; 1085 struct ifnet *ifp; 1086 int error; 1087 int reg; 1088 int i; 1089 1090 sc = device_get_softc(dev); 1091 sc->dev = dev; 1092 sc->mii_clk = MII_CLK_VAL; 1093 sc->rx_idx = 0; 1094 1095 sc->txcount = TX_DESC_COUNT; 1096 1097 if (bus_alloc_resources(dev, dwc_spec, sc->res)) { 1098 device_printf(dev, "could not allocate resources\n"); 1099 return (ENXIO); 1100 } 1101 1102 /* Memory interface */ 1103 sc->bst = rman_get_bustag(sc->res[0]); 1104 sc->bsh = rman_get_bushandle(sc->res[0]); 1105 1106 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), 1107 MTX_NETWORK_LOCK, MTX_DEF); 1108 1109 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); 1110 1111 /* Setup interrupt handler. */ 1112 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 1113 NULL, dwc_intr, sc, &sc->intr_cookie); 1114 if (error != 0) { 1115 device_printf(dev, "could not setup interrupt handler.\n"); 1116 return (ENXIO); 1117 } 1118 1119 /* Read MAC before reset */ 1120 if (dwc_get_hwaddr(sc, macaddr)) { 1121 device_printf(sc->dev, "can't get mac\n"); 1122 return (ENXIO); 1123 } 1124 1125 /* Reset */ 1126 reg = READ4(sc, BUS_MODE); 1127 reg |= (BUS_MODE_SWR); 1128 WRITE4(sc, BUS_MODE, reg); 1129 1130 for (i = 0; i < 100; i++) { 1131 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 1132 break; 1133 DELAY(10); 1134 } 1135 if (i == 0) { 1136 device_printf(sc->dev, "Can't reset DWC.\n"); 1137 return (ENXIO); 1138 } 1139 1140 reg = READ4(sc, BUS_MODE); 1141 reg |= (BUS_MODE_EIGHTXPBL); 1142 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); 1143 WRITE4(sc, BUS_MODE, reg); 1144 1145 /* 1146 * DMA must be stop while changing descriptor list addresses. 1147 */ 1148 reg = READ4(sc, OPERATION_MODE); 1149 reg &= ~(MODE_ST | MODE_SR); 1150 WRITE4(sc, OPERATION_MODE, reg); 1151 1152 if (setup_dma(sc)) 1153 return (ENXIO); 1154 1155 /* Setup addresses */ 1156 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 1157 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 1158 1159 /* Set up the ethernet interface. */ 1160 sc->ifp = ifp = if_alloc(IFT_ETHER); 1161 1162 ifp->if_softc = sc; 1163 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1164 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1165 ifp->if_capabilities = IFCAP_VLAN_MTU; 1166 ifp->if_capenable = ifp->if_capabilities; 1167 ifp->if_start = dwc_txstart; 1168 ifp->if_ioctl = dwc_ioctl; 1169 ifp->if_init = dwc_init; 1170 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1171 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1172 IFQ_SET_READY(&ifp->if_snd); 1173 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1174 1175 /* Attach the mii driver. */ 1176 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, 1177 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 1178 MII_OFFSET_ANY, 0); 1179 1180 if (error != 0) { 1181 device_printf(dev, "PHY attach failed\n"); 1182 return (ENXIO); 1183 } 1184 sc->mii_softc = device_get_softc(sc->miibus); 1185 1186 /* All ready to run, attach the ethernet interface. */ 1187 ether_ifattach(ifp, macaddr); 1188 sc->is_attached = true; 1189 1190 return (0); 1191 } 1192 1193 static int 1194 dwc_miibus_read_reg(device_t dev, int phy, int reg) 1195 { 1196 struct dwc_softc *sc; 1197 uint16_t mii; 1198 size_t cnt; 1199 int rv = 0; 1200 1201 sc = device_get_softc(dev); 1202 1203 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1204 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1205 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1206 | GMII_ADDRESS_GB; /* Busy flag */ 1207 1208 WRITE4(sc, GMII_ADDRESS, mii); 1209 1210 for (cnt = 0; cnt < 1000; cnt++) { 1211 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1212 rv = READ4(sc, GMII_DATA); 1213 break; 1214 } 1215 DELAY(10); 1216 } 1217 1218 return rv; 1219 } 1220 1221 static int 1222 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) 1223 { 1224 struct dwc_softc *sc; 1225 uint16_t mii; 1226 size_t cnt; 1227 1228 sc = device_get_softc(dev); 1229 1230 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1231 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1232 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1233 | GMII_ADDRESS_GB | GMII_ADDRESS_GW; 1234 1235 WRITE4(sc, GMII_DATA, val); 1236 WRITE4(sc, GMII_ADDRESS, mii); 1237 1238 for (cnt = 0; cnt < 1000; cnt++) { 1239 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1240 break; 1241 } 1242 DELAY(10); 1243 } 1244 1245 return (0); 1246 } 1247 1248 static void 1249 dwc_miibus_statchg(device_t dev) 1250 { 1251 struct dwc_softc *sc; 1252 struct mii_data *mii; 1253 int reg; 1254 1255 /* 1256 * Called by the MII bus driver when the PHY establishes 1257 * link to set the MAC interface registers. 1258 */ 1259 1260 sc = device_get_softc(dev); 1261 1262 DWC_ASSERT_LOCKED(sc); 1263 1264 mii = sc->mii_softc; 1265 1266 if (mii->mii_media_status & IFM_ACTIVE) 1267 sc->link_is_up = true; 1268 else 1269 sc->link_is_up = false; 1270 1271 reg = READ4(sc, MAC_CONFIGURATION); 1272 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1273 case IFM_1000_T: 1274 case IFM_1000_SX: 1275 reg &= ~(CONF_FES | CONF_PS); 1276 break; 1277 case IFM_100_TX: 1278 reg |= (CONF_FES | CONF_PS); 1279 break; 1280 case IFM_10_T: 1281 reg &= ~(CONF_FES); 1282 reg |= (CONF_PS); 1283 break; 1284 case IFM_NONE: 1285 sc->link_is_up = false; 1286 return; 1287 default: 1288 sc->link_is_up = false; 1289 device_printf(dev, "Unsupported media %u\n", 1290 IFM_SUBTYPE(mii->mii_media_active)); 1291 return; 1292 } 1293 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1294 reg |= (CONF_DM); 1295 else 1296 reg &= ~(CONF_DM); 1297 WRITE4(sc, MAC_CONFIGURATION, reg); 1298 } 1299 1300 static device_method_t dwc_methods[] = { 1301 DEVMETHOD(device_probe, dwc_probe), 1302 DEVMETHOD(device_attach, dwc_attach), 1303 1304 /* MII Interface */ 1305 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), 1306 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), 1307 DEVMETHOD(miibus_statchg, dwc_miibus_statchg), 1308 1309 { 0, 0 } 1310 }; 1311 1312 static driver_t dwc_driver = { 1313 "dwc", 1314 dwc_methods, 1315 sizeof(struct dwc_softc), 1316 }; 1317 1318 static devclass_t dwc_devclass; 1319 1320 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); 1321 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); 1322 1323 MODULE_DEPEND(dwc, ether, 1, 1, 1); 1324 MODULE_DEPEND(dwc, miibus, 1, 1, 1); 1325