1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Ethernet media access controller (EMAC) 33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 * 35 * EMAC is an instance of the Synopsys DesignWare 3504-0 36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/gpio.h> 46 #include <sys/kernel.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/module.h> 51 #include <sys/mutex.h> 52 #include <sys/rman.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_var.h> 63 64 #include <machine/bus.h> 65 66 #include <dev/dwc/if_dwc.h> 67 #include <dev/dwc/if_dwcvar.h> 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 #include <dev/ofw/ofw_bus.h> 71 #include <dev/ofw/ofw_bus_subr.h> 72 73 #include "if_dwc_if.h" 74 #include "gpio_if.h" 75 #include "miibus_if.h" 76 77 #define READ4(_sc, _reg) \ 78 bus_read_4((_sc)->res[0], _reg) 79 #define WRITE4(_sc, _reg, _val) \ 80 bus_write_4((_sc)->res[0], _reg, _val) 81 82 #define MAC_RESET_TIMEOUT 100 83 #define WATCHDOG_TIMEOUT_SECS 5 84 #define STATS_HARVEST_INTERVAL 2 85 86 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) 87 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 88 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 89 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 90 91 #define DDESC_TDES0_OWN (1U << 31) 92 #define DDESC_TDES0_TXINT (1U << 30) 93 #define DDESC_TDES0_TXLAST (1U << 29) 94 #define DDESC_TDES0_TXFIRST (1U << 28) 95 #define DDESC_TDES0_TXCRCDIS (1U << 27) 96 #define DDESC_TDES0_TXRINGEND (1U << 21) 97 #define DDESC_TDES0_TXCHAIN (1U << 20) 98 99 #define DDESC_RDES0_OWN (1U << 31) 100 #define DDESC_RDES0_FL_MASK 0x3fff 101 #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ 102 #define DDESC_RDES1_CHAINED (1U << 14) 103 104 /* Alt descriptor bits. */ 105 #define DDESC_CNTL_TXINT (1U << 31) 106 #define DDESC_CNTL_TXLAST (1U << 30) 107 #define DDESC_CNTL_TXFIRST (1U << 29) 108 #define DDESC_CNTL_TXCRCDIS (1U << 26) 109 #define DDESC_CNTL_TXRINGEND (1U << 25) 110 #define DDESC_CNTL_TXCHAIN (1U << 24) 111 112 #define DDESC_CNTL_CHAINED (1U << 24) 113 114 /* 115 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 116 * layout, but the bits in the fields have different meanings. 117 */ 118 struct dwc_hwdesc 119 { 120 uint32_t tdes0; /* status for alt layout */ 121 uint32_t tdes1; /* cntl for alt layout */ 122 uint32_t addr; /* pointer to buffer data */ 123 uint32_t addr_next; /* link to next descriptor */ 124 }; 125 126 /* 127 * The hardware imposes alignment restrictions on various objects involved in 128 * DMA transfers. These values are expressed in bytes (not bits). 129 */ 130 #define DWC_DESC_RING_ALIGN 2048 131 132 static struct resource_spec dwc_spec[] = { 133 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 134 { SYS_RES_IRQ, 0, RF_ACTIVE }, 135 { -1, 0 } 136 }; 137 138 static void dwc_txfinish_locked(struct dwc_softc *sc); 139 static void dwc_rxfinish_locked(struct dwc_softc *sc); 140 static void dwc_stop_locked(struct dwc_softc *sc); 141 static void dwc_setup_rxfilter(struct dwc_softc *sc); 142 143 static inline uint32_t 144 next_rxidx(struct dwc_softc *sc, uint32_t curidx) 145 { 146 147 return ((curidx + 1) % RX_DESC_COUNT); 148 } 149 150 static inline uint32_t 151 next_txidx(struct dwc_softc *sc, uint32_t curidx) 152 { 153 154 return ((curidx + 1) % TX_DESC_COUNT); 155 } 156 157 static void 158 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 159 { 160 161 if (error != 0) 162 return; 163 *(bus_addr_t *)arg = segs[0].ds_addr; 164 } 165 166 inline static uint32_t 167 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, 168 uint32_t len) 169 { 170 uint32_t flags; 171 uint32_t nidx; 172 173 nidx = next_txidx(sc, idx); 174 175 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 176 if (paddr == 0 || len == 0) { 177 flags = 0; 178 --sc->txcount; 179 } else { 180 if (sc->mactype == DWC_GMAC_ALT_DESC) 181 flags = DDESC_CNTL_TXCHAIN | DDESC_CNTL_TXFIRST 182 | DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT; 183 else 184 flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST 185 | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT; 186 ++sc->txcount; 187 } 188 189 sc->txdesc_ring[idx].addr = (uint32_t)(paddr); 190 if (sc->mactype == DWC_GMAC_ALT_DESC) { 191 sc->txdesc_ring[idx].tdes0 = 0; 192 sc->txdesc_ring[idx].tdes1 = flags | len; 193 } else { 194 sc->txdesc_ring[idx].tdes0 = flags; 195 sc->txdesc_ring[idx].tdes1 = len; 196 } 197 198 if (paddr && len) { 199 wmb(); 200 sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN; 201 wmb(); 202 } 203 204 return (nidx); 205 } 206 207 static int 208 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) 209 { 210 struct bus_dma_segment seg; 211 int error, nsegs; 212 struct mbuf * m; 213 214 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 215 return (ENOMEM); 216 *mp = m; 217 218 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 219 m, &seg, &nsegs, 0); 220 if (error != 0) { 221 return (ENOMEM); 222 } 223 224 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 225 226 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 227 BUS_DMASYNC_PREWRITE); 228 229 sc->txbuf_map[idx].mbuf = m; 230 231 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 232 233 return (0); 234 } 235 236 static void 237 dwc_txstart_locked(struct dwc_softc *sc) 238 { 239 struct ifnet *ifp; 240 struct mbuf *m; 241 int enqueued; 242 243 DWC_ASSERT_LOCKED(sc); 244 245 if (!sc->link_is_up) 246 return; 247 248 ifp = sc->ifp; 249 250 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 251 return; 252 } 253 254 enqueued = 0; 255 256 for (;;) { 257 if (sc->txcount == (TX_DESC_COUNT-1)) { 258 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 259 break; 260 } 261 262 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 263 if (m == NULL) 264 break; 265 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 266 IFQ_DRV_PREPEND(&ifp->if_snd, m); 267 break; 268 } 269 BPF_MTAP(ifp, m); 270 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 271 ++enqueued; 272 } 273 274 if (enqueued != 0) { 275 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 276 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 277 } 278 } 279 280 static void 281 dwc_txstart(struct ifnet *ifp) 282 { 283 struct dwc_softc *sc = ifp->if_softc; 284 285 DWC_LOCK(sc); 286 dwc_txstart_locked(sc); 287 DWC_UNLOCK(sc); 288 } 289 290 static void 291 dwc_stop_locked(struct dwc_softc *sc) 292 { 293 struct ifnet *ifp; 294 uint32_t reg; 295 296 DWC_ASSERT_LOCKED(sc); 297 298 ifp = sc->ifp; 299 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 300 sc->tx_watchdog_count = 0; 301 sc->stats_harvest_count = 0; 302 303 callout_stop(&sc->dwc_callout); 304 305 /* Stop DMA TX */ 306 reg = READ4(sc, OPERATION_MODE); 307 reg &= ~(MODE_ST); 308 WRITE4(sc, OPERATION_MODE, reg); 309 310 /* Flush TX */ 311 reg = READ4(sc, OPERATION_MODE); 312 reg |= (MODE_FTF); 313 WRITE4(sc, OPERATION_MODE, reg); 314 315 /* Stop transmitters */ 316 reg = READ4(sc, MAC_CONFIGURATION); 317 reg &= ~(CONF_TE | CONF_RE); 318 WRITE4(sc, MAC_CONFIGURATION, reg); 319 320 /* Stop DMA RX */ 321 reg = READ4(sc, OPERATION_MODE); 322 reg &= ~(MODE_SR); 323 WRITE4(sc, OPERATION_MODE, reg); 324 } 325 326 static void dwc_clear_stats(struct dwc_softc *sc) 327 { 328 uint32_t reg; 329 330 reg = READ4(sc, MMC_CONTROL); 331 reg |= (MMC_CONTROL_CNTRST); 332 WRITE4(sc, MMC_CONTROL, reg); 333 } 334 335 static void 336 dwc_harvest_stats(struct dwc_softc *sc) 337 { 338 struct ifnet *ifp; 339 340 /* We don't need to harvest too often. */ 341 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 342 return; 343 344 sc->stats_harvest_count = 0; 345 ifp = sc->ifp; 346 347 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); 348 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); 349 if_inc_counter(ifp, IFCOUNTER_IERRORS, 350 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + 351 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + 352 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + 353 READ4(sc, RXLENGTHERROR)); 354 355 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); 356 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); 357 if_inc_counter(ifp, IFCOUNTER_OERRORS, 358 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + 359 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); 360 361 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 362 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); 363 364 dwc_clear_stats(sc); 365 } 366 367 static void 368 dwc_tick(void *arg) 369 { 370 struct dwc_softc *sc; 371 struct ifnet *ifp; 372 int link_was_up; 373 374 sc = arg; 375 376 DWC_ASSERT_LOCKED(sc); 377 378 ifp = sc->ifp; 379 380 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 381 return; 382 383 /* 384 * Typical tx watchdog. If this fires it indicates that we enqueued 385 * packets for output and never got a txdone interrupt for them. Maybe 386 * it's a missed interrupt somehow, just pretend we got one. 387 */ 388 if (sc->tx_watchdog_count > 0) { 389 if (--sc->tx_watchdog_count == 0) { 390 dwc_txfinish_locked(sc); 391 } 392 } 393 394 /* Gather stats from hardware counters. */ 395 dwc_harvest_stats(sc); 396 397 /* Check the media status. */ 398 link_was_up = sc->link_is_up; 399 mii_tick(sc->mii_softc); 400 if (sc->link_is_up && !link_was_up) 401 dwc_txstart_locked(sc); 402 403 /* Schedule another check one second from now. */ 404 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 405 } 406 407 static void 408 dwc_init_locked(struct dwc_softc *sc) 409 { 410 struct ifnet *ifp = sc->ifp; 411 uint32_t reg; 412 413 DWC_ASSERT_LOCKED(sc); 414 415 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 416 return; 417 418 ifp->if_drv_flags |= IFF_DRV_RUNNING; 419 420 dwc_setup_rxfilter(sc); 421 422 /* Initializa DMA and enable transmitters */ 423 reg = READ4(sc, OPERATION_MODE); 424 reg |= (MODE_TSF | MODE_OSF | MODE_FUF); 425 reg &= ~(MODE_RSF); 426 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); 427 WRITE4(sc, OPERATION_MODE, reg); 428 429 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 430 431 /* Start DMA */ 432 reg = READ4(sc, OPERATION_MODE); 433 reg |= (MODE_ST | MODE_SR); 434 WRITE4(sc, OPERATION_MODE, reg); 435 436 /* Enable transmitters */ 437 reg = READ4(sc, MAC_CONFIGURATION); 438 reg |= (CONF_JD | CONF_ACS | CONF_BE); 439 reg |= (CONF_TE | CONF_RE); 440 WRITE4(sc, MAC_CONFIGURATION, reg); 441 442 /* 443 * Call mii_mediachg() which will call back into dwc_miibus_statchg() 444 * to set up the remaining config registers based on current media. 445 */ 446 mii_mediachg(sc->mii_softc); 447 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 448 } 449 450 static void 451 dwc_init(void *if_softc) 452 { 453 struct dwc_softc *sc = if_softc; 454 455 DWC_LOCK(sc); 456 dwc_init_locked(sc); 457 DWC_UNLOCK(sc); 458 } 459 460 inline static uint32_t 461 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) 462 { 463 uint32_t nidx; 464 465 sc->rxdesc_ring[idx].addr = (uint32_t)paddr; 466 nidx = next_rxidx(sc, idx); 467 sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \ 468 (nidx * sizeof(struct dwc_hwdesc)); 469 if (sc->mactype == DWC_GMAC_ALT_DESC) 470 sc->rxdesc_ring[idx].tdes1 = DDESC_CNTL_CHAINED | RX_MAX_PACKET; 471 else 472 sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; 473 474 wmb(); 475 sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; 476 wmb(); 477 478 return (nidx); 479 } 480 481 static int 482 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) 483 { 484 struct bus_dma_segment seg; 485 int error, nsegs; 486 487 m_adj(m, ETHER_ALIGN); 488 489 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 490 m, &seg, &nsegs, 0); 491 if (error != 0) { 492 return (error); 493 } 494 495 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 496 497 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 498 BUS_DMASYNC_PREREAD); 499 500 sc->rxbuf_map[idx].mbuf = m; 501 dwc_setup_rxdesc(sc, idx, seg.ds_addr); 502 503 return (0); 504 } 505 506 static struct mbuf * 507 dwc_alloc_mbufcl(struct dwc_softc *sc) 508 { 509 struct mbuf *m; 510 511 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 512 if (m != NULL) 513 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 514 515 return (m); 516 } 517 518 static void 519 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 520 { 521 struct dwc_softc *sc; 522 struct mii_data *mii; 523 524 sc = ifp->if_softc; 525 mii = sc->mii_softc; 526 DWC_LOCK(sc); 527 mii_pollstat(mii); 528 ifmr->ifm_active = mii->mii_media_active; 529 ifmr->ifm_status = mii->mii_media_status; 530 DWC_UNLOCK(sc); 531 } 532 533 static int 534 dwc_media_change_locked(struct dwc_softc *sc) 535 { 536 537 return (mii_mediachg(sc->mii_softc)); 538 } 539 540 static int 541 dwc_media_change(struct ifnet * ifp) 542 { 543 struct dwc_softc *sc; 544 int error; 545 546 sc = ifp->if_softc; 547 548 DWC_LOCK(sc); 549 error = dwc_media_change_locked(sc); 550 DWC_UNLOCK(sc); 551 return (error); 552 } 553 554 static const uint8_t nibbletab[] = { 555 /* 0x0 0000 -> 0000 */ 0x0, 556 /* 0x1 0001 -> 1000 */ 0x8, 557 /* 0x2 0010 -> 0100 */ 0x4, 558 /* 0x3 0011 -> 1100 */ 0xc, 559 /* 0x4 0100 -> 0010 */ 0x2, 560 /* 0x5 0101 -> 1010 */ 0xa, 561 /* 0x6 0110 -> 0110 */ 0x6, 562 /* 0x7 0111 -> 1110 */ 0xe, 563 /* 0x8 1000 -> 0001 */ 0x1, 564 /* 0x9 1001 -> 1001 */ 0x9, 565 /* 0xa 1010 -> 0101 */ 0x5, 566 /* 0xb 1011 -> 1101 */ 0xd, 567 /* 0xc 1100 -> 0011 */ 0x3, 568 /* 0xd 1101 -> 1011 */ 0xb, 569 /* 0xe 1110 -> 0111 */ 0x7, 570 /* 0xf 1111 -> 1111 */ 0xf, }; 571 572 static uint8_t 573 bitreverse(uint8_t x) 574 { 575 576 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; 577 } 578 579 static void 580 dwc_setup_rxfilter(struct dwc_softc *sc) 581 { 582 struct ifmultiaddr *ifma; 583 struct ifnet *ifp; 584 uint8_t *eaddr, val; 585 uint32_t crc, ffval, hashbit, hashreg, hi, lo, reg; 586 587 DWC_ASSERT_LOCKED(sc); 588 589 ifp = sc->ifp; 590 591 /* 592 * Set the multicast (group) filter hash. 593 */ 594 if ((ifp->if_flags & IFF_ALLMULTI)) 595 ffval = (FRAME_FILTER_PM); 596 else { 597 ffval = (FRAME_FILTER_HMC); 598 if_maddr_rlock(ifp); 599 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 600 if (ifma->ifma_addr->sa_family != AF_LINK) 601 continue; 602 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 603 ifma->ifma_addr), ETHER_ADDR_LEN); 604 605 /* Take lower 8 bits and reverse it */ 606 val = bitreverse(~crc & 0xff); 607 hashreg = (val >> 5); 608 hashbit = (val & 31); 609 610 reg = READ4(sc, HASH_TABLE_REG(hashreg)); 611 reg |= (1 << hashbit); 612 WRITE4(sc, HASH_TABLE_REG(hashreg), reg); 613 } 614 if_maddr_runlock(ifp); 615 } 616 617 /* 618 * Set the individual address filter hash. 619 */ 620 if (ifp->if_flags & IFF_PROMISC) 621 ffval |= (FRAME_FILTER_PR); 622 623 /* 624 * Set the primary address. 625 */ 626 eaddr = IF_LLADDR(ifp); 627 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 628 (eaddr[3] << 24); 629 hi = eaddr[4] | (eaddr[5] << 8); 630 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); 631 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); 632 WRITE4(sc, MAC_FRAME_FILTER, ffval); 633 } 634 635 static int 636 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 637 { 638 struct dwc_softc *sc; 639 struct mii_data *mii; 640 struct ifreq *ifr; 641 int mask, error; 642 643 sc = ifp->if_softc; 644 ifr = (struct ifreq *)data; 645 646 error = 0; 647 switch (cmd) { 648 case SIOCSIFFLAGS: 649 DWC_LOCK(sc); 650 if (ifp->if_flags & IFF_UP) { 651 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 652 if ((ifp->if_flags ^ sc->if_flags) & 653 (IFF_PROMISC | IFF_ALLMULTI)) 654 dwc_setup_rxfilter(sc); 655 } else { 656 if (!sc->is_detaching) 657 dwc_init_locked(sc); 658 } 659 } else { 660 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 661 dwc_stop_locked(sc); 662 } 663 sc->if_flags = ifp->if_flags; 664 DWC_UNLOCK(sc); 665 break; 666 case SIOCADDMULTI: 667 case SIOCDELMULTI: 668 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 669 DWC_LOCK(sc); 670 dwc_setup_rxfilter(sc); 671 DWC_UNLOCK(sc); 672 } 673 break; 674 case SIOCSIFMEDIA: 675 case SIOCGIFMEDIA: 676 mii = sc->mii_softc; 677 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 678 break; 679 case SIOCSIFCAP: 680 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 681 if (mask & IFCAP_VLAN_MTU) { 682 /* No work to do except acknowledge the change took */ 683 ifp->if_capenable ^= IFCAP_VLAN_MTU; 684 } 685 break; 686 687 default: 688 error = ether_ioctl(ifp, cmd, data); 689 break; 690 } 691 692 return (error); 693 } 694 695 static void 696 dwc_txfinish_locked(struct dwc_softc *sc) 697 { 698 struct dwc_bufmap *bmap; 699 struct dwc_hwdesc *desc; 700 struct ifnet *ifp; 701 702 DWC_ASSERT_LOCKED(sc); 703 704 ifp = sc->ifp; 705 while (sc->tx_idx_tail != sc->tx_idx_head) { 706 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 707 if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) 708 break; 709 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 710 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 711 BUS_DMASYNC_POSTWRITE); 712 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 713 m_freem(bmap->mbuf); 714 bmap->mbuf = NULL; 715 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 716 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 717 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 718 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 719 } 720 721 /* If there are no buffers outstanding, muzzle the watchdog. */ 722 if (sc->tx_idx_tail == sc->tx_idx_head) { 723 sc->tx_watchdog_count = 0; 724 } 725 } 726 727 static void 728 dwc_rxfinish_locked(struct dwc_softc *sc) 729 { 730 struct ifnet *ifp; 731 struct mbuf *m0; 732 struct mbuf *m; 733 int error, idx, len; 734 uint32_t rdes0; 735 736 ifp = sc->ifp; 737 738 for (;;) { 739 idx = sc->rx_idx; 740 741 rdes0 = sc->rxdesc_ring[idx].tdes0; 742 if ((rdes0 & DDESC_RDES0_OWN) != 0) 743 break; 744 745 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 746 BUS_DMASYNC_POSTREAD); 747 bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); 748 749 len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; 750 if (len != 0) { 751 m = sc->rxbuf_map[idx].mbuf; 752 m->m_pkthdr.rcvif = ifp; 753 m->m_pkthdr.len = len; 754 m->m_len = len; 755 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 756 757 DWC_UNLOCK(sc); 758 (*ifp->if_input)(ifp, m); 759 DWC_LOCK(sc); 760 } else { 761 /* XXX Zero-length packet ? */ 762 } 763 764 if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) { 765 if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { 766 /* 767 * XXX Now what? 768 * We've got a hole in the rx ring. 769 */ 770 } 771 } else 772 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 773 774 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 775 } 776 } 777 778 static void 779 dwc_intr(void *arg) 780 { 781 struct dwc_softc *sc; 782 uint32_t reg; 783 784 sc = arg; 785 786 DWC_LOCK(sc); 787 788 reg = READ4(sc, INTERRUPT_STATUS); 789 if (reg) 790 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); 791 792 reg = READ4(sc, DMA_STATUS); 793 if (reg & DMA_STATUS_NIS) { 794 if (reg & DMA_STATUS_RI) 795 dwc_rxfinish_locked(sc); 796 797 if (reg & DMA_STATUS_TI) { 798 dwc_txfinish_locked(sc); 799 dwc_txstart_locked(sc); 800 } 801 } 802 803 if (reg & DMA_STATUS_AIS) { 804 if (reg & DMA_STATUS_FBI) { 805 /* Fatal bus error */ 806 device_printf(sc->dev, 807 "Ethernet DMA error, restarting controller.\n"); 808 dwc_stop_locked(sc); 809 dwc_init_locked(sc); 810 } 811 } 812 813 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 814 DWC_UNLOCK(sc); 815 } 816 817 static int 818 setup_dma(struct dwc_softc *sc) 819 { 820 struct mbuf *m; 821 int error; 822 int nidx; 823 int idx; 824 825 /* 826 * Set up TX descriptor ring, descriptors, and dma maps. 827 */ 828 error = bus_dma_tag_create( 829 bus_get_dma_tag(sc->dev), /* Parent tag. */ 830 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 831 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 832 BUS_SPACE_MAXADDR, /* highaddr */ 833 NULL, NULL, /* filter, filterarg */ 834 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 835 TX_DESC_SIZE, /* maxsegsize */ 836 0, /* flags */ 837 NULL, NULL, /* lockfunc, lockarg */ 838 &sc->txdesc_tag); 839 if (error != 0) { 840 device_printf(sc->dev, 841 "could not create TX ring DMA tag.\n"); 842 goto out; 843 } 844 845 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 846 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 847 &sc->txdesc_map); 848 if (error != 0) { 849 device_printf(sc->dev, 850 "could not allocate TX descriptor ring.\n"); 851 goto out; 852 } 853 854 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, 855 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, 856 &sc->txdesc_ring_paddr, 0); 857 if (error != 0) { 858 device_printf(sc->dev, 859 "could not load TX descriptor ring map.\n"); 860 goto out; 861 } 862 863 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 864 nidx = next_txidx(sc, idx); 865 sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + 866 (nidx * sizeof(struct dwc_hwdesc)); 867 } 868 869 error = bus_dma_tag_create( 870 bus_get_dma_tag(sc->dev), /* Parent tag. */ 871 1, 0, /* alignment, boundary */ 872 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 873 BUS_SPACE_MAXADDR, /* highaddr */ 874 NULL, NULL, /* filter, filterarg */ 875 MCLBYTES, 1, /* maxsize, nsegments */ 876 MCLBYTES, /* maxsegsize */ 877 0, /* flags */ 878 NULL, NULL, /* lockfunc, lockarg */ 879 &sc->txbuf_tag); 880 if (error != 0) { 881 device_printf(sc->dev, 882 "could not create TX ring DMA tag.\n"); 883 goto out; 884 } 885 886 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 887 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, 888 &sc->txbuf_map[idx].map); 889 if (error != 0) { 890 device_printf(sc->dev, 891 "could not create TX buffer DMA map.\n"); 892 goto out; 893 } 894 dwc_setup_txdesc(sc, idx, 0, 0); 895 } 896 897 /* 898 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 899 */ 900 error = bus_dma_tag_create( 901 bus_get_dma_tag(sc->dev), /* Parent tag. */ 902 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 903 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 904 BUS_SPACE_MAXADDR, /* highaddr */ 905 NULL, NULL, /* filter, filterarg */ 906 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 907 RX_DESC_SIZE, /* maxsegsize */ 908 0, /* flags */ 909 NULL, NULL, /* lockfunc, lockarg */ 910 &sc->rxdesc_tag); 911 if (error != 0) { 912 device_printf(sc->dev, 913 "could not create RX ring DMA tag.\n"); 914 goto out; 915 } 916 917 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 918 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 919 &sc->rxdesc_map); 920 if (error != 0) { 921 device_printf(sc->dev, 922 "could not allocate RX descriptor ring.\n"); 923 goto out; 924 } 925 926 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, 927 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, 928 &sc->rxdesc_ring_paddr, 0); 929 if (error != 0) { 930 device_printf(sc->dev, 931 "could not load RX descriptor ring map.\n"); 932 goto out; 933 } 934 935 error = bus_dma_tag_create( 936 bus_get_dma_tag(sc->dev), /* Parent tag. */ 937 1, 0, /* alignment, boundary */ 938 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 939 BUS_SPACE_MAXADDR, /* highaddr */ 940 NULL, NULL, /* filter, filterarg */ 941 MCLBYTES, 1, /* maxsize, nsegments */ 942 MCLBYTES, /* maxsegsize */ 943 0, /* flags */ 944 NULL, NULL, /* lockfunc, lockarg */ 945 &sc->rxbuf_tag); 946 if (error != 0) { 947 device_printf(sc->dev, 948 "could not create RX buf DMA tag.\n"); 949 goto out; 950 } 951 952 for (idx = 0; idx < RX_DESC_COUNT; idx++) { 953 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, 954 &sc->rxbuf_map[idx].map); 955 if (error != 0) { 956 device_printf(sc->dev, 957 "could not create RX buffer DMA map.\n"); 958 goto out; 959 } 960 if ((m = dwc_alloc_mbufcl(sc)) == NULL) { 961 device_printf(sc->dev, "Could not alloc mbuf\n"); 962 error = ENOMEM; 963 goto out; 964 } 965 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { 966 device_printf(sc->dev, 967 "could not create new RX buffer.\n"); 968 goto out; 969 } 970 } 971 972 out: 973 if (error != 0) 974 return (ENXIO); 975 976 return (0); 977 } 978 979 static int 980 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) 981 { 982 uint32_t hi, lo, rnd; 983 984 /* 985 * Try to recover a MAC address from the running hardware. If there's 986 * something non-zero there, assume the bootloader did the right thing 987 * and just use it. 988 * 989 * Otherwise, set the address to a convenient locally assigned address, 990 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 991 * assigned bit set, and the broadcast/multicast bit clear. 992 */ 993 lo = READ4(sc, MAC_ADDRESS_LOW(0)); 994 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; 995 if ((lo != 0xffffffff) || (hi != 0xffff)) { 996 hwaddr[0] = (lo >> 0) & 0xff; 997 hwaddr[1] = (lo >> 8) & 0xff; 998 hwaddr[2] = (lo >> 16) & 0xff; 999 hwaddr[3] = (lo >> 24) & 0xff; 1000 hwaddr[4] = (hi >> 0) & 0xff; 1001 hwaddr[5] = (hi >> 8) & 0xff; 1002 } else { 1003 rnd = arc4random() & 0x00ffffff; 1004 hwaddr[0] = 'b'; 1005 hwaddr[1] = 's'; 1006 hwaddr[2] = 'd'; 1007 hwaddr[3] = rnd >> 16; 1008 hwaddr[4] = rnd >> 8; 1009 hwaddr[5] = rnd >> 0; 1010 } 1011 1012 return (0); 1013 } 1014 1015 #define GPIO_ACTIVE_LOW 1 1016 1017 static int 1018 dwc_reset(device_t dev) 1019 { 1020 pcell_t gpio_prop[4]; 1021 pcell_t delay_prop[3]; 1022 phandle_t node, gpio_node; 1023 device_t gpio; 1024 uint32_t pin, flags; 1025 uint32_t pin_value; 1026 1027 node = ofw_bus_get_node(dev); 1028 if (OF_getencprop(node, "snps,reset-gpio", 1029 gpio_prop, sizeof(gpio_prop)) <= 0) 1030 return (0); 1031 1032 if (OF_getencprop(node, "snps,reset-delays-us", 1033 delay_prop, sizeof(delay_prop)) <= 0) { 1034 device_printf(dev, 1035 "Wrong property for snps,reset-delays-us"); 1036 return (ENXIO); 1037 } 1038 1039 gpio_node = OF_node_from_xref(gpio_prop[0]); 1040 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) { 1041 device_printf(dev, 1042 "Can't find gpio controller for phy reset\n"); 1043 return (ENXIO); 1044 } 1045 1046 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, 1047 sizeof(gpio_prop) / sizeof(gpio_prop[0]) - 1, 1048 gpio_prop + 1, &pin, &flags) != 0) { 1049 device_printf(dev, "Can't map gpio for phy reset\n"); 1050 return (ENXIO); 1051 } 1052 1053 pin_value = GPIO_PIN_LOW; 1054 if (OF_hasprop(node, "snps,reset-active-low")) 1055 pin_value = GPIO_PIN_HIGH; 1056 1057 if (flags & GPIO_ACTIVE_LOW) 1058 pin_value = !pin_value; 1059 1060 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); 1061 GPIO_PIN_SET(gpio, pin, pin_value); 1062 DELAY(delay_prop[0]); 1063 GPIO_PIN_SET(gpio, pin, !pin_value); 1064 DELAY(delay_prop[1]); 1065 GPIO_PIN_SET(gpio, pin, pin_value); 1066 DELAY(delay_prop[2]); 1067 1068 return (0); 1069 } 1070 1071 static int 1072 dwc_probe(device_t dev) 1073 { 1074 1075 if (!ofw_bus_status_okay(dev)) 1076 return (ENXIO); 1077 1078 if (!ofw_bus_is_compatible(dev, "snps,dwmac")) 1079 return (ENXIO); 1080 1081 device_set_desc(dev, "Gigabit Ethernet Controller"); 1082 return (BUS_PROBE_DEFAULT); 1083 } 1084 1085 static int 1086 dwc_attach(device_t dev) 1087 { 1088 uint8_t macaddr[ETHER_ADDR_LEN]; 1089 struct dwc_softc *sc; 1090 struct ifnet *ifp; 1091 int error, i; 1092 uint32_t reg; 1093 1094 sc = device_get_softc(dev); 1095 sc->dev = dev; 1096 sc->rx_idx = 0; 1097 sc->txcount = TX_DESC_COUNT; 1098 sc->mii_clk = IF_DWC_MII_CLK(dev); 1099 sc->mactype = IF_DWC_MAC_TYPE(dev); 1100 1101 if (IF_DWC_INIT(dev) != 0) 1102 return (ENXIO); 1103 1104 if (bus_alloc_resources(dev, dwc_spec, sc->res)) { 1105 device_printf(dev, "could not allocate resources\n"); 1106 return (ENXIO); 1107 } 1108 1109 /* Memory interface */ 1110 sc->bst = rman_get_bustag(sc->res[0]); 1111 sc->bsh = rman_get_bushandle(sc->res[0]); 1112 1113 /* Read MAC before reset */ 1114 if (dwc_get_hwaddr(sc, macaddr)) { 1115 device_printf(sc->dev, "can't get mac\n"); 1116 return (ENXIO); 1117 } 1118 1119 /* Reset the PHY if needed */ 1120 if (dwc_reset(dev) != 0) { 1121 device_printf(dev, "Can't reset the PHY\n"); 1122 return (ENXIO); 1123 } 1124 1125 /* Reset */ 1126 reg = READ4(sc, BUS_MODE); 1127 reg |= (BUS_MODE_SWR); 1128 WRITE4(sc, BUS_MODE, reg); 1129 1130 for (i = 0; i < MAC_RESET_TIMEOUT; i++) { 1131 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 1132 break; 1133 DELAY(10); 1134 } 1135 if (i >= MAC_RESET_TIMEOUT) { 1136 device_printf(sc->dev, "Can't reset DWC.\n"); 1137 return (ENXIO); 1138 } 1139 1140 if (sc->mactype == DWC_GMAC_ALT_DESC) { 1141 reg = BUS_MODE_FIXEDBURST; 1142 reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT); 1143 } else 1144 reg = (BUS_MODE_EIGHTXPBL); 1145 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); 1146 WRITE4(sc, BUS_MODE, reg); 1147 1148 /* 1149 * DMA must be stop while changing descriptor list addresses. 1150 */ 1151 reg = READ4(sc, OPERATION_MODE); 1152 reg &= ~(MODE_ST | MODE_SR); 1153 WRITE4(sc, OPERATION_MODE, reg); 1154 1155 if (setup_dma(sc)) 1156 return (ENXIO); 1157 1158 /* Setup addresses */ 1159 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 1160 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 1161 1162 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), 1163 MTX_NETWORK_LOCK, MTX_DEF); 1164 1165 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); 1166 1167 /* Setup interrupt handler. */ 1168 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 1169 NULL, dwc_intr, sc, &sc->intr_cookie); 1170 if (error != 0) { 1171 device_printf(dev, "could not setup interrupt handler.\n"); 1172 return (ENXIO); 1173 } 1174 1175 /* Set up the ethernet interface. */ 1176 sc->ifp = ifp = if_alloc(IFT_ETHER); 1177 1178 ifp->if_softc = sc; 1179 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1180 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1181 ifp->if_capabilities = IFCAP_VLAN_MTU; 1182 ifp->if_capenable = ifp->if_capabilities; 1183 ifp->if_start = dwc_txstart; 1184 ifp->if_ioctl = dwc_ioctl; 1185 ifp->if_init = dwc_init; 1186 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1187 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1188 IFQ_SET_READY(&ifp->if_snd); 1189 1190 /* Attach the mii driver. */ 1191 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, 1192 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 1193 MII_OFFSET_ANY, 0); 1194 1195 if (error != 0) { 1196 device_printf(dev, "PHY attach failed\n"); 1197 return (ENXIO); 1198 } 1199 sc->mii_softc = device_get_softc(sc->miibus); 1200 1201 /* All ready to run, attach the ethernet interface. */ 1202 ether_ifattach(ifp, macaddr); 1203 sc->is_attached = true; 1204 1205 return (0); 1206 } 1207 1208 static int 1209 dwc_miibus_read_reg(device_t dev, int phy, int reg) 1210 { 1211 struct dwc_softc *sc; 1212 uint16_t mii; 1213 size_t cnt; 1214 int rv = 0; 1215 1216 sc = device_get_softc(dev); 1217 1218 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1219 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1220 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1221 | GMII_ADDRESS_GB; /* Busy flag */ 1222 1223 WRITE4(sc, GMII_ADDRESS, mii); 1224 1225 for (cnt = 0; cnt < 1000; cnt++) { 1226 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1227 rv = READ4(sc, GMII_DATA); 1228 break; 1229 } 1230 DELAY(10); 1231 } 1232 1233 return rv; 1234 } 1235 1236 static int 1237 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) 1238 { 1239 struct dwc_softc *sc; 1240 uint16_t mii; 1241 size_t cnt; 1242 1243 sc = device_get_softc(dev); 1244 1245 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1246 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1247 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1248 | GMII_ADDRESS_GB | GMII_ADDRESS_GW; 1249 1250 WRITE4(sc, GMII_DATA, val); 1251 WRITE4(sc, GMII_ADDRESS, mii); 1252 1253 for (cnt = 0; cnt < 1000; cnt++) { 1254 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1255 break; 1256 } 1257 DELAY(10); 1258 } 1259 1260 return (0); 1261 } 1262 1263 static void 1264 dwc_miibus_statchg(device_t dev) 1265 { 1266 struct dwc_softc *sc; 1267 struct mii_data *mii; 1268 uint32_t reg; 1269 1270 /* 1271 * Called by the MII bus driver when the PHY establishes 1272 * link to set the MAC interface registers. 1273 */ 1274 1275 sc = device_get_softc(dev); 1276 1277 DWC_ASSERT_LOCKED(sc); 1278 1279 mii = sc->mii_softc; 1280 1281 if (mii->mii_media_status & IFM_ACTIVE) 1282 sc->link_is_up = true; 1283 else 1284 sc->link_is_up = false; 1285 1286 reg = READ4(sc, MAC_CONFIGURATION); 1287 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1288 case IFM_1000_T: 1289 case IFM_1000_SX: 1290 reg &= ~(CONF_FES | CONF_PS); 1291 break; 1292 case IFM_100_TX: 1293 reg |= (CONF_FES | CONF_PS); 1294 break; 1295 case IFM_10_T: 1296 reg &= ~(CONF_FES); 1297 reg |= (CONF_PS); 1298 break; 1299 case IFM_NONE: 1300 sc->link_is_up = false; 1301 return; 1302 default: 1303 sc->link_is_up = false; 1304 device_printf(dev, "Unsupported media %u\n", 1305 IFM_SUBTYPE(mii->mii_media_active)); 1306 return; 1307 } 1308 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1309 reg |= (CONF_DM); 1310 else 1311 reg &= ~(CONF_DM); 1312 WRITE4(sc, MAC_CONFIGURATION, reg); 1313 } 1314 1315 static device_method_t dwc_methods[] = { 1316 DEVMETHOD(device_probe, dwc_probe), 1317 DEVMETHOD(device_attach, dwc_attach), 1318 1319 /* MII Interface */ 1320 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), 1321 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), 1322 DEVMETHOD(miibus_statchg, dwc_miibus_statchg), 1323 1324 { 0, 0 } 1325 }; 1326 1327 driver_t dwc_driver = { 1328 "dwc", 1329 dwc_methods, 1330 sizeof(struct dwc_softc), 1331 }; 1332 1333 static devclass_t dwc_devclass; 1334 1335 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); 1336 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); 1337 1338 MODULE_DEPEND(dwc, ether, 1, 1, 1); 1339 MODULE_DEPEND(dwc, miibus, 1, 1, 1); 1340