1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Ethernet media access controller (EMAC) 33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 * 35 * EMAC is an instance of the Synopsys DesignWare 3504-0 36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/gpio.h> 46 #include <sys/kernel.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/module.h> 51 #include <sys/mutex.h> 52 #include <sys/rman.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_var.h> 63 64 #include <machine/bus.h> 65 66 #include <dev/dwc/if_dwc.h> 67 #include <dev/dwc/if_dwcvar.h> 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 #include <dev/ofw/ofw_bus.h> 71 #include <dev/ofw/ofw_bus_subr.h> 72 73 #ifdef EXT_RESOURCES 74 #include <dev/extres/clk/clk.h> 75 #include <dev/extres/hwreset/hwreset.h> 76 #endif 77 78 #include "if_dwc_if.h" 79 #include "gpio_if.h" 80 #include "miibus_if.h" 81 82 #define READ4(_sc, _reg) \ 83 bus_read_4((_sc)->res[0], _reg) 84 #define WRITE4(_sc, _reg, _val) \ 85 bus_write_4((_sc)->res[0], _reg, _val) 86 87 #define MAC_RESET_TIMEOUT 100 88 #define WATCHDOG_TIMEOUT_SECS 5 89 #define STATS_HARVEST_INTERVAL 2 90 91 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) 92 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 93 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 94 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 95 96 #define DDESC_TDES0_OWN (1U << 31) 97 #define DDESC_TDES0_TXINT (1U << 30) 98 #define DDESC_TDES0_TXLAST (1U << 29) 99 #define DDESC_TDES0_TXFIRST (1U << 28) 100 #define DDESC_TDES0_TXCRCDIS (1U << 27) 101 #define DDESC_TDES0_TXRINGEND (1U << 21) 102 #define DDESC_TDES0_TXCHAIN (1U << 20) 103 104 #define DDESC_RDES0_OWN (1U << 31) 105 #define DDESC_RDES0_FL_MASK 0x3fff 106 #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ 107 #define DDESC_RDES1_CHAINED (1U << 14) 108 109 /* Alt descriptor bits. */ 110 #define DDESC_CNTL_TXINT (1U << 31) 111 #define DDESC_CNTL_TXLAST (1U << 30) 112 #define DDESC_CNTL_TXFIRST (1U << 29) 113 #define DDESC_CNTL_TXCRCDIS (1U << 26) 114 #define DDESC_CNTL_TXRINGEND (1U << 25) 115 #define DDESC_CNTL_TXCHAIN (1U << 24) 116 117 #define DDESC_CNTL_CHAINED (1U << 24) 118 119 /* 120 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 121 * layout, but the bits in the fields have different meanings. 122 */ 123 struct dwc_hwdesc 124 { 125 uint32_t tdes0; /* status for alt layout */ 126 uint32_t tdes1; /* cntl for alt layout */ 127 uint32_t addr; /* pointer to buffer data */ 128 uint32_t addr_next; /* link to next descriptor */ 129 }; 130 131 /* 132 * The hardware imposes alignment restrictions on various objects involved in 133 * DMA transfers. These values are expressed in bytes (not bits). 134 */ 135 #define DWC_DESC_RING_ALIGN 2048 136 137 static struct resource_spec dwc_spec[] = { 138 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 139 { SYS_RES_IRQ, 0, RF_ACTIVE }, 140 { -1, 0 } 141 }; 142 143 static void dwc_txfinish_locked(struct dwc_softc *sc); 144 static void dwc_rxfinish_locked(struct dwc_softc *sc); 145 static void dwc_stop_locked(struct dwc_softc *sc); 146 static void dwc_setup_rxfilter(struct dwc_softc *sc); 147 148 static inline uint32_t 149 next_rxidx(struct dwc_softc *sc, uint32_t curidx) 150 { 151 152 return ((curidx + 1) % RX_DESC_COUNT); 153 } 154 155 static inline uint32_t 156 next_txidx(struct dwc_softc *sc, uint32_t curidx) 157 { 158 159 return ((curidx + 1) % TX_DESC_COUNT); 160 } 161 162 static void 163 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 164 { 165 166 if (error != 0) 167 return; 168 *(bus_addr_t *)arg = segs[0].ds_addr; 169 } 170 171 inline static uint32_t 172 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, 173 uint32_t len) 174 { 175 uint32_t flags; 176 uint32_t nidx; 177 178 nidx = next_txidx(sc, idx); 179 180 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 181 if (paddr == 0 || len == 0) { 182 flags = 0; 183 --sc->txcount; 184 } else { 185 if (sc->mactype == DWC_GMAC_ALT_DESC) 186 flags = DDESC_CNTL_TXCHAIN | DDESC_CNTL_TXFIRST 187 | DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT; 188 else 189 flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST 190 | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT; 191 ++sc->txcount; 192 } 193 194 sc->txdesc_ring[idx].addr = (uint32_t)(paddr); 195 if (sc->mactype == DWC_GMAC_ALT_DESC) { 196 sc->txdesc_ring[idx].tdes0 = 0; 197 sc->txdesc_ring[idx].tdes1 = flags | len; 198 } else { 199 sc->txdesc_ring[idx].tdes0 = flags; 200 sc->txdesc_ring[idx].tdes1 = len; 201 } 202 203 if (paddr && len) { 204 wmb(); 205 sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN; 206 wmb(); 207 } 208 209 return (nidx); 210 } 211 212 static int 213 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) 214 { 215 struct bus_dma_segment seg; 216 int error, nsegs; 217 struct mbuf * m; 218 219 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 220 return (ENOMEM); 221 *mp = m; 222 223 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 224 m, &seg, &nsegs, 0); 225 if (error != 0) { 226 return (ENOMEM); 227 } 228 229 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 230 231 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 232 BUS_DMASYNC_PREWRITE); 233 234 sc->txbuf_map[idx].mbuf = m; 235 236 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 237 238 return (0); 239 } 240 241 static void 242 dwc_txstart_locked(struct dwc_softc *sc) 243 { 244 struct ifnet *ifp; 245 struct mbuf *m; 246 int enqueued; 247 248 DWC_ASSERT_LOCKED(sc); 249 250 if (!sc->link_is_up) 251 return; 252 253 ifp = sc->ifp; 254 255 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 256 return; 257 258 enqueued = 0; 259 260 for (;;) { 261 if (sc->txcount == (TX_DESC_COUNT - 1)) { 262 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 263 break; 264 } 265 266 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 267 if (m == NULL) 268 break; 269 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 270 IFQ_DRV_PREPEND(&ifp->if_snd, m); 271 break; 272 } 273 BPF_MTAP(ifp, m); 274 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 275 ++enqueued; 276 } 277 278 if (enqueued != 0) { 279 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 280 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 281 } 282 } 283 284 static void 285 dwc_txstart(struct ifnet *ifp) 286 { 287 struct dwc_softc *sc = ifp->if_softc; 288 289 DWC_LOCK(sc); 290 dwc_txstart_locked(sc); 291 DWC_UNLOCK(sc); 292 } 293 294 static void 295 dwc_stop_locked(struct dwc_softc *sc) 296 { 297 struct ifnet *ifp; 298 uint32_t reg; 299 300 DWC_ASSERT_LOCKED(sc); 301 302 ifp = sc->ifp; 303 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 304 sc->tx_watchdog_count = 0; 305 sc->stats_harvest_count = 0; 306 307 callout_stop(&sc->dwc_callout); 308 309 /* Stop DMA TX */ 310 reg = READ4(sc, OPERATION_MODE); 311 reg &= ~(MODE_ST); 312 WRITE4(sc, OPERATION_MODE, reg); 313 314 /* Flush TX */ 315 reg = READ4(sc, OPERATION_MODE); 316 reg |= (MODE_FTF); 317 WRITE4(sc, OPERATION_MODE, reg); 318 319 /* Stop transmitters */ 320 reg = READ4(sc, MAC_CONFIGURATION); 321 reg &= ~(CONF_TE | CONF_RE); 322 WRITE4(sc, MAC_CONFIGURATION, reg); 323 324 /* Stop DMA RX */ 325 reg = READ4(sc, OPERATION_MODE); 326 reg &= ~(MODE_SR); 327 WRITE4(sc, OPERATION_MODE, reg); 328 } 329 330 static void dwc_clear_stats(struct dwc_softc *sc) 331 { 332 uint32_t reg; 333 334 reg = READ4(sc, MMC_CONTROL); 335 reg |= (MMC_CONTROL_CNTRST); 336 WRITE4(sc, MMC_CONTROL, reg); 337 } 338 339 static void 340 dwc_harvest_stats(struct dwc_softc *sc) 341 { 342 struct ifnet *ifp; 343 344 /* We don't need to harvest too often. */ 345 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 346 return; 347 348 sc->stats_harvest_count = 0; 349 ifp = sc->ifp; 350 351 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); 352 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); 353 if_inc_counter(ifp, IFCOUNTER_IERRORS, 354 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + 355 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + 356 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + 357 READ4(sc, RXLENGTHERROR)); 358 359 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); 360 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); 361 if_inc_counter(ifp, IFCOUNTER_OERRORS, 362 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + 363 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); 364 365 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 366 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); 367 368 dwc_clear_stats(sc); 369 } 370 371 static void 372 dwc_tick(void *arg) 373 { 374 struct dwc_softc *sc; 375 struct ifnet *ifp; 376 int link_was_up; 377 378 sc = arg; 379 380 DWC_ASSERT_LOCKED(sc); 381 382 ifp = sc->ifp; 383 384 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 385 return; 386 387 /* 388 * Typical tx watchdog. If this fires it indicates that we enqueued 389 * packets for output and never got a txdone interrupt for them. Maybe 390 * it's a missed interrupt somehow, just pretend we got one. 391 */ 392 if (sc->tx_watchdog_count > 0) { 393 if (--sc->tx_watchdog_count == 0) { 394 dwc_txfinish_locked(sc); 395 } 396 } 397 398 /* Gather stats from hardware counters. */ 399 dwc_harvest_stats(sc); 400 401 /* Check the media status. */ 402 link_was_up = sc->link_is_up; 403 mii_tick(sc->mii_softc); 404 if (sc->link_is_up && !link_was_up) 405 dwc_txstart_locked(sc); 406 407 /* Schedule another check one second from now. */ 408 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 409 } 410 411 static void 412 dwc_init_locked(struct dwc_softc *sc) 413 { 414 struct ifnet *ifp = sc->ifp; 415 uint32_t reg; 416 417 DWC_ASSERT_LOCKED(sc); 418 419 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 420 return; 421 422 ifp->if_drv_flags |= IFF_DRV_RUNNING; 423 424 dwc_setup_rxfilter(sc); 425 426 /* Initializa DMA and enable transmitters */ 427 reg = READ4(sc, OPERATION_MODE); 428 reg |= (MODE_TSF | MODE_OSF | MODE_FUF); 429 reg &= ~(MODE_RSF); 430 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); 431 WRITE4(sc, OPERATION_MODE, reg); 432 433 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 434 435 /* Start DMA */ 436 reg = READ4(sc, OPERATION_MODE); 437 reg |= (MODE_ST | MODE_SR); 438 WRITE4(sc, OPERATION_MODE, reg); 439 440 /* Enable transmitters */ 441 reg = READ4(sc, MAC_CONFIGURATION); 442 reg |= (CONF_JD | CONF_ACS | CONF_BE); 443 reg |= (CONF_TE | CONF_RE); 444 WRITE4(sc, MAC_CONFIGURATION, reg); 445 446 /* 447 * Call mii_mediachg() which will call back into dwc_miibus_statchg() 448 * to set up the remaining config registers based on current media. 449 */ 450 mii_mediachg(sc->mii_softc); 451 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 452 } 453 454 static void 455 dwc_init(void *if_softc) 456 { 457 struct dwc_softc *sc = if_softc; 458 459 DWC_LOCK(sc); 460 dwc_init_locked(sc); 461 DWC_UNLOCK(sc); 462 } 463 464 inline static uint32_t 465 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) 466 { 467 uint32_t nidx; 468 469 sc->rxdesc_ring[idx].addr = (uint32_t)paddr; 470 nidx = next_rxidx(sc, idx); 471 sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + 472 (nidx * sizeof(struct dwc_hwdesc)); 473 if (sc->mactype == DWC_GMAC_ALT_DESC) 474 sc->rxdesc_ring[idx].tdes1 = DDESC_CNTL_CHAINED | RX_MAX_PACKET; 475 else 476 sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; 477 478 wmb(); 479 sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; 480 wmb(); 481 482 return (nidx); 483 } 484 485 static int 486 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) 487 { 488 struct bus_dma_segment seg; 489 int error, nsegs; 490 491 m_adj(m, ETHER_ALIGN); 492 493 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 494 m, &seg, &nsegs, 0); 495 if (error != 0) 496 return (error); 497 498 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 499 500 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 501 BUS_DMASYNC_PREREAD); 502 503 sc->rxbuf_map[idx].mbuf = m; 504 dwc_setup_rxdesc(sc, idx, seg.ds_addr); 505 506 return (0); 507 } 508 509 static struct mbuf * 510 dwc_alloc_mbufcl(struct dwc_softc *sc) 511 { 512 struct mbuf *m; 513 514 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 515 if (m != NULL) 516 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 517 518 return (m); 519 } 520 521 static void 522 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 523 { 524 struct dwc_softc *sc; 525 struct mii_data *mii; 526 527 sc = ifp->if_softc; 528 mii = sc->mii_softc; 529 DWC_LOCK(sc); 530 mii_pollstat(mii); 531 ifmr->ifm_active = mii->mii_media_active; 532 ifmr->ifm_status = mii->mii_media_status; 533 DWC_UNLOCK(sc); 534 } 535 536 static int 537 dwc_media_change_locked(struct dwc_softc *sc) 538 { 539 540 return (mii_mediachg(sc->mii_softc)); 541 } 542 543 static int 544 dwc_media_change(struct ifnet * ifp) 545 { 546 struct dwc_softc *sc; 547 int error; 548 549 sc = ifp->if_softc; 550 551 DWC_LOCK(sc); 552 error = dwc_media_change_locked(sc); 553 DWC_UNLOCK(sc); 554 return (error); 555 } 556 557 static const uint8_t nibbletab[] = { 558 /* 0x0 0000 -> 0000 */ 0x0, 559 /* 0x1 0001 -> 1000 */ 0x8, 560 /* 0x2 0010 -> 0100 */ 0x4, 561 /* 0x3 0011 -> 1100 */ 0xc, 562 /* 0x4 0100 -> 0010 */ 0x2, 563 /* 0x5 0101 -> 1010 */ 0xa, 564 /* 0x6 0110 -> 0110 */ 0x6, 565 /* 0x7 0111 -> 1110 */ 0xe, 566 /* 0x8 1000 -> 0001 */ 0x1, 567 /* 0x9 1001 -> 1001 */ 0x9, 568 /* 0xa 1010 -> 0101 */ 0x5, 569 /* 0xb 1011 -> 1101 */ 0xd, 570 /* 0xc 1100 -> 0011 */ 0x3, 571 /* 0xd 1101 -> 1011 */ 0xb, 572 /* 0xe 1110 -> 0111 */ 0x7, 573 /* 0xf 1111 -> 1111 */ 0xf, }; 574 575 static uint8_t 576 bitreverse(uint8_t x) 577 { 578 579 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; 580 } 581 582 struct dwc_hash_maddr_ctx { 583 struct dwc_softc *sc; 584 uint32_t hash[8]; 585 }; 586 587 static u_int 588 dwc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 589 { 590 struct dwc_hash_maddr_ctx *ctx = arg; 591 uint32_t crc, hashbit, hashreg; 592 uint8_t val; 593 594 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN); 595 /* Take lower 8 bits and reverse it */ 596 val = bitreverse(~crc & 0xff); 597 if (ctx->sc->mactype == DWC_GMAC_ALT_DESC) 598 val >>= 2; /* Only need lower 6 bits */ 599 hashreg = (val >> 5); 600 hashbit = (val & 31); 601 ctx->hash[hashreg] |= (1 << hashbit); 602 603 return (1); 604 } 605 606 static void 607 dwc_setup_rxfilter(struct dwc_softc *sc) 608 { 609 struct dwc_hash_maddr_ctx ctx; 610 struct ifnet *ifp; 611 uint8_t *eaddr; 612 uint32_t ffval, hi, lo; 613 int nhash, i; 614 615 DWC_ASSERT_LOCKED(sc); 616 617 ifp = sc->ifp; 618 nhash = sc->mactype == DWC_GMAC_ALT_DESC ? 2 : 8; 619 620 /* 621 * Set the multicast (group) filter hash. 622 */ 623 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 624 ffval = (FRAME_FILTER_PM); 625 for (i = 0; i < nhash; i++) 626 ctx.hash[i] = ~0; 627 } else { 628 ffval = (FRAME_FILTER_HMC); 629 for (i = 0; i < nhash; i++) 630 ctx.hash[i] = 0; 631 ctx.sc = sc; 632 if_foreach_llmaddr(ifp, dwc_hash_maddr, &ctx); 633 } 634 635 /* 636 * Set the individual address filter hash. 637 */ 638 if (ifp->if_flags & IFF_PROMISC) 639 ffval |= (FRAME_FILTER_PR); 640 641 /* 642 * Set the primary address. 643 */ 644 eaddr = IF_LLADDR(ifp); 645 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 646 (eaddr[3] << 24); 647 hi = eaddr[4] | (eaddr[5] << 8); 648 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); 649 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); 650 WRITE4(sc, MAC_FRAME_FILTER, ffval); 651 if (sc->mactype == DWC_GMAC_ALT_DESC) { 652 WRITE4(sc, GMAC_MAC_HTLOW, ctx.hash[0]); 653 WRITE4(sc, GMAC_MAC_HTHIGH, ctx.hash[1]); 654 } else { 655 for (i = 0; i < nhash; i++) 656 WRITE4(sc, HASH_TABLE_REG(i), ctx.hash[i]); 657 } 658 } 659 660 static int 661 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 662 { 663 struct dwc_softc *sc; 664 struct mii_data *mii; 665 struct ifreq *ifr; 666 int mask, error; 667 668 sc = ifp->if_softc; 669 ifr = (struct ifreq *)data; 670 671 error = 0; 672 switch (cmd) { 673 case SIOCSIFFLAGS: 674 DWC_LOCK(sc); 675 if (ifp->if_flags & IFF_UP) { 676 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 677 if ((ifp->if_flags ^ sc->if_flags) & 678 (IFF_PROMISC | IFF_ALLMULTI)) 679 dwc_setup_rxfilter(sc); 680 } else { 681 if (!sc->is_detaching) 682 dwc_init_locked(sc); 683 } 684 } else { 685 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 686 dwc_stop_locked(sc); 687 } 688 sc->if_flags = ifp->if_flags; 689 DWC_UNLOCK(sc); 690 break; 691 case SIOCADDMULTI: 692 case SIOCDELMULTI: 693 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 694 DWC_LOCK(sc); 695 dwc_setup_rxfilter(sc); 696 DWC_UNLOCK(sc); 697 } 698 break; 699 case SIOCSIFMEDIA: 700 case SIOCGIFMEDIA: 701 mii = sc->mii_softc; 702 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 703 break; 704 case SIOCSIFCAP: 705 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 706 if (mask & IFCAP_VLAN_MTU) { 707 /* No work to do except acknowledge the change took */ 708 ifp->if_capenable ^= IFCAP_VLAN_MTU; 709 } 710 break; 711 712 default: 713 error = ether_ioctl(ifp, cmd, data); 714 break; 715 } 716 717 return (error); 718 } 719 720 static void 721 dwc_txfinish_locked(struct dwc_softc *sc) 722 { 723 struct dwc_bufmap *bmap; 724 struct dwc_hwdesc *desc; 725 struct ifnet *ifp; 726 727 DWC_ASSERT_LOCKED(sc); 728 729 ifp = sc->ifp; 730 while (sc->tx_idx_tail != sc->tx_idx_head) { 731 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 732 if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) 733 break; 734 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 735 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 736 BUS_DMASYNC_POSTWRITE); 737 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 738 m_freem(bmap->mbuf); 739 bmap->mbuf = NULL; 740 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 741 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 742 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 743 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 744 } 745 746 /* If there are no buffers outstanding, muzzle the watchdog. */ 747 if (sc->tx_idx_tail == sc->tx_idx_head) { 748 sc->tx_watchdog_count = 0; 749 } 750 } 751 752 static void 753 dwc_rxfinish_locked(struct dwc_softc *sc) 754 { 755 struct ifnet *ifp; 756 struct mbuf *m0; 757 struct mbuf *m; 758 int error, idx, len; 759 uint32_t rdes0; 760 761 ifp = sc->ifp; 762 763 for (;;) { 764 idx = sc->rx_idx; 765 766 rdes0 = sc->rxdesc_ring[idx].tdes0; 767 if ((rdes0 & DDESC_RDES0_OWN) != 0) 768 break; 769 770 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 771 BUS_DMASYNC_POSTREAD); 772 bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); 773 774 len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; 775 if (len != 0) { 776 m = sc->rxbuf_map[idx].mbuf; 777 m->m_pkthdr.rcvif = ifp; 778 m->m_pkthdr.len = len; 779 m->m_len = len; 780 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 781 782 /* Remove trailing FCS */ 783 m_adj(m, -ETHER_CRC_LEN); 784 785 DWC_UNLOCK(sc); 786 (*ifp->if_input)(ifp, m); 787 DWC_LOCK(sc); 788 } else { 789 /* XXX Zero-length packet ? */ 790 } 791 792 if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) { 793 if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { 794 /* 795 * XXX Now what? 796 * We've got a hole in the rx ring. 797 */ 798 } 799 } else 800 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 801 802 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 803 } 804 } 805 806 static void 807 dwc_intr(void *arg) 808 { 809 struct dwc_softc *sc; 810 uint32_t reg; 811 812 sc = arg; 813 814 DWC_LOCK(sc); 815 816 reg = READ4(sc, INTERRUPT_STATUS); 817 if (reg) 818 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); 819 820 reg = READ4(sc, DMA_STATUS); 821 if (reg & DMA_STATUS_NIS) { 822 if (reg & DMA_STATUS_RI) 823 dwc_rxfinish_locked(sc); 824 825 if (reg & DMA_STATUS_TI) { 826 dwc_txfinish_locked(sc); 827 dwc_txstart_locked(sc); 828 } 829 } 830 831 if (reg & DMA_STATUS_AIS) { 832 if (reg & DMA_STATUS_FBI) { 833 /* Fatal bus error */ 834 device_printf(sc->dev, 835 "Ethernet DMA error, restarting controller.\n"); 836 dwc_stop_locked(sc); 837 dwc_init_locked(sc); 838 } 839 } 840 841 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 842 DWC_UNLOCK(sc); 843 } 844 845 static int 846 setup_dma(struct dwc_softc *sc) 847 { 848 struct mbuf *m; 849 int error; 850 int nidx; 851 int idx; 852 853 /* 854 * Set up TX descriptor ring, descriptors, and dma maps. 855 */ 856 error = bus_dma_tag_create( 857 bus_get_dma_tag(sc->dev), /* Parent tag. */ 858 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 859 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 860 BUS_SPACE_MAXADDR, /* highaddr */ 861 NULL, NULL, /* filter, filterarg */ 862 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 863 TX_DESC_SIZE, /* maxsegsize */ 864 0, /* flags */ 865 NULL, NULL, /* lockfunc, lockarg */ 866 &sc->txdesc_tag); 867 if (error != 0) { 868 device_printf(sc->dev, 869 "could not create TX ring DMA tag.\n"); 870 goto out; 871 } 872 873 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 874 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 875 &sc->txdesc_map); 876 if (error != 0) { 877 device_printf(sc->dev, 878 "could not allocate TX descriptor ring.\n"); 879 goto out; 880 } 881 882 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, 883 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, 884 &sc->txdesc_ring_paddr, 0); 885 if (error != 0) { 886 device_printf(sc->dev, 887 "could not load TX descriptor ring map.\n"); 888 goto out; 889 } 890 891 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 892 nidx = next_txidx(sc, idx); 893 sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + 894 (nidx * sizeof(struct dwc_hwdesc)); 895 } 896 897 error = bus_dma_tag_create( 898 bus_get_dma_tag(sc->dev), /* Parent tag. */ 899 1, 0, /* alignment, boundary */ 900 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 901 BUS_SPACE_MAXADDR, /* highaddr */ 902 NULL, NULL, /* filter, filterarg */ 903 MCLBYTES, 1, /* maxsize, nsegments */ 904 MCLBYTES, /* maxsegsize */ 905 0, /* flags */ 906 NULL, NULL, /* lockfunc, lockarg */ 907 &sc->txbuf_tag); 908 if (error != 0) { 909 device_printf(sc->dev, 910 "could not create TX ring DMA tag.\n"); 911 goto out; 912 } 913 914 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 915 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, 916 &sc->txbuf_map[idx].map); 917 if (error != 0) { 918 device_printf(sc->dev, 919 "could not create TX buffer DMA map.\n"); 920 goto out; 921 } 922 dwc_setup_txdesc(sc, idx, 0, 0); 923 } 924 925 /* 926 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 927 */ 928 error = bus_dma_tag_create( 929 bus_get_dma_tag(sc->dev), /* Parent tag. */ 930 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 931 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 932 BUS_SPACE_MAXADDR, /* highaddr */ 933 NULL, NULL, /* filter, filterarg */ 934 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 935 RX_DESC_SIZE, /* maxsegsize */ 936 0, /* flags */ 937 NULL, NULL, /* lockfunc, lockarg */ 938 &sc->rxdesc_tag); 939 if (error != 0) { 940 device_printf(sc->dev, 941 "could not create RX ring DMA tag.\n"); 942 goto out; 943 } 944 945 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 946 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 947 &sc->rxdesc_map); 948 if (error != 0) { 949 device_printf(sc->dev, 950 "could not allocate RX descriptor ring.\n"); 951 goto out; 952 } 953 954 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, 955 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, 956 &sc->rxdesc_ring_paddr, 0); 957 if (error != 0) { 958 device_printf(sc->dev, 959 "could not load RX descriptor ring map.\n"); 960 goto out; 961 } 962 963 error = bus_dma_tag_create( 964 bus_get_dma_tag(sc->dev), /* Parent tag. */ 965 1, 0, /* alignment, boundary */ 966 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 967 BUS_SPACE_MAXADDR, /* highaddr */ 968 NULL, NULL, /* filter, filterarg */ 969 MCLBYTES, 1, /* maxsize, nsegments */ 970 MCLBYTES, /* maxsegsize */ 971 0, /* flags */ 972 NULL, NULL, /* lockfunc, lockarg */ 973 &sc->rxbuf_tag); 974 if (error != 0) { 975 device_printf(sc->dev, 976 "could not create RX buf DMA tag.\n"); 977 goto out; 978 } 979 980 for (idx = 0; idx < RX_DESC_COUNT; idx++) { 981 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, 982 &sc->rxbuf_map[idx].map); 983 if (error != 0) { 984 device_printf(sc->dev, 985 "could not create RX buffer DMA map.\n"); 986 goto out; 987 } 988 if ((m = dwc_alloc_mbufcl(sc)) == NULL) { 989 device_printf(sc->dev, "Could not alloc mbuf\n"); 990 error = ENOMEM; 991 goto out; 992 } 993 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { 994 device_printf(sc->dev, 995 "could not create new RX buffer.\n"); 996 goto out; 997 } 998 } 999 1000 out: 1001 if (error != 0) 1002 return (ENXIO); 1003 1004 return (0); 1005 } 1006 1007 static int 1008 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) 1009 { 1010 uint32_t hi, lo, rnd; 1011 1012 /* 1013 * Try to recover a MAC address from the running hardware. If there's 1014 * something non-zero there, assume the bootloader did the right thing 1015 * and just use it. 1016 * 1017 * Otherwise, set the address to a convenient locally assigned address, 1018 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 1019 * assigned bit set, and the broadcast/multicast bit clear. 1020 */ 1021 lo = READ4(sc, MAC_ADDRESS_LOW(0)); 1022 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; 1023 if ((lo != 0xffffffff) || (hi != 0xffff)) { 1024 hwaddr[0] = (lo >> 0) & 0xff; 1025 hwaddr[1] = (lo >> 8) & 0xff; 1026 hwaddr[2] = (lo >> 16) & 0xff; 1027 hwaddr[3] = (lo >> 24) & 0xff; 1028 hwaddr[4] = (hi >> 0) & 0xff; 1029 hwaddr[5] = (hi >> 8) & 0xff; 1030 } else { 1031 rnd = arc4random() & 0x00ffffff; 1032 hwaddr[0] = 'b'; 1033 hwaddr[1] = 's'; 1034 hwaddr[2] = 'd'; 1035 hwaddr[3] = rnd >> 16; 1036 hwaddr[4] = rnd >> 8; 1037 hwaddr[5] = rnd >> 0; 1038 } 1039 1040 return (0); 1041 } 1042 1043 #define GPIO_ACTIVE_LOW 1 1044 1045 static int 1046 dwc_reset(device_t dev) 1047 { 1048 pcell_t gpio_prop[4]; 1049 pcell_t delay_prop[3]; 1050 phandle_t node, gpio_node; 1051 device_t gpio; 1052 uint32_t pin, flags; 1053 uint32_t pin_value; 1054 1055 node = ofw_bus_get_node(dev); 1056 if (OF_getencprop(node, "snps,reset-gpio", 1057 gpio_prop, sizeof(gpio_prop)) <= 0) 1058 return (0); 1059 1060 if (OF_getencprop(node, "snps,reset-delays-us", 1061 delay_prop, sizeof(delay_prop)) <= 0) { 1062 device_printf(dev, 1063 "Wrong property for snps,reset-delays-us"); 1064 return (ENXIO); 1065 } 1066 1067 gpio_node = OF_node_from_xref(gpio_prop[0]); 1068 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) { 1069 device_printf(dev, 1070 "Can't find gpio controller for phy reset\n"); 1071 return (ENXIO); 1072 } 1073 1074 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, 1075 nitems(gpio_prop) - 1, 1076 gpio_prop + 1, &pin, &flags) != 0) { 1077 device_printf(dev, "Can't map gpio for phy reset\n"); 1078 return (ENXIO); 1079 } 1080 1081 pin_value = GPIO_PIN_LOW; 1082 if (OF_hasprop(node, "snps,reset-active-low")) 1083 pin_value = GPIO_PIN_HIGH; 1084 1085 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); 1086 GPIO_PIN_SET(gpio, pin, pin_value); 1087 DELAY(delay_prop[0] * 5); 1088 GPIO_PIN_SET(gpio, pin, !pin_value); 1089 DELAY(delay_prop[1] * 5); 1090 GPIO_PIN_SET(gpio, pin, pin_value); 1091 DELAY(delay_prop[2] * 5); 1092 1093 return (0); 1094 } 1095 1096 #ifdef EXT_RESOURCES 1097 static int 1098 dwc_clock_init(device_t dev) 1099 { 1100 hwreset_t rst; 1101 clk_t clk; 1102 int error; 1103 1104 /* Enable clock */ 1105 if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk) == 0) { 1106 error = clk_enable(clk); 1107 if (error != 0) { 1108 device_printf(dev, "could not enable main clock\n"); 1109 return (error); 1110 } 1111 } 1112 1113 /* De-assert reset */ 1114 if (hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst) == 0) { 1115 error = hwreset_deassert(rst); 1116 if (error != 0) { 1117 device_printf(dev, "could not de-assert reset\n"); 1118 return (error); 1119 } 1120 } 1121 1122 return (0); 1123 } 1124 #endif 1125 1126 static int 1127 dwc_probe(device_t dev) 1128 { 1129 1130 if (!ofw_bus_status_okay(dev)) 1131 return (ENXIO); 1132 1133 if (!ofw_bus_is_compatible(dev, "snps,dwmac")) 1134 return (ENXIO); 1135 1136 device_set_desc(dev, "Gigabit Ethernet Controller"); 1137 return (BUS_PROBE_DEFAULT); 1138 } 1139 1140 static int 1141 dwc_attach(device_t dev) 1142 { 1143 uint8_t macaddr[ETHER_ADDR_LEN]; 1144 struct dwc_softc *sc; 1145 struct ifnet *ifp; 1146 int error, i; 1147 uint32_t reg; 1148 1149 sc = device_get_softc(dev); 1150 sc->dev = dev; 1151 sc->rx_idx = 0; 1152 sc->txcount = TX_DESC_COUNT; 1153 sc->mii_clk = IF_DWC_MII_CLK(dev); 1154 sc->mactype = IF_DWC_MAC_TYPE(dev); 1155 1156 if (IF_DWC_INIT(dev) != 0) 1157 return (ENXIO); 1158 1159 #ifdef EXT_RESOURCES 1160 if (dwc_clock_init(dev) != 0) 1161 return (ENXIO); 1162 #endif 1163 1164 if (bus_alloc_resources(dev, dwc_spec, sc->res)) { 1165 device_printf(dev, "could not allocate resources\n"); 1166 return (ENXIO); 1167 } 1168 1169 /* Read MAC before reset */ 1170 if (dwc_get_hwaddr(sc, macaddr)) { 1171 device_printf(sc->dev, "can't get mac\n"); 1172 return (ENXIO); 1173 } 1174 1175 /* Reset the PHY if needed */ 1176 if (dwc_reset(dev) != 0) { 1177 device_printf(dev, "Can't reset the PHY\n"); 1178 return (ENXIO); 1179 } 1180 1181 /* Reset */ 1182 reg = READ4(sc, BUS_MODE); 1183 reg |= (BUS_MODE_SWR); 1184 WRITE4(sc, BUS_MODE, reg); 1185 1186 for (i = 0; i < MAC_RESET_TIMEOUT; i++) { 1187 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 1188 break; 1189 DELAY(10); 1190 } 1191 if (i >= MAC_RESET_TIMEOUT) { 1192 device_printf(sc->dev, "Can't reset DWC.\n"); 1193 return (ENXIO); 1194 } 1195 1196 if (sc->mactype == DWC_GMAC_ALT_DESC) { 1197 reg = BUS_MODE_FIXEDBURST; 1198 reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT); 1199 } else 1200 reg = (BUS_MODE_EIGHTXPBL); 1201 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); 1202 WRITE4(sc, BUS_MODE, reg); 1203 1204 /* 1205 * DMA must be stop while changing descriptor list addresses. 1206 */ 1207 reg = READ4(sc, OPERATION_MODE); 1208 reg &= ~(MODE_ST | MODE_SR); 1209 WRITE4(sc, OPERATION_MODE, reg); 1210 1211 if (setup_dma(sc)) 1212 return (ENXIO); 1213 1214 /* Setup addresses */ 1215 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 1216 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 1217 1218 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), 1219 MTX_NETWORK_LOCK, MTX_DEF); 1220 1221 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); 1222 1223 /* Setup interrupt handler. */ 1224 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 1225 NULL, dwc_intr, sc, &sc->intr_cookie); 1226 if (error != 0) { 1227 device_printf(dev, "could not setup interrupt handler.\n"); 1228 return (ENXIO); 1229 } 1230 1231 /* Set up the ethernet interface. */ 1232 sc->ifp = ifp = if_alloc(IFT_ETHER); 1233 1234 ifp->if_softc = sc; 1235 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1236 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1237 ifp->if_capabilities = IFCAP_VLAN_MTU; 1238 ifp->if_capenable = ifp->if_capabilities; 1239 ifp->if_start = dwc_txstart; 1240 ifp->if_ioctl = dwc_ioctl; 1241 ifp->if_init = dwc_init; 1242 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1243 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1244 IFQ_SET_READY(&ifp->if_snd); 1245 1246 /* Attach the mii driver. */ 1247 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, 1248 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 1249 MII_OFFSET_ANY, 0); 1250 1251 if (error != 0) { 1252 device_printf(dev, "PHY attach failed\n"); 1253 return (ENXIO); 1254 } 1255 sc->mii_softc = device_get_softc(sc->miibus); 1256 1257 /* All ready to run, attach the ethernet interface. */ 1258 ether_ifattach(ifp, macaddr); 1259 sc->is_attached = true; 1260 1261 return (0); 1262 } 1263 1264 static int 1265 dwc_miibus_read_reg(device_t dev, int phy, int reg) 1266 { 1267 struct dwc_softc *sc; 1268 uint16_t mii; 1269 size_t cnt; 1270 int rv = 0; 1271 1272 sc = device_get_softc(dev); 1273 1274 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1275 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1276 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1277 | GMII_ADDRESS_GB; /* Busy flag */ 1278 1279 WRITE4(sc, GMII_ADDRESS, mii); 1280 1281 for (cnt = 0; cnt < 1000; cnt++) { 1282 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1283 rv = READ4(sc, GMII_DATA); 1284 break; 1285 } 1286 DELAY(10); 1287 } 1288 1289 return rv; 1290 } 1291 1292 static int 1293 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) 1294 { 1295 struct dwc_softc *sc; 1296 uint16_t mii; 1297 size_t cnt; 1298 1299 sc = device_get_softc(dev); 1300 1301 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1302 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1303 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1304 | GMII_ADDRESS_GB | GMII_ADDRESS_GW; 1305 1306 WRITE4(sc, GMII_DATA, val); 1307 WRITE4(sc, GMII_ADDRESS, mii); 1308 1309 for (cnt = 0; cnt < 1000; cnt++) { 1310 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1311 break; 1312 } 1313 DELAY(10); 1314 } 1315 1316 return (0); 1317 } 1318 1319 static void 1320 dwc_miibus_statchg(device_t dev) 1321 { 1322 struct dwc_softc *sc; 1323 struct mii_data *mii; 1324 uint32_t reg; 1325 1326 /* 1327 * Called by the MII bus driver when the PHY establishes 1328 * link to set the MAC interface registers. 1329 */ 1330 1331 sc = device_get_softc(dev); 1332 1333 DWC_ASSERT_LOCKED(sc); 1334 1335 mii = sc->mii_softc; 1336 1337 if (mii->mii_media_status & IFM_ACTIVE) 1338 sc->link_is_up = true; 1339 else 1340 sc->link_is_up = false; 1341 1342 reg = READ4(sc, MAC_CONFIGURATION); 1343 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1344 case IFM_1000_T: 1345 case IFM_1000_SX: 1346 reg &= ~(CONF_FES | CONF_PS); 1347 break; 1348 case IFM_100_TX: 1349 reg |= (CONF_FES | CONF_PS); 1350 break; 1351 case IFM_10_T: 1352 reg &= ~(CONF_FES); 1353 reg |= (CONF_PS); 1354 break; 1355 case IFM_NONE: 1356 sc->link_is_up = false; 1357 return; 1358 default: 1359 sc->link_is_up = false; 1360 device_printf(dev, "Unsupported media %u\n", 1361 IFM_SUBTYPE(mii->mii_media_active)); 1362 return; 1363 } 1364 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1365 reg |= (CONF_DM); 1366 else 1367 reg &= ~(CONF_DM); 1368 WRITE4(sc, MAC_CONFIGURATION, reg); 1369 } 1370 1371 static device_method_t dwc_methods[] = { 1372 DEVMETHOD(device_probe, dwc_probe), 1373 DEVMETHOD(device_attach, dwc_attach), 1374 1375 /* MII Interface */ 1376 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), 1377 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), 1378 DEVMETHOD(miibus_statchg, dwc_miibus_statchg), 1379 1380 { 0, 0 } 1381 }; 1382 1383 driver_t dwc_driver = { 1384 "dwc", 1385 dwc_methods, 1386 sizeof(struct dwc_softc), 1387 }; 1388 1389 static devclass_t dwc_devclass; 1390 1391 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); 1392 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); 1393 1394 MODULE_DEPEND(dwc, ether, 1, 1, 1); 1395 MODULE_DEPEND(dwc, miibus, 1, 1, 1); 1396