1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Ethernet media access controller (EMAC) 33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 * 35 * EMAC is an instance of the Synopsys DesignWare 3504-0 36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/malloc.h> 48 #include <sys/rman.h> 49 #include <sys/endian.h> 50 #include <sys/lock.h> 51 #include <sys/mbuf.h> 52 #include <sys/mutex.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 #include <sys/sysctl.h> 56 57 #include <dev/fdt/fdt_common.h> 58 #include <dev/ofw/openfirm.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 62 #include <net/bpf.h> 63 #include <net/if.h> 64 #include <net/ethernet.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 #include <net/if_var.h> 69 #include <net/if_vlan_var.h> 70 71 #include <machine/bus.h> 72 #include <machine/fdt.h> 73 74 #include <dev/mii/mii.h> 75 #include <dev/mii/miivar.h> 76 #include "miibus_if.h" 77 78 #define READ4(_sc, _reg) \ 79 bus_read_4((_sc)->res[0], _reg) 80 #define WRITE4(_sc, _reg, _val) \ 81 bus_write_4((_sc)->res[0], _reg, _val) 82 83 #define MAC_RESET_TIMEOUT 100 84 #define WATCHDOG_TIMEOUT_SECS 5 85 #define STATS_HARVEST_INTERVAL 2 86 #define MII_CLK_VAL 2 87 88 #include <dev/dwc/if_dwc.h> 89 90 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) 91 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 92 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 93 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 94 95 #define DDESC_TDES0_OWN (1U << 31) 96 #define DDESC_TDES0_TXINT (1U << 30) 97 #define DDESC_TDES0_TXLAST (1U << 29) 98 #define DDESC_TDES0_TXFIRST (1U << 28) 99 #define DDESC_TDES0_TXCRCDIS (1U << 27) 100 #define DDESC_TDES0_TXRINGEND (1U << 21) 101 #define DDESC_TDES0_TXCHAIN (1U << 20) 102 103 #define DDESC_RDES0_OWN (1U << 31) 104 #define DDESC_RDES0_FL_MASK 0x3fff 105 #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ 106 #define DDESC_RDES1_CHAINED (1U << 14) 107 108 struct dwc_bufmap { 109 bus_dmamap_t map; 110 struct mbuf *mbuf; 111 }; 112 113 /* 114 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 115 * layout, but the bits in the flags field have different meanings. 116 */ 117 struct dwc_hwdesc 118 { 119 uint32_t tdes0; 120 uint32_t tdes1; 121 uint32_t addr; /* pointer to buffer data */ 122 uint32_t addr_next; /* link to next descriptor */ 123 }; 124 125 /* 126 * Driver data and defines. 127 */ 128 #define RX_DESC_COUNT 1024 129 #define RX_DESC_SIZE (sizeof(struct dwc_hwdesc) * RX_DESC_COUNT) 130 #define TX_DESC_COUNT 1024 131 #define TX_DESC_SIZE (sizeof(struct dwc_hwdesc) * TX_DESC_COUNT) 132 133 /* 134 * The hardware imposes alignment restrictions on various objects involved in 135 * DMA transfers. These values are expressed in bytes (not bits). 136 */ 137 #define DWC_DESC_RING_ALIGN 2048 138 139 struct dwc_softc { 140 struct resource *res[2]; 141 bus_space_tag_t bst; 142 bus_space_handle_t bsh; 143 device_t dev; 144 int mii_clk; 145 device_t miibus; 146 struct mii_data * mii_softc; 147 struct ifnet *ifp; 148 int if_flags; 149 struct mtx mtx; 150 void * intr_cookie; 151 struct callout dwc_callout; 152 boolean_t link_is_up; 153 boolean_t is_attached; 154 boolean_t is_detaching; 155 int tx_watchdog_count; 156 int stats_harvest_count; 157 158 /* RX */ 159 bus_dma_tag_t rxdesc_tag; 160 bus_dmamap_t rxdesc_map; 161 struct dwc_hwdesc *rxdesc_ring; 162 bus_addr_t rxdesc_ring_paddr; 163 bus_dma_tag_t rxbuf_tag; 164 struct dwc_bufmap rxbuf_map[RX_DESC_COUNT]; 165 uint32_t rx_idx; 166 167 /* TX */ 168 bus_dma_tag_t txdesc_tag; 169 bus_dmamap_t txdesc_map; 170 struct dwc_hwdesc *txdesc_ring; 171 bus_addr_t txdesc_ring_paddr; 172 bus_dma_tag_t txbuf_tag; 173 struct dwc_bufmap txbuf_map[RX_DESC_COUNT]; 174 uint32_t tx_idx_head; 175 uint32_t tx_idx_tail; 176 int txcount; 177 }; 178 179 static struct resource_spec dwc_spec[] = { 180 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 181 { SYS_RES_IRQ, 0, RF_ACTIVE }, 182 { -1, 0 } 183 }; 184 185 static void dwc_txfinish_locked(struct dwc_softc *sc); 186 static void dwc_rxfinish_locked(struct dwc_softc *sc); 187 static void dwc_stop_locked(struct dwc_softc *sc); 188 static void dwc_setup_rxfilter(struct dwc_softc *sc); 189 190 static inline uint32_t 191 next_rxidx(struct dwc_softc *sc, uint32_t curidx) 192 { 193 194 return ((curidx + 1) % RX_DESC_COUNT); 195 } 196 197 static inline uint32_t 198 next_txidx(struct dwc_softc *sc, uint32_t curidx) 199 { 200 201 return ((curidx + 1) % TX_DESC_COUNT); 202 } 203 204 static void 205 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 206 { 207 208 if (error != 0) 209 return; 210 *(bus_addr_t *)arg = segs[0].ds_addr; 211 } 212 213 inline static uint32_t 214 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, 215 uint32_t len) 216 { 217 uint32_t flags; 218 uint32_t nidx; 219 220 nidx = next_txidx(sc, idx); 221 222 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 223 if (paddr == 0 || len == 0) { 224 flags = 0; 225 --sc->txcount; 226 } else { 227 flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST 228 | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT; 229 ++sc->txcount; 230 } 231 232 sc->txdesc_ring[idx].addr = (uint32_t)(paddr); 233 sc->txdesc_ring[idx].tdes0 = flags; 234 sc->txdesc_ring[idx].tdes1 = len; 235 236 if (paddr && len) { 237 wmb(); 238 sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN; 239 wmb(); 240 } 241 242 return (nidx); 243 } 244 245 static int 246 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) 247 { 248 struct bus_dma_segment seg; 249 int error, nsegs; 250 struct mbuf * m; 251 252 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 253 return (ENOMEM); 254 *mp = m; 255 256 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 257 m, &seg, &nsegs, 0); 258 if (error != 0) { 259 return (ENOMEM); 260 } 261 262 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 263 264 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 265 BUS_DMASYNC_PREWRITE); 266 267 sc->txbuf_map[idx].mbuf = m; 268 269 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 270 271 return (0); 272 } 273 274 static void 275 dwc_txstart_locked(struct dwc_softc *sc) 276 { 277 struct ifnet *ifp; 278 struct mbuf *m; 279 int enqueued; 280 281 DWC_ASSERT_LOCKED(sc); 282 283 if (!sc->link_is_up) 284 return; 285 286 ifp = sc->ifp; 287 288 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 289 return; 290 } 291 292 enqueued = 0; 293 294 for (;;) { 295 if (sc->txcount == (TX_DESC_COUNT-1)) { 296 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 297 break; 298 } 299 300 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 301 if (m == NULL) 302 break; 303 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 304 IFQ_DRV_PREPEND(&ifp->if_snd, m); 305 break; 306 } 307 BPF_MTAP(ifp, m); 308 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 309 ++enqueued; 310 } 311 312 if (enqueued != 0) { 313 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 314 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 315 } 316 } 317 318 static void 319 dwc_txstart(struct ifnet *ifp) 320 { 321 struct dwc_softc *sc = ifp->if_softc; 322 323 DWC_LOCK(sc); 324 dwc_txstart_locked(sc); 325 DWC_UNLOCK(sc); 326 } 327 328 static void 329 dwc_stop_locked(struct dwc_softc *sc) 330 { 331 struct ifnet *ifp; 332 uint32_t reg; 333 334 DWC_ASSERT_LOCKED(sc); 335 336 ifp = sc->ifp; 337 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 338 sc->tx_watchdog_count = 0; 339 sc->stats_harvest_count = 0; 340 341 callout_stop(&sc->dwc_callout); 342 343 /* Stop DMA TX */ 344 reg = READ4(sc, OPERATION_MODE); 345 reg &= ~(MODE_ST); 346 WRITE4(sc, OPERATION_MODE, reg); 347 348 /* Flush TX */ 349 reg = READ4(sc, OPERATION_MODE); 350 reg |= (MODE_FTF); 351 WRITE4(sc, OPERATION_MODE, reg); 352 353 /* Stop transmitters */ 354 reg = READ4(sc, MAC_CONFIGURATION); 355 reg &= ~(CONF_TE | CONF_RE); 356 WRITE4(sc, MAC_CONFIGURATION, reg); 357 358 /* Stop DMA RX */ 359 reg = READ4(sc, OPERATION_MODE); 360 reg &= ~(MODE_SR); 361 WRITE4(sc, OPERATION_MODE, reg); 362 } 363 364 static void dwc_clear_stats(struct dwc_softc *sc) 365 { 366 uint32_t reg; 367 368 reg = READ4(sc, MMC_CONTROL); 369 reg |= (MMC_CONTROL_CNTRST); 370 WRITE4(sc, MMC_CONTROL, reg); 371 } 372 373 static void 374 dwc_harvest_stats(struct dwc_softc *sc) 375 { 376 struct ifnet *ifp; 377 378 /* We don't need to harvest too often. */ 379 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 380 return; 381 382 sc->stats_harvest_count = 0; 383 ifp = sc->ifp; 384 385 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); 386 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); 387 if_inc_counter(ifp, IFCOUNTER_IERRORS, 388 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + 389 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + 390 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + 391 READ4(sc, RXLENGTHERROR)); 392 393 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); 394 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); 395 if_inc_counter(ifp, IFCOUNTER_OERRORS, 396 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + 397 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); 398 399 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 400 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); 401 402 dwc_clear_stats(sc); 403 } 404 405 static void 406 dwc_tick(void *arg) 407 { 408 struct dwc_softc *sc; 409 struct ifnet *ifp; 410 int link_was_up; 411 412 sc = arg; 413 414 DWC_ASSERT_LOCKED(sc); 415 416 ifp = sc->ifp; 417 418 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 419 return; 420 421 /* 422 * Typical tx watchdog. If this fires it indicates that we enqueued 423 * packets for output and never got a txdone interrupt for them. Maybe 424 * it's a missed interrupt somehow, just pretend we got one. 425 */ 426 if (sc->tx_watchdog_count > 0) { 427 if (--sc->tx_watchdog_count == 0) { 428 dwc_txfinish_locked(sc); 429 } 430 } 431 432 /* Gather stats from hardware counters. */ 433 dwc_harvest_stats(sc); 434 435 /* Check the media status. */ 436 link_was_up = sc->link_is_up; 437 mii_tick(sc->mii_softc); 438 if (sc->link_is_up && !link_was_up) 439 dwc_txstart_locked(sc); 440 441 /* Schedule another check one second from now. */ 442 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 443 } 444 445 static void 446 dwc_init_locked(struct dwc_softc *sc) 447 { 448 struct ifnet *ifp = sc->ifp; 449 uint32_t reg; 450 451 DWC_ASSERT_LOCKED(sc); 452 453 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 454 return; 455 456 ifp->if_drv_flags |= IFF_DRV_RUNNING; 457 458 dwc_setup_rxfilter(sc); 459 460 /* Initializa DMA and enable transmitters */ 461 reg = READ4(sc, OPERATION_MODE); 462 reg |= (MODE_TSF | MODE_OSF | MODE_FUF); 463 reg &= ~(MODE_RSF); 464 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); 465 WRITE4(sc, OPERATION_MODE, reg); 466 467 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 468 469 /* Start DMA */ 470 reg = READ4(sc, OPERATION_MODE); 471 reg |= (MODE_ST | MODE_SR); 472 WRITE4(sc, OPERATION_MODE, reg); 473 474 /* Enable transmitters */ 475 reg = READ4(sc, MAC_CONFIGURATION); 476 reg |= (CONF_JD | CONF_ACS | CONF_BE); 477 reg |= (CONF_TE | CONF_RE); 478 WRITE4(sc, MAC_CONFIGURATION, reg); 479 480 /* 481 * Call mii_mediachg() which will call back into dwc_miibus_statchg() 482 * to set up the remaining config registers based on current media. 483 */ 484 mii_mediachg(sc->mii_softc); 485 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 486 } 487 488 static void 489 dwc_init(void *if_softc) 490 { 491 struct dwc_softc *sc = if_softc; 492 493 DWC_LOCK(sc); 494 dwc_init_locked(sc); 495 DWC_UNLOCK(sc); 496 } 497 498 inline static uint32_t 499 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) 500 { 501 uint32_t nidx; 502 503 sc->rxdesc_ring[idx].addr = (uint32_t)paddr; 504 nidx = next_rxidx(sc, idx); 505 sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \ 506 (nidx * sizeof(struct dwc_hwdesc)); 507 sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; 508 509 wmb(); 510 sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; 511 wmb(); 512 513 return (nidx); 514 } 515 516 static int 517 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) 518 { 519 struct bus_dma_segment seg; 520 int error, nsegs; 521 522 m_adj(m, ETHER_ALIGN); 523 524 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 525 m, &seg, &nsegs, 0); 526 if (error != 0) { 527 return (error); 528 } 529 530 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 531 532 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 533 BUS_DMASYNC_PREREAD); 534 535 sc->rxbuf_map[idx].mbuf = m; 536 dwc_setup_rxdesc(sc, idx, seg.ds_addr); 537 538 return (0); 539 } 540 541 static struct mbuf * 542 dwc_alloc_mbufcl(struct dwc_softc *sc) 543 { 544 struct mbuf *m; 545 546 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 547 if (m != NULL) 548 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 549 550 return (m); 551 } 552 553 static void 554 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 555 { 556 struct dwc_softc *sc; 557 struct mii_data *mii; 558 559 sc = ifp->if_softc; 560 mii = sc->mii_softc; 561 DWC_LOCK(sc); 562 mii_pollstat(mii); 563 ifmr->ifm_active = mii->mii_media_active; 564 ifmr->ifm_status = mii->mii_media_status; 565 DWC_UNLOCK(sc); 566 } 567 568 static int 569 dwc_media_change_locked(struct dwc_softc *sc) 570 { 571 572 return (mii_mediachg(sc->mii_softc)); 573 } 574 575 static int 576 dwc_media_change(struct ifnet * ifp) 577 { 578 struct dwc_softc *sc; 579 int error; 580 581 sc = ifp->if_softc; 582 583 DWC_LOCK(sc); 584 error = dwc_media_change_locked(sc); 585 DWC_UNLOCK(sc); 586 return (error); 587 } 588 589 static const uint8_t nibbletab[] = { 590 /* 0x0 0000 -> 0000 */ 0x0, 591 /* 0x1 0001 -> 1000 */ 0x8, 592 /* 0x2 0010 -> 0100 */ 0x4, 593 /* 0x3 0011 -> 1100 */ 0xc, 594 /* 0x4 0100 -> 0010 */ 0x2, 595 /* 0x5 0101 -> 1010 */ 0xa, 596 /* 0x6 0110 -> 0110 */ 0x6, 597 /* 0x7 0111 -> 1110 */ 0xe, 598 /* 0x8 1000 -> 0001 */ 0x1, 599 /* 0x9 1001 -> 1001 */ 0x9, 600 /* 0xa 1010 -> 0101 */ 0x5, 601 /* 0xb 1011 -> 1101 */ 0xd, 602 /* 0xc 1100 -> 0011 */ 0x3, 603 /* 0xd 1101 -> 1011 */ 0xb, 604 /* 0xe 1110 -> 0111 */ 0x7, 605 /* 0xf 1111 -> 1111 */ 0xf, }; 606 607 static uint8_t 608 bitreverse(uint8_t x) 609 { 610 611 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; 612 } 613 614 static void 615 dwc_setup_rxfilter(struct dwc_softc *sc) 616 { 617 struct ifmultiaddr *ifma; 618 struct ifnet *ifp; 619 uint8_t *eaddr, val; 620 uint32_t crc, ffval, hashbit, hashreg, hi, lo, reg; 621 622 DWC_ASSERT_LOCKED(sc); 623 624 ifp = sc->ifp; 625 626 /* 627 * Set the multicast (group) filter hash. 628 */ 629 if ((ifp->if_flags & IFF_ALLMULTI)) 630 ffval = (FRAME_FILTER_PM); 631 else { 632 ffval = (FRAME_FILTER_HMC); 633 if_maddr_rlock(ifp); 634 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 635 if (ifma->ifma_addr->sa_family != AF_LINK) 636 continue; 637 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 638 ifma->ifma_addr), ETHER_ADDR_LEN); 639 640 /* Take lower 8 bits and reverse it */ 641 val = bitreverse(~crc & 0xff); 642 hashreg = (val >> 5); 643 hashbit = (val & 31); 644 645 reg = READ4(sc, HASH_TABLE_REG(hashreg)); 646 reg |= (1 << hashbit); 647 WRITE4(sc, HASH_TABLE_REG(hashreg), reg); 648 } 649 if_maddr_runlock(ifp); 650 } 651 652 /* 653 * Set the individual address filter hash. 654 */ 655 if (ifp->if_flags & IFF_PROMISC) 656 ffval |= (FRAME_FILTER_PR); 657 658 /* 659 * Set the primary address. 660 */ 661 eaddr = IF_LLADDR(ifp); 662 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 663 (eaddr[3] << 24); 664 hi = eaddr[4] | (eaddr[5] << 8); 665 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); 666 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); 667 WRITE4(sc, MAC_FRAME_FILTER, ffval); 668 } 669 670 static int 671 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 672 { 673 struct dwc_softc *sc; 674 struct mii_data *mii; 675 struct ifreq *ifr; 676 int mask, error; 677 678 sc = ifp->if_softc; 679 ifr = (struct ifreq *)data; 680 681 error = 0; 682 switch (cmd) { 683 case SIOCSIFFLAGS: 684 DWC_LOCK(sc); 685 if (ifp->if_flags & IFF_UP) { 686 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 687 if ((ifp->if_flags ^ sc->if_flags) & 688 (IFF_PROMISC | IFF_ALLMULTI)) 689 dwc_setup_rxfilter(sc); 690 } else { 691 if (!sc->is_detaching) 692 dwc_init_locked(sc); 693 } 694 } else { 695 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 696 dwc_stop_locked(sc); 697 } 698 sc->if_flags = ifp->if_flags; 699 DWC_UNLOCK(sc); 700 break; 701 case SIOCADDMULTI: 702 case SIOCDELMULTI: 703 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 704 DWC_LOCK(sc); 705 dwc_setup_rxfilter(sc); 706 DWC_UNLOCK(sc); 707 } 708 break; 709 case SIOCSIFMEDIA: 710 case SIOCGIFMEDIA: 711 mii = sc->mii_softc; 712 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 713 break; 714 case SIOCSIFCAP: 715 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 716 if (mask & IFCAP_VLAN_MTU) { 717 /* No work to do except acknowledge the change took */ 718 ifp->if_capenable ^= IFCAP_VLAN_MTU; 719 } 720 break; 721 722 default: 723 error = ether_ioctl(ifp, cmd, data); 724 break; 725 } 726 727 return (error); 728 } 729 730 static void 731 dwc_txfinish_locked(struct dwc_softc *sc) 732 { 733 struct dwc_bufmap *bmap; 734 struct dwc_hwdesc *desc; 735 struct ifnet *ifp; 736 737 DWC_ASSERT_LOCKED(sc); 738 739 ifp = sc->ifp; 740 while (sc->tx_idx_tail != sc->tx_idx_head) { 741 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 742 if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) 743 break; 744 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 745 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 746 BUS_DMASYNC_POSTWRITE); 747 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 748 m_freem(bmap->mbuf); 749 bmap->mbuf = NULL; 750 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 751 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 752 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 753 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 754 } 755 756 /* If there are no buffers outstanding, muzzle the watchdog. */ 757 if (sc->tx_idx_tail == sc->tx_idx_head) { 758 sc->tx_watchdog_count = 0; 759 } 760 } 761 762 static void 763 dwc_rxfinish_locked(struct dwc_softc *sc) 764 { 765 struct ifnet *ifp; 766 struct mbuf *m0; 767 struct mbuf *m; 768 int error, idx, len; 769 uint32_t rdes0; 770 771 ifp = sc->ifp; 772 773 for (;;) { 774 idx = sc->rx_idx; 775 776 rdes0 = sc->rxdesc_ring[idx].tdes0; 777 if ((rdes0 & DDESC_RDES0_OWN) != 0) 778 break; 779 780 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 781 BUS_DMASYNC_POSTREAD); 782 bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); 783 784 len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; 785 if (len != 0) { 786 m = sc->rxbuf_map[idx].mbuf; 787 m->m_pkthdr.rcvif = ifp; 788 m->m_pkthdr.len = len; 789 m->m_len = len; 790 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 791 792 DWC_UNLOCK(sc); 793 (*ifp->if_input)(ifp, m); 794 DWC_LOCK(sc); 795 } else { 796 /* XXX Zero-length packet ? */ 797 } 798 799 if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) { 800 if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { 801 /* 802 * XXX Now what? 803 * We've got a hole in the rx ring. 804 */ 805 } 806 } else 807 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 808 809 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 810 } 811 } 812 813 static void 814 dwc_intr(void *arg) 815 { 816 struct dwc_softc *sc; 817 uint32_t reg; 818 819 sc = arg; 820 821 DWC_LOCK(sc); 822 823 reg = READ4(sc, INTERRUPT_STATUS); 824 if (reg) { 825 mii_mediachg(sc->mii_softc); 826 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); 827 } 828 829 reg = READ4(sc, DMA_STATUS); 830 if (reg & DMA_STATUS_NIS) { 831 if (reg & DMA_STATUS_RI) 832 dwc_rxfinish_locked(sc); 833 834 if (reg & DMA_STATUS_TI) { 835 dwc_txfinish_locked(sc); 836 dwc_txstart_locked(sc); 837 } 838 } 839 840 if (reg & DMA_STATUS_AIS) { 841 if (reg & DMA_STATUS_FBI) { 842 /* Fatal bus error */ 843 device_printf(sc->dev, 844 "Ethernet DMA error, restarting controller.\n"); 845 dwc_stop_locked(sc); 846 dwc_init_locked(sc); 847 } 848 } 849 850 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 851 DWC_UNLOCK(sc); 852 } 853 854 static int 855 setup_dma(struct dwc_softc *sc) 856 { 857 struct mbuf *m; 858 int error; 859 int nidx; 860 int idx; 861 862 /* 863 * Set up TX descriptor ring, descriptors, and dma maps. 864 */ 865 error = bus_dma_tag_create( 866 bus_get_dma_tag(sc->dev), /* Parent tag. */ 867 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 868 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 869 BUS_SPACE_MAXADDR, /* highaddr */ 870 NULL, NULL, /* filter, filterarg */ 871 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 872 TX_DESC_SIZE, /* maxsegsize */ 873 0, /* flags */ 874 NULL, NULL, /* lockfunc, lockarg */ 875 &sc->txdesc_tag); 876 if (error != 0) { 877 device_printf(sc->dev, 878 "could not create TX ring DMA tag.\n"); 879 goto out; 880 } 881 882 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 883 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 884 &sc->txdesc_map); 885 if (error != 0) { 886 device_printf(sc->dev, 887 "could not allocate TX descriptor ring.\n"); 888 goto out; 889 } 890 891 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, 892 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, 893 &sc->txdesc_ring_paddr, 0); 894 if (error != 0) { 895 device_printf(sc->dev, 896 "could not load TX descriptor ring map.\n"); 897 goto out; 898 } 899 900 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 901 nidx = next_txidx(sc, idx); 902 sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + 903 (nidx * sizeof(struct dwc_hwdesc)); 904 } 905 906 error = bus_dma_tag_create( 907 bus_get_dma_tag(sc->dev), /* Parent tag. */ 908 1, 0, /* alignment, boundary */ 909 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 910 BUS_SPACE_MAXADDR, /* highaddr */ 911 NULL, NULL, /* filter, filterarg */ 912 MCLBYTES, 1, /* maxsize, nsegments */ 913 MCLBYTES, /* maxsegsize */ 914 0, /* flags */ 915 NULL, NULL, /* lockfunc, lockarg */ 916 &sc->txbuf_tag); 917 if (error != 0) { 918 device_printf(sc->dev, 919 "could not create TX ring DMA tag.\n"); 920 goto out; 921 } 922 923 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 924 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, 925 &sc->txbuf_map[idx].map); 926 if (error != 0) { 927 device_printf(sc->dev, 928 "could not create TX buffer DMA map.\n"); 929 goto out; 930 } 931 dwc_setup_txdesc(sc, idx, 0, 0); 932 } 933 934 /* 935 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 936 */ 937 error = bus_dma_tag_create( 938 bus_get_dma_tag(sc->dev), /* Parent tag. */ 939 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 940 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 941 BUS_SPACE_MAXADDR, /* highaddr */ 942 NULL, NULL, /* filter, filterarg */ 943 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 944 RX_DESC_SIZE, /* maxsegsize */ 945 0, /* flags */ 946 NULL, NULL, /* lockfunc, lockarg */ 947 &sc->rxdesc_tag); 948 if (error != 0) { 949 device_printf(sc->dev, 950 "could not create RX ring DMA tag.\n"); 951 goto out; 952 } 953 954 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 955 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 956 &sc->rxdesc_map); 957 if (error != 0) { 958 device_printf(sc->dev, 959 "could not allocate RX descriptor ring.\n"); 960 goto out; 961 } 962 963 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, 964 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, 965 &sc->rxdesc_ring_paddr, 0); 966 if (error != 0) { 967 device_printf(sc->dev, 968 "could not load RX descriptor ring map.\n"); 969 goto out; 970 } 971 972 error = bus_dma_tag_create( 973 bus_get_dma_tag(sc->dev), /* Parent tag. */ 974 1, 0, /* alignment, boundary */ 975 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 976 BUS_SPACE_MAXADDR, /* highaddr */ 977 NULL, NULL, /* filter, filterarg */ 978 MCLBYTES, 1, /* maxsize, nsegments */ 979 MCLBYTES, /* maxsegsize */ 980 0, /* flags */ 981 NULL, NULL, /* lockfunc, lockarg */ 982 &sc->rxbuf_tag); 983 if (error != 0) { 984 device_printf(sc->dev, 985 "could not create RX buf DMA tag.\n"); 986 goto out; 987 } 988 989 for (idx = 0; idx < RX_DESC_COUNT; idx++) { 990 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, 991 &sc->rxbuf_map[idx].map); 992 if (error != 0) { 993 device_printf(sc->dev, 994 "could not create RX buffer DMA map.\n"); 995 goto out; 996 } 997 if ((m = dwc_alloc_mbufcl(sc)) == NULL) { 998 device_printf(sc->dev, "Could not alloc mbuf\n"); 999 error = ENOMEM; 1000 goto out; 1001 } 1002 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { 1003 device_printf(sc->dev, 1004 "could not create new RX buffer.\n"); 1005 goto out; 1006 } 1007 } 1008 1009 out: 1010 if (error != 0) 1011 return (ENXIO); 1012 1013 return (0); 1014 } 1015 1016 static int 1017 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) 1018 { 1019 uint32_t hi, lo, rnd; 1020 1021 /* 1022 * Try to recover a MAC address from the running hardware. If there's 1023 * something non-zero there, assume the bootloader did the right thing 1024 * and just use it. 1025 * 1026 * Otherwise, set the address to a convenient locally assigned address, 1027 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 1028 * assigned bit set, and the broadcast/multicast bit clear. 1029 */ 1030 lo = READ4(sc, MAC_ADDRESS_LOW(0)); 1031 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; 1032 if ((lo != 0xffffffff) || (hi != 0xffff)) { 1033 hwaddr[0] = (lo >> 0) & 0xff; 1034 hwaddr[1] = (lo >> 8) & 0xff; 1035 hwaddr[2] = (lo >> 16) & 0xff; 1036 hwaddr[3] = (lo >> 24) & 0xff; 1037 hwaddr[4] = (hi >> 0) & 0xff; 1038 hwaddr[5] = (hi >> 8) & 0xff; 1039 } else { 1040 rnd = arc4random() & 0x00ffffff; 1041 hwaddr[0] = 'b'; 1042 hwaddr[1] = 's'; 1043 hwaddr[2] = 'd'; 1044 hwaddr[3] = rnd >> 16; 1045 hwaddr[4] = rnd >> 8; 1046 hwaddr[5] = rnd >> 0; 1047 } 1048 1049 return (0); 1050 } 1051 1052 static int 1053 dwc_probe(device_t dev) 1054 { 1055 1056 if (!ofw_bus_status_okay(dev)) 1057 return (ENXIO); 1058 1059 if (!ofw_bus_is_compatible(dev, "snps,dwmac")) 1060 return (ENXIO); 1061 1062 device_set_desc(dev, "Gigabit Ethernet Controller"); 1063 return (BUS_PROBE_DEFAULT); 1064 } 1065 1066 static int 1067 dwc_attach(device_t dev) 1068 { 1069 uint8_t macaddr[ETHER_ADDR_LEN]; 1070 struct dwc_softc *sc; 1071 struct ifnet *ifp; 1072 int error, i; 1073 uint32_t reg; 1074 1075 sc = device_get_softc(dev); 1076 sc->dev = dev; 1077 sc->mii_clk = MII_CLK_VAL; 1078 sc->rx_idx = 0; 1079 1080 sc->txcount = TX_DESC_COUNT; 1081 1082 if (bus_alloc_resources(dev, dwc_spec, sc->res)) { 1083 device_printf(dev, "could not allocate resources\n"); 1084 return (ENXIO); 1085 } 1086 1087 /* Memory interface */ 1088 sc->bst = rman_get_bustag(sc->res[0]); 1089 sc->bsh = rman_get_bushandle(sc->res[0]); 1090 1091 /* Read MAC before reset */ 1092 if (dwc_get_hwaddr(sc, macaddr)) { 1093 device_printf(sc->dev, "can't get mac\n"); 1094 return (ENXIO); 1095 } 1096 1097 /* Reset */ 1098 reg = READ4(sc, BUS_MODE); 1099 reg |= (BUS_MODE_SWR); 1100 WRITE4(sc, BUS_MODE, reg); 1101 1102 for (i = 0; i < MAC_RESET_TIMEOUT; i++) { 1103 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 1104 break; 1105 DELAY(10); 1106 } 1107 if (i >= MAC_RESET_TIMEOUT) { 1108 device_printf(sc->dev, "Can't reset DWC.\n"); 1109 return (ENXIO); 1110 } 1111 1112 reg = READ4(sc, BUS_MODE); 1113 reg |= (BUS_MODE_EIGHTXPBL); 1114 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); 1115 WRITE4(sc, BUS_MODE, reg); 1116 1117 /* 1118 * DMA must be stop while changing descriptor list addresses. 1119 */ 1120 reg = READ4(sc, OPERATION_MODE); 1121 reg &= ~(MODE_ST | MODE_SR); 1122 WRITE4(sc, OPERATION_MODE, reg); 1123 1124 if (setup_dma(sc)) 1125 return (ENXIO); 1126 1127 /* Setup addresses */ 1128 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 1129 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 1130 1131 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), 1132 MTX_NETWORK_LOCK, MTX_DEF); 1133 1134 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); 1135 1136 /* Setup interrupt handler. */ 1137 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 1138 NULL, dwc_intr, sc, &sc->intr_cookie); 1139 if (error != 0) { 1140 device_printf(dev, "could not setup interrupt handler.\n"); 1141 return (ENXIO); 1142 } 1143 1144 /* Set up the ethernet interface. */ 1145 sc->ifp = ifp = if_alloc(IFT_ETHER); 1146 1147 ifp->if_softc = sc; 1148 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1149 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1150 ifp->if_capabilities = IFCAP_VLAN_MTU; 1151 ifp->if_capenable = ifp->if_capabilities; 1152 ifp->if_start = dwc_txstart; 1153 ifp->if_ioctl = dwc_ioctl; 1154 ifp->if_init = dwc_init; 1155 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1156 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1157 IFQ_SET_READY(&ifp->if_snd); 1158 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1159 1160 /* Attach the mii driver. */ 1161 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, 1162 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 1163 MII_OFFSET_ANY, 0); 1164 1165 if (error != 0) { 1166 device_printf(dev, "PHY attach failed\n"); 1167 return (ENXIO); 1168 } 1169 sc->mii_softc = device_get_softc(sc->miibus); 1170 1171 /* All ready to run, attach the ethernet interface. */ 1172 ether_ifattach(ifp, macaddr); 1173 sc->is_attached = true; 1174 1175 return (0); 1176 } 1177 1178 static int 1179 dwc_miibus_read_reg(device_t dev, int phy, int reg) 1180 { 1181 struct dwc_softc *sc; 1182 uint16_t mii; 1183 size_t cnt; 1184 int rv = 0; 1185 1186 sc = device_get_softc(dev); 1187 1188 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1189 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1190 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1191 | GMII_ADDRESS_GB; /* Busy flag */ 1192 1193 WRITE4(sc, GMII_ADDRESS, mii); 1194 1195 for (cnt = 0; cnt < 1000; cnt++) { 1196 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1197 rv = READ4(sc, GMII_DATA); 1198 break; 1199 } 1200 DELAY(10); 1201 } 1202 1203 return rv; 1204 } 1205 1206 static int 1207 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) 1208 { 1209 struct dwc_softc *sc; 1210 uint16_t mii; 1211 size_t cnt; 1212 1213 sc = device_get_softc(dev); 1214 1215 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1216 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1217 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1218 | GMII_ADDRESS_GB | GMII_ADDRESS_GW; 1219 1220 WRITE4(sc, GMII_DATA, val); 1221 WRITE4(sc, GMII_ADDRESS, mii); 1222 1223 for (cnt = 0; cnt < 1000; cnt++) { 1224 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1225 break; 1226 } 1227 DELAY(10); 1228 } 1229 1230 return (0); 1231 } 1232 1233 static void 1234 dwc_miibus_statchg(device_t dev) 1235 { 1236 struct dwc_softc *sc; 1237 struct mii_data *mii; 1238 uint32_t reg; 1239 1240 /* 1241 * Called by the MII bus driver when the PHY establishes 1242 * link to set the MAC interface registers. 1243 */ 1244 1245 sc = device_get_softc(dev); 1246 1247 DWC_ASSERT_LOCKED(sc); 1248 1249 mii = sc->mii_softc; 1250 1251 if (mii->mii_media_status & IFM_ACTIVE) 1252 sc->link_is_up = true; 1253 else 1254 sc->link_is_up = false; 1255 1256 reg = READ4(sc, MAC_CONFIGURATION); 1257 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1258 case IFM_1000_T: 1259 case IFM_1000_SX: 1260 reg &= ~(CONF_FES | CONF_PS); 1261 break; 1262 case IFM_100_TX: 1263 reg |= (CONF_FES | CONF_PS); 1264 break; 1265 case IFM_10_T: 1266 reg &= ~(CONF_FES); 1267 reg |= (CONF_PS); 1268 break; 1269 case IFM_NONE: 1270 sc->link_is_up = false; 1271 return; 1272 default: 1273 sc->link_is_up = false; 1274 device_printf(dev, "Unsupported media %u\n", 1275 IFM_SUBTYPE(mii->mii_media_active)); 1276 return; 1277 } 1278 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1279 reg |= (CONF_DM); 1280 else 1281 reg &= ~(CONF_DM); 1282 WRITE4(sc, MAC_CONFIGURATION, reg); 1283 } 1284 1285 static device_method_t dwc_methods[] = { 1286 DEVMETHOD(device_probe, dwc_probe), 1287 DEVMETHOD(device_attach, dwc_attach), 1288 1289 /* MII Interface */ 1290 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), 1291 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), 1292 DEVMETHOD(miibus_statchg, dwc_miibus_statchg), 1293 1294 { 0, 0 } 1295 }; 1296 1297 static driver_t dwc_driver = { 1298 "dwc", 1299 dwc_methods, 1300 sizeof(struct dwc_softc), 1301 }; 1302 1303 static devclass_t dwc_devclass; 1304 1305 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); 1306 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); 1307 1308 MODULE_DEPEND(dwc, ether, 1, 1, 1); 1309 MODULE_DEPEND(dwc, miibus, 1, 1, 1); 1310