1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Ethernet media access controller (EMAC) 33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 * 35 * EMAC is an instance of the Synopsys DesignWare 3504-0 36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/malloc.h> 48 #include <sys/rman.h> 49 #include <sys/endian.h> 50 #include <sys/lock.h> 51 #include <sys/mbuf.h> 52 #include <sys/mutex.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 #include <sys/sysctl.h> 56 57 #include <dev/fdt/fdt_common.h> 58 #include <dev/ofw/openfirm.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 62 #include <net/bpf.h> 63 #include <net/if.h> 64 #include <net/ethernet.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 #include <net/if_var.h> 69 #include <net/if_vlan_var.h> 70 71 #include <machine/bus.h> 72 #include <machine/fdt.h> 73 74 #include <dev/mii/mii.h> 75 #include <dev/mii/miivar.h> 76 #include "miibus_if.h" 77 78 #define READ4(_sc, _reg) \ 79 bus_read_4((_sc)->res[0], _reg) 80 #define WRITE4(_sc, _reg, _val) \ 81 bus_write_4((_sc)->res[0], _reg, _val) 82 83 #define MAC_RESET_TIMEOUT 100 84 #define WATCHDOG_TIMEOUT_SECS 5 85 #define STATS_HARVEST_INTERVAL 2 86 #define MII_CLK_VAL 2 87 88 #include <dev/dwc/if_dwc.h> 89 90 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) 91 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 92 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 93 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 94 95 #define DDESC_TDES0_OWN (1 << 31) 96 #define DDESC_TDES0_TXINT (1 << 30) 97 #define DDESC_TDES0_TXLAST (1 << 29) 98 #define DDESC_TDES0_TXFIRST (1 << 28) 99 #define DDESC_TDES0_TXCRCDIS (1 << 27) 100 #define DDESC_TDES0_TXRINGEND (1 << 21) 101 #define DDESC_TDES0_TXCHAIN (1 << 20) 102 103 #define DDESC_RDES0_OWN (1 << 31) 104 #define DDESC_RDES0_FL_MASK 0x3fff 105 #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ 106 #define DDESC_RDES1_CHAINED (1 << 14) 107 108 struct dwc_bufmap { 109 bus_dmamap_t map; 110 struct mbuf *mbuf; 111 }; 112 113 /* 114 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 115 * layout, but the bits in the flags field have different meanings. 116 */ 117 struct dwc_hwdesc 118 { 119 uint32_t tdes0; 120 uint32_t tdes1; 121 uint32_t addr; /* pointer to buffer data */ 122 uint32_t addr_next; /* link to next descriptor */ 123 }; 124 125 /* 126 * Driver data and defines. 127 */ 128 #define RX_DESC_COUNT 1024 129 #define RX_DESC_SIZE (sizeof(struct dwc_hwdesc) * RX_DESC_COUNT) 130 #define TX_DESC_COUNT 1024 131 #define TX_DESC_SIZE (sizeof(struct dwc_hwdesc) * TX_DESC_COUNT) 132 133 /* 134 * The hardware imposes alignment restrictions on various objects involved in 135 * DMA transfers. These values are expressed in bytes (not bits). 136 */ 137 #define DWC_DESC_RING_ALIGN 2048 138 139 struct dwc_softc { 140 struct resource *res[2]; 141 bus_space_tag_t bst; 142 bus_space_handle_t bsh; 143 device_t dev; 144 int mii_clk; 145 device_t miibus; 146 struct mii_data * mii_softc; 147 struct ifnet *ifp; 148 int if_flags; 149 struct mtx mtx; 150 void * intr_cookie; 151 struct callout dwc_callout; 152 uint8_t phy_conn_type; 153 uint8_t mactype; 154 boolean_t link_is_up; 155 boolean_t is_attached; 156 boolean_t is_detaching; 157 int tx_watchdog_count; 158 int stats_harvest_count; 159 160 /* RX */ 161 bus_dma_tag_t rxdesc_tag; 162 bus_dmamap_t rxdesc_map; 163 struct dwc_hwdesc *rxdesc_ring; 164 bus_addr_t rxdesc_ring_paddr; 165 bus_dma_tag_t rxbuf_tag; 166 struct dwc_bufmap rxbuf_map[RX_DESC_COUNT]; 167 uint32_t rx_idx; 168 169 /* TX */ 170 bus_dma_tag_t txdesc_tag; 171 bus_dmamap_t txdesc_map; 172 struct dwc_hwdesc *txdesc_ring; 173 bus_addr_t txdesc_ring_paddr; 174 bus_dma_tag_t txbuf_tag; 175 struct dwc_bufmap txbuf_map[RX_DESC_COUNT]; 176 uint32_t tx_idx_head; 177 uint32_t tx_idx_tail; 178 int txcount; 179 }; 180 181 static struct resource_spec dwc_spec[] = { 182 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 183 { SYS_RES_IRQ, 0, RF_ACTIVE }, 184 { -1, 0 } 185 }; 186 187 static void dwc_txfinish_locked(struct dwc_softc *sc); 188 static void dwc_rxfinish_locked(struct dwc_softc *sc); 189 static void dwc_stop_locked(struct dwc_softc *sc); 190 static void dwc_setup_rxfilter(struct dwc_softc *sc); 191 192 static inline uint32_t 193 next_rxidx(struct dwc_softc *sc, uint32_t curidx) 194 { 195 196 return ((curidx + 1) % RX_DESC_COUNT); 197 } 198 199 static inline uint32_t 200 next_txidx(struct dwc_softc *sc, uint32_t curidx) 201 { 202 203 return ((curidx + 1) % TX_DESC_COUNT); 204 } 205 206 static void 207 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 208 { 209 210 if (error != 0) 211 return; 212 *(bus_addr_t *)arg = segs[0].ds_addr; 213 } 214 215 inline static uint32_t 216 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, 217 uint32_t len) 218 { 219 uint32_t flags; 220 uint32_t nidx; 221 222 nidx = next_txidx(sc, idx); 223 224 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 225 if (paddr == 0 || len == 0) { 226 flags = 0; 227 --sc->txcount; 228 } else { 229 flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST 230 | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT; 231 ++sc->txcount; 232 } 233 234 sc->txdesc_ring[idx].addr = (uint32_t)(paddr); 235 sc->txdesc_ring[idx].tdes0 = flags; 236 sc->txdesc_ring[idx].tdes1 = len; 237 238 if (paddr && len) { 239 wmb(); 240 sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN; 241 wmb(); 242 } 243 244 return (nidx); 245 } 246 247 static int 248 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) 249 { 250 struct bus_dma_segment seg; 251 int error, nsegs; 252 struct mbuf * m; 253 254 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 255 return (ENOMEM); 256 *mp = m; 257 258 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 259 m, &seg, &nsegs, 0); 260 if (error != 0) { 261 return (ENOMEM); 262 } 263 264 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 265 266 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 267 BUS_DMASYNC_PREWRITE); 268 269 sc->txbuf_map[idx].mbuf = m; 270 271 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 272 273 return (0); 274 } 275 276 static void 277 dwc_txstart_locked(struct dwc_softc *sc) 278 { 279 struct ifnet *ifp; 280 struct mbuf *m; 281 int enqueued; 282 283 DWC_ASSERT_LOCKED(sc); 284 285 if (!sc->link_is_up) 286 return; 287 288 ifp = sc->ifp; 289 290 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 291 return; 292 } 293 294 enqueued = 0; 295 296 for (;;) { 297 if (sc->txcount == (TX_DESC_COUNT-1)) { 298 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 299 break; 300 } 301 302 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 303 if (m == NULL) 304 break; 305 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 306 IFQ_DRV_PREPEND(&ifp->if_snd, m); 307 break; 308 } 309 BPF_MTAP(ifp, m); 310 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 311 ++enqueued; 312 } 313 314 if (enqueued != 0) { 315 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 316 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 317 } 318 } 319 320 static void 321 dwc_txstart(struct ifnet *ifp) 322 { 323 struct dwc_softc *sc = ifp->if_softc; 324 325 DWC_LOCK(sc); 326 dwc_txstart_locked(sc); 327 DWC_UNLOCK(sc); 328 } 329 330 static void 331 dwc_stop_locked(struct dwc_softc *sc) 332 { 333 struct ifnet *ifp; 334 int reg; 335 336 DWC_ASSERT_LOCKED(sc); 337 338 ifp = sc->ifp; 339 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 340 sc->tx_watchdog_count = 0; 341 sc->stats_harvest_count = 0; 342 343 callout_stop(&sc->dwc_callout); 344 345 /* Stop DMA TX */ 346 reg = READ4(sc, OPERATION_MODE); 347 reg &= ~(MODE_ST); 348 WRITE4(sc, OPERATION_MODE, reg); 349 350 /* Flush TX */ 351 reg = READ4(sc, OPERATION_MODE); 352 reg |= (MODE_FTF); 353 WRITE4(sc, OPERATION_MODE, reg); 354 355 /* Stop transmitters */ 356 reg = READ4(sc, MAC_CONFIGURATION); 357 reg &= ~(CONF_TE | CONF_RE); 358 WRITE4(sc, MAC_CONFIGURATION, reg); 359 360 /* Stop DMA RX */ 361 reg = READ4(sc, OPERATION_MODE); 362 reg &= ~(MODE_SR); 363 WRITE4(sc, OPERATION_MODE, reg); 364 } 365 366 static void dwc_clear_stats(struct dwc_softc *sc) 367 { 368 int reg; 369 370 reg = READ4(sc, MMC_CONTROL); 371 reg |= (MMC_CONTROL_CNTRST); 372 WRITE4(sc, MMC_CONTROL, reg); 373 } 374 375 static void 376 dwc_harvest_stats(struct dwc_softc *sc) 377 { 378 struct ifnet *ifp; 379 380 /* We don't need to harvest too often. */ 381 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 382 return; 383 384 sc->stats_harvest_count = 0; 385 ifp = sc->ifp; 386 387 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); 388 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); 389 if_inc_counter(ifp, IFCOUNTER_IERRORS, 390 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + 391 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + 392 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + 393 READ4(sc, RXLENGTHERROR)); 394 395 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); 396 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); 397 if_inc_counter(ifp, IFCOUNTER_OERRORS, 398 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + 399 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); 400 401 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 402 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); 403 404 dwc_clear_stats(sc); 405 } 406 407 static void 408 dwc_tick(void *arg) 409 { 410 struct dwc_softc *sc; 411 struct ifnet *ifp; 412 int link_was_up; 413 414 sc = arg; 415 416 DWC_ASSERT_LOCKED(sc); 417 418 ifp = sc->ifp; 419 420 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 421 return; 422 423 /* 424 * Typical tx watchdog. If this fires it indicates that we enqueued 425 * packets for output and never got a txdone interrupt for them. Maybe 426 * it's a missed interrupt somehow, just pretend we got one. 427 */ 428 if (sc->tx_watchdog_count > 0) { 429 if (--sc->tx_watchdog_count == 0) { 430 dwc_txfinish_locked(sc); 431 } 432 } 433 434 /* Gather stats from hardware counters. */ 435 dwc_harvest_stats(sc); 436 437 /* Check the media status. */ 438 link_was_up = sc->link_is_up; 439 mii_tick(sc->mii_softc); 440 if (sc->link_is_up && !link_was_up) 441 dwc_txstart_locked(sc); 442 443 /* Schedule another check one second from now. */ 444 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 445 } 446 447 static void 448 dwc_init_locked(struct dwc_softc *sc) 449 { 450 struct ifnet *ifp = sc->ifp; 451 int reg; 452 453 DWC_ASSERT_LOCKED(sc); 454 455 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 456 return; 457 458 ifp->if_drv_flags |= IFF_DRV_RUNNING; 459 460 dwc_setup_rxfilter(sc); 461 462 /* Initializa DMA and enable transmitters */ 463 reg = READ4(sc, OPERATION_MODE); 464 reg |= (MODE_TSF | MODE_OSF | MODE_FUF); 465 reg &= ~(MODE_RSF); 466 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); 467 WRITE4(sc, OPERATION_MODE, reg); 468 469 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 470 471 /* Start DMA */ 472 reg = READ4(sc, OPERATION_MODE); 473 reg |= (MODE_ST | MODE_SR); 474 WRITE4(sc, OPERATION_MODE, reg); 475 476 /* Enable transmitters */ 477 reg = READ4(sc, MAC_CONFIGURATION); 478 reg |= (CONF_JD | CONF_ACS | CONF_BE); 479 reg |= (CONF_TE | CONF_RE); 480 WRITE4(sc, MAC_CONFIGURATION, reg); 481 482 /* 483 * Call mii_mediachg() which will call back into dwc_miibus_statchg() 484 * to set up the remaining config registers based on current media. 485 */ 486 mii_mediachg(sc->mii_softc); 487 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 488 } 489 490 static void 491 dwc_init(void *if_softc) 492 { 493 struct dwc_softc *sc = if_softc; 494 495 DWC_LOCK(sc); 496 dwc_init_locked(sc); 497 DWC_UNLOCK(sc); 498 } 499 500 inline static uint32_t 501 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) 502 { 503 uint32_t nidx; 504 505 sc->rxdesc_ring[idx].addr = (uint32_t)paddr; 506 nidx = next_rxidx(sc, idx); 507 sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \ 508 (nidx * sizeof(struct dwc_hwdesc)); 509 sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; 510 511 wmb(); 512 sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; 513 wmb(); 514 515 return (nidx); 516 } 517 518 static int 519 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) 520 { 521 struct bus_dma_segment seg; 522 int error, nsegs; 523 524 m_adj(m, ETHER_ALIGN); 525 526 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 527 m, &seg, &nsegs, 0); 528 if (error != 0) { 529 return (error); 530 } 531 532 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 533 534 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 535 BUS_DMASYNC_PREREAD); 536 537 sc->rxbuf_map[idx].mbuf = m; 538 dwc_setup_rxdesc(sc, idx, seg.ds_addr); 539 540 return (0); 541 } 542 543 static struct mbuf * 544 dwc_alloc_mbufcl(struct dwc_softc *sc) 545 { 546 struct mbuf *m; 547 548 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 549 if (m != NULL) 550 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 551 552 return (m); 553 } 554 555 static void 556 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 557 { 558 struct dwc_softc *sc; 559 struct mii_data *mii; 560 561 sc = ifp->if_softc; 562 mii = sc->mii_softc; 563 DWC_LOCK(sc); 564 mii_pollstat(mii); 565 ifmr->ifm_active = mii->mii_media_active; 566 ifmr->ifm_status = mii->mii_media_status; 567 DWC_UNLOCK(sc); 568 } 569 570 static int 571 dwc_media_change_locked(struct dwc_softc *sc) 572 { 573 574 return (mii_mediachg(sc->mii_softc)); 575 } 576 577 static int 578 dwc_media_change(struct ifnet * ifp) 579 { 580 struct dwc_softc *sc; 581 int error; 582 583 sc = ifp->if_softc; 584 585 DWC_LOCK(sc); 586 error = dwc_media_change_locked(sc); 587 DWC_UNLOCK(sc); 588 return (error); 589 } 590 591 static const uint8_t nibbletab[] = { 592 /* 0x0 0000 -> 0000 */ 0x0, 593 /* 0x1 0001 -> 1000 */ 0x8, 594 /* 0x2 0010 -> 0100 */ 0x4, 595 /* 0x3 0011 -> 1100 */ 0xc, 596 /* 0x4 0100 -> 0010 */ 0x2, 597 /* 0x5 0101 -> 1010 */ 0xa, 598 /* 0x6 0110 -> 0110 */ 0x6, 599 /* 0x7 0111 -> 1110 */ 0xe, 600 /* 0x8 1000 -> 0001 */ 0x1, 601 /* 0x9 1001 -> 1001 */ 0x9, 602 /* 0xa 1010 -> 0101 */ 0x5, 603 /* 0xb 1011 -> 1101 */ 0xd, 604 /* 0xc 1100 -> 0011 */ 0x3, 605 /* 0xd 1101 -> 1011 */ 0xb, 606 /* 0xe 1110 -> 0111 */ 0x7, 607 /* 0xf 1111 -> 1111 */ 0xf, }; 608 609 static uint8_t 610 bitreverse(uint8_t x) 611 { 612 613 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; 614 } 615 616 static void 617 dwc_setup_rxfilter(struct dwc_softc *sc) 618 { 619 struct ifmultiaddr *ifma; 620 struct ifnet *ifp; 621 uint8_t *eaddr; 622 uint32_t crc; 623 uint8_t val; 624 int hashbit; 625 int hashreg; 626 int ffval; 627 int reg; 628 int lo; 629 int hi; 630 631 DWC_ASSERT_LOCKED(sc); 632 633 ifp = sc->ifp; 634 635 /* 636 * Set the multicast (group) filter hash. 637 */ 638 if ((ifp->if_flags & IFF_ALLMULTI)) 639 ffval = (FRAME_FILTER_PM); 640 else { 641 ffval = (FRAME_FILTER_HMC); 642 if_maddr_rlock(ifp); 643 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 644 if (ifma->ifma_addr->sa_family != AF_LINK) 645 continue; 646 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 647 ifma->ifma_addr), ETHER_ADDR_LEN); 648 649 /* Take lower 8 bits and reverse it */ 650 val = bitreverse(~crc & 0xff); 651 hashreg = (val >> 5); 652 hashbit = (val & 31); 653 654 reg = READ4(sc, HASH_TABLE_REG(hashreg)); 655 reg |= (1 << hashbit); 656 WRITE4(sc, HASH_TABLE_REG(hashreg), reg); 657 } 658 if_maddr_runlock(ifp); 659 } 660 661 /* 662 * Set the individual address filter hash. 663 */ 664 if (ifp->if_flags & IFF_PROMISC) 665 ffval |= (FRAME_FILTER_PR); 666 667 /* 668 * Set the primary address. 669 */ 670 eaddr = IF_LLADDR(ifp); 671 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 672 (eaddr[3] << 24); 673 hi = eaddr[4] | (eaddr[5] << 8); 674 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); 675 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); 676 WRITE4(sc, MAC_FRAME_FILTER, ffval); 677 } 678 679 static int 680 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 681 { 682 struct dwc_softc *sc; 683 struct mii_data *mii; 684 struct ifreq *ifr; 685 int mask, error; 686 687 sc = ifp->if_softc; 688 ifr = (struct ifreq *)data; 689 690 error = 0; 691 switch (cmd) { 692 case SIOCSIFFLAGS: 693 DWC_LOCK(sc); 694 if (ifp->if_flags & IFF_UP) { 695 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 696 if ((ifp->if_flags ^ sc->if_flags) & 697 (IFF_PROMISC | IFF_ALLMULTI)) 698 dwc_setup_rxfilter(sc); 699 } else { 700 if (!sc->is_detaching) 701 dwc_init_locked(sc); 702 } 703 } else { 704 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 705 dwc_stop_locked(sc); 706 } 707 sc->if_flags = ifp->if_flags; 708 DWC_UNLOCK(sc); 709 break; 710 case SIOCADDMULTI: 711 case SIOCDELMULTI: 712 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 713 DWC_LOCK(sc); 714 dwc_setup_rxfilter(sc); 715 DWC_UNLOCK(sc); 716 } 717 break; 718 case SIOCSIFMEDIA: 719 case SIOCGIFMEDIA: 720 mii = sc->mii_softc; 721 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 722 break; 723 case SIOCSIFCAP: 724 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 725 if (mask & IFCAP_VLAN_MTU) { 726 /* No work to do except acknowledge the change took */ 727 ifp->if_capenable ^= IFCAP_VLAN_MTU; 728 } 729 break; 730 731 default: 732 error = ether_ioctl(ifp, cmd, data); 733 break; 734 } 735 736 return (error); 737 } 738 739 static void 740 dwc_txfinish_locked(struct dwc_softc *sc) 741 { 742 struct dwc_bufmap *bmap; 743 struct dwc_hwdesc *desc; 744 745 DWC_ASSERT_LOCKED(sc); 746 747 while (sc->tx_idx_tail != sc->tx_idx_head) { 748 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 749 if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) 750 break; 751 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 752 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 753 BUS_DMASYNC_POSTWRITE); 754 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 755 m_freem(bmap->mbuf); 756 bmap->mbuf = NULL; 757 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 758 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 759 } 760 761 /* If there are no buffers outstanding, muzzle the watchdog. */ 762 if (sc->tx_idx_tail == sc->tx_idx_head) { 763 sc->tx_watchdog_count = 0; 764 } 765 } 766 767 static void 768 dwc_rxfinish_locked(struct dwc_softc *sc) 769 { 770 struct ifnet *ifp; 771 struct mbuf *m0; 772 struct mbuf *m; 773 int error; 774 int rdes0; 775 int idx; 776 int len; 777 778 ifp = sc->ifp; 779 780 for (;;) { 781 idx = sc->rx_idx; 782 783 rdes0 = sc->rxdesc_ring[idx].tdes0; 784 if ((rdes0 & DDESC_RDES0_OWN) != 0) 785 break; 786 787 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 788 BUS_DMASYNC_POSTREAD); 789 bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); 790 791 len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; 792 if (len != 0) { 793 m = sc->rxbuf_map[idx].mbuf; 794 m->m_pkthdr.rcvif = ifp; 795 m->m_pkthdr.len = len; 796 m->m_len = len; 797 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 798 799 DWC_UNLOCK(sc); 800 (*ifp->if_input)(ifp, m); 801 DWC_LOCK(sc); 802 } else { 803 /* XXX Zero-length packet ? */ 804 } 805 806 if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) { 807 if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { 808 /* 809 * XXX Now what? 810 * We've got a hole in the rx ring. 811 */ 812 } 813 } else 814 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 815 816 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 817 } 818 } 819 820 static void 821 dwc_intr(void *arg) 822 { 823 struct dwc_softc *sc; 824 uint32_t reg; 825 826 sc = arg; 827 828 DWC_LOCK(sc); 829 830 reg = READ4(sc, INTERRUPT_STATUS); 831 if (reg) { 832 mii_mediachg(sc->mii_softc); 833 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); 834 } 835 836 reg = READ4(sc, DMA_STATUS); 837 if (reg & DMA_STATUS_NIS) { 838 if (reg & DMA_STATUS_RI) 839 dwc_rxfinish_locked(sc); 840 841 if (reg & DMA_STATUS_TI) 842 dwc_txfinish_locked(sc); 843 } 844 845 if (reg & DMA_STATUS_AIS) { 846 if (reg & DMA_STATUS_FBI) { 847 /* Fatal bus error */ 848 device_printf(sc->dev, 849 "Ethernet DMA error, restarting controller.\n"); 850 dwc_stop_locked(sc); 851 dwc_init_locked(sc); 852 } 853 } 854 855 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 856 DWC_UNLOCK(sc); 857 } 858 859 static int 860 setup_dma(struct dwc_softc *sc) 861 { 862 struct mbuf *m; 863 int error; 864 int nidx; 865 int idx; 866 867 /* 868 * Set up TX descriptor ring, descriptors, and dma maps. 869 */ 870 error = bus_dma_tag_create( 871 bus_get_dma_tag(sc->dev), /* Parent tag. */ 872 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 873 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 874 BUS_SPACE_MAXADDR, /* highaddr */ 875 NULL, NULL, /* filter, filterarg */ 876 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 877 TX_DESC_SIZE, /* maxsegsize */ 878 0, /* flags */ 879 NULL, NULL, /* lockfunc, lockarg */ 880 &sc->txdesc_tag); 881 if (error != 0) { 882 device_printf(sc->dev, 883 "could not create TX ring DMA tag.\n"); 884 goto out; 885 } 886 887 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 888 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 889 &sc->txdesc_map); 890 if (error != 0) { 891 device_printf(sc->dev, 892 "could not allocate TX descriptor ring.\n"); 893 goto out; 894 } 895 896 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, 897 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, 898 &sc->txdesc_ring_paddr, 0); 899 if (error != 0) { 900 device_printf(sc->dev, 901 "could not load TX descriptor ring map.\n"); 902 goto out; 903 } 904 905 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 906 sc->txdesc_ring[idx].tdes0 = DDESC_TDES0_TXCHAIN; 907 sc->txdesc_ring[idx].tdes1 = 0; 908 nidx = next_txidx(sc, idx); 909 sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + \ 910 (nidx * sizeof(struct dwc_hwdesc)); 911 } 912 913 error = bus_dma_tag_create( 914 bus_get_dma_tag(sc->dev), /* Parent tag. */ 915 1, 0, /* alignment, boundary */ 916 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 917 BUS_SPACE_MAXADDR, /* highaddr */ 918 NULL, NULL, /* filter, filterarg */ 919 MCLBYTES, 1, /* maxsize, nsegments */ 920 MCLBYTES, /* maxsegsize */ 921 0, /* flags */ 922 NULL, NULL, /* lockfunc, lockarg */ 923 &sc->txbuf_tag); 924 if (error != 0) { 925 device_printf(sc->dev, 926 "could not create TX ring DMA tag.\n"); 927 goto out; 928 } 929 930 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 931 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, 932 &sc->txbuf_map[idx].map); 933 if (error != 0) { 934 device_printf(sc->dev, 935 "could not create TX buffer DMA map.\n"); 936 goto out; 937 } 938 dwc_setup_txdesc(sc, idx, 0, 0); 939 } 940 941 /* 942 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 943 */ 944 error = bus_dma_tag_create( 945 bus_get_dma_tag(sc->dev), /* Parent tag. */ 946 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 947 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 948 BUS_SPACE_MAXADDR, /* highaddr */ 949 NULL, NULL, /* filter, filterarg */ 950 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 951 RX_DESC_SIZE, /* maxsegsize */ 952 0, /* flags */ 953 NULL, NULL, /* lockfunc, lockarg */ 954 &sc->rxdesc_tag); 955 if (error != 0) { 956 device_printf(sc->dev, 957 "could not create RX ring DMA tag.\n"); 958 goto out; 959 } 960 961 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 962 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 963 &sc->rxdesc_map); 964 if (error != 0) { 965 device_printf(sc->dev, 966 "could not allocate RX descriptor ring.\n"); 967 goto out; 968 } 969 970 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, 971 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, 972 &sc->rxdesc_ring_paddr, 0); 973 if (error != 0) { 974 device_printf(sc->dev, 975 "could not load RX descriptor ring map.\n"); 976 goto out; 977 } 978 979 error = bus_dma_tag_create( 980 bus_get_dma_tag(sc->dev), /* Parent tag. */ 981 1, 0, /* alignment, boundary */ 982 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 983 BUS_SPACE_MAXADDR, /* highaddr */ 984 NULL, NULL, /* filter, filterarg */ 985 MCLBYTES, 1, /* maxsize, nsegments */ 986 MCLBYTES, /* maxsegsize */ 987 0, /* flags */ 988 NULL, NULL, /* lockfunc, lockarg */ 989 &sc->rxbuf_tag); 990 if (error != 0) { 991 device_printf(sc->dev, 992 "could not create RX buf DMA tag.\n"); 993 goto out; 994 } 995 996 for (idx = 0; idx < RX_DESC_COUNT; idx++) { 997 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, 998 &sc->rxbuf_map[idx].map); 999 if (error != 0) { 1000 device_printf(sc->dev, 1001 "could not create RX buffer DMA map.\n"); 1002 goto out; 1003 } 1004 if ((m = dwc_alloc_mbufcl(sc)) == NULL) { 1005 device_printf(sc->dev, "Could not alloc mbuf\n"); 1006 error = ENOMEM; 1007 goto out; 1008 } 1009 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { 1010 device_printf(sc->dev, 1011 "could not create new RX buffer.\n"); 1012 goto out; 1013 } 1014 } 1015 1016 out: 1017 if (error != 0) 1018 return (ENXIO); 1019 1020 return (0); 1021 } 1022 1023 static int 1024 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) 1025 { 1026 int rnd; 1027 int lo; 1028 int hi; 1029 1030 /* 1031 * Try to recover a MAC address from the running hardware. If there's 1032 * something non-zero there, assume the bootloader did the right thing 1033 * and just use it. 1034 * 1035 * Otherwise, set the address to a convenient locally assigned address, 1036 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 1037 * assigned bit set, and the broadcast/multicast bit clear. 1038 */ 1039 lo = READ4(sc, MAC_ADDRESS_LOW(0)); 1040 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; 1041 if ((lo != 0xffffffff) || (hi != 0xffff)) { 1042 hwaddr[0] = (lo >> 0) & 0xff; 1043 hwaddr[1] = (lo >> 8) & 0xff; 1044 hwaddr[2] = (lo >> 16) & 0xff; 1045 hwaddr[3] = (lo >> 24) & 0xff; 1046 hwaddr[4] = (hi >> 0) & 0xff; 1047 hwaddr[5] = (hi >> 8) & 0xff; 1048 } else { 1049 rnd = arc4random() & 0x00ffffff; 1050 hwaddr[0] = 'b'; 1051 hwaddr[1] = 's'; 1052 hwaddr[2] = 'd'; 1053 hwaddr[3] = rnd >> 16; 1054 hwaddr[4] = rnd >> 8; 1055 hwaddr[5] = rnd >> 0; 1056 } 1057 1058 return (0); 1059 } 1060 1061 static int 1062 dwc_probe(device_t dev) 1063 { 1064 1065 if (!ofw_bus_status_okay(dev)) 1066 return (ENXIO); 1067 1068 if (!ofw_bus_is_compatible(dev, "snps,dwmac")) 1069 return (ENXIO); 1070 1071 device_set_desc(dev, "Gigabit Ethernet Controller"); 1072 return (BUS_PROBE_DEFAULT); 1073 } 1074 1075 static int 1076 dwc_attach(device_t dev) 1077 { 1078 uint8_t macaddr[ETHER_ADDR_LEN]; 1079 struct dwc_softc *sc; 1080 struct ifnet *ifp; 1081 int error; 1082 int reg; 1083 int i; 1084 1085 sc = device_get_softc(dev); 1086 sc->dev = dev; 1087 sc->mii_clk = MII_CLK_VAL; 1088 sc->rx_idx = 0; 1089 1090 sc->txcount = TX_DESC_COUNT; 1091 1092 if (bus_alloc_resources(dev, dwc_spec, sc->res)) { 1093 device_printf(dev, "could not allocate resources\n"); 1094 return (ENXIO); 1095 } 1096 1097 /* Memory interface */ 1098 sc->bst = rman_get_bustag(sc->res[0]); 1099 sc->bsh = rman_get_bushandle(sc->res[0]); 1100 1101 /* Read MAC before reset */ 1102 if (dwc_get_hwaddr(sc, macaddr)) { 1103 device_printf(sc->dev, "can't get mac\n"); 1104 return (ENXIO); 1105 } 1106 1107 /* Reset */ 1108 reg = READ4(sc, BUS_MODE); 1109 reg |= (BUS_MODE_SWR); 1110 WRITE4(sc, BUS_MODE, reg); 1111 1112 for (i = 0; i < MAC_RESET_TIMEOUT; i++) { 1113 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 1114 break; 1115 DELAY(10); 1116 } 1117 if (i >= MAC_RESET_TIMEOUT) { 1118 device_printf(sc->dev, "Can't reset DWC.\n"); 1119 return (ENXIO); 1120 } 1121 1122 reg = READ4(sc, BUS_MODE); 1123 reg |= (BUS_MODE_EIGHTXPBL); 1124 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); 1125 WRITE4(sc, BUS_MODE, reg); 1126 1127 /* 1128 * DMA must be stop while changing descriptor list addresses. 1129 */ 1130 reg = READ4(sc, OPERATION_MODE); 1131 reg &= ~(MODE_ST | MODE_SR); 1132 WRITE4(sc, OPERATION_MODE, reg); 1133 1134 if (setup_dma(sc)) 1135 return (ENXIO); 1136 1137 /* Setup addresses */ 1138 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 1139 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 1140 1141 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), 1142 MTX_NETWORK_LOCK, MTX_DEF); 1143 1144 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); 1145 1146 /* Setup interrupt handler. */ 1147 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 1148 NULL, dwc_intr, sc, &sc->intr_cookie); 1149 if (error != 0) { 1150 device_printf(dev, "could not setup interrupt handler.\n"); 1151 return (ENXIO); 1152 } 1153 1154 /* Set up the ethernet interface. */ 1155 sc->ifp = ifp = if_alloc(IFT_ETHER); 1156 1157 ifp->if_softc = sc; 1158 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1159 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1160 ifp->if_capabilities = IFCAP_VLAN_MTU; 1161 ifp->if_capenable = ifp->if_capabilities; 1162 ifp->if_start = dwc_txstart; 1163 ifp->if_ioctl = dwc_ioctl; 1164 ifp->if_init = dwc_init; 1165 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1166 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1167 IFQ_SET_READY(&ifp->if_snd); 1168 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1169 1170 /* Attach the mii driver. */ 1171 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, 1172 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 1173 MII_OFFSET_ANY, 0); 1174 1175 if (error != 0) { 1176 device_printf(dev, "PHY attach failed\n"); 1177 return (ENXIO); 1178 } 1179 sc->mii_softc = device_get_softc(sc->miibus); 1180 1181 /* All ready to run, attach the ethernet interface. */ 1182 ether_ifattach(ifp, macaddr); 1183 sc->is_attached = true; 1184 1185 return (0); 1186 } 1187 1188 static int 1189 dwc_miibus_read_reg(device_t dev, int phy, int reg) 1190 { 1191 struct dwc_softc *sc; 1192 uint16_t mii; 1193 size_t cnt; 1194 int rv = 0; 1195 1196 sc = device_get_softc(dev); 1197 1198 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1199 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1200 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1201 | GMII_ADDRESS_GB; /* Busy flag */ 1202 1203 WRITE4(sc, GMII_ADDRESS, mii); 1204 1205 for (cnt = 0; cnt < 1000; cnt++) { 1206 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1207 rv = READ4(sc, GMII_DATA); 1208 break; 1209 } 1210 DELAY(10); 1211 } 1212 1213 return rv; 1214 } 1215 1216 static int 1217 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) 1218 { 1219 struct dwc_softc *sc; 1220 uint16_t mii; 1221 size_t cnt; 1222 1223 sc = device_get_softc(dev); 1224 1225 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1226 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1227 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1228 | GMII_ADDRESS_GB | GMII_ADDRESS_GW; 1229 1230 WRITE4(sc, GMII_DATA, val); 1231 WRITE4(sc, GMII_ADDRESS, mii); 1232 1233 for (cnt = 0; cnt < 1000; cnt++) { 1234 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1235 break; 1236 } 1237 DELAY(10); 1238 } 1239 1240 return (0); 1241 } 1242 1243 static void 1244 dwc_miibus_statchg(device_t dev) 1245 { 1246 struct dwc_softc *sc; 1247 struct mii_data *mii; 1248 int reg; 1249 1250 /* 1251 * Called by the MII bus driver when the PHY establishes 1252 * link to set the MAC interface registers. 1253 */ 1254 1255 sc = device_get_softc(dev); 1256 1257 DWC_ASSERT_LOCKED(sc); 1258 1259 mii = sc->mii_softc; 1260 1261 if (mii->mii_media_status & IFM_ACTIVE) 1262 sc->link_is_up = true; 1263 else 1264 sc->link_is_up = false; 1265 1266 reg = READ4(sc, MAC_CONFIGURATION); 1267 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1268 case IFM_1000_T: 1269 case IFM_1000_SX: 1270 reg &= ~(CONF_FES | CONF_PS); 1271 break; 1272 case IFM_100_TX: 1273 reg |= (CONF_FES | CONF_PS); 1274 break; 1275 case IFM_10_T: 1276 reg &= ~(CONF_FES); 1277 reg |= (CONF_PS); 1278 break; 1279 case IFM_NONE: 1280 sc->link_is_up = false; 1281 return; 1282 default: 1283 sc->link_is_up = false; 1284 device_printf(dev, "Unsupported media %u\n", 1285 IFM_SUBTYPE(mii->mii_media_active)); 1286 return; 1287 } 1288 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1289 reg |= (CONF_DM); 1290 else 1291 reg &= ~(CONF_DM); 1292 WRITE4(sc, MAC_CONFIGURATION, reg); 1293 } 1294 1295 static device_method_t dwc_methods[] = { 1296 DEVMETHOD(device_probe, dwc_probe), 1297 DEVMETHOD(device_attach, dwc_attach), 1298 1299 /* MII Interface */ 1300 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), 1301 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), 1302 DEVMETHOD(miibus_statchg, dwc_miibus_statchg), 1303 1304 { 0, 0 } 1305 }; 1306 1307 static driver_t dwc_driver = { 1308 "dwc", 1309 dwc_methods, 1310 sizeof(struct dwc_softc), 1311 }; 1312 1313 static devclass_t dwc_devclass; 1314 1315 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); 1316 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); 1317 1318 MODULE_DEPEND(dwc, ether, 1, 1, 1); 1319 MODULE_DEPEND(dwc, miibus, 1, 1, 1); 1320