1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Ethernet media access controller (EMAC) 33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 * 35 * EMAC is an instance of the Synopsys DesignWare 3504-0 36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/malloc.h> 48 #include <sys/mbuf.h> 49 #include <sys/module.h> 50 #include <sys/mutex.h> 51 #include <sys/rman.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 55 #include <net/bpf.h> 56 #include <net/if.h> 57 #include <net/ethernet.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_types.h> 61 #include <net/if_var.h> 62 63 #include <machine/bus.h> 64 65 #include <dev/dwc/if_dwc.h> 66 #include <dev/dwc/if_dwcvar.h> 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 #include <dev/ofw/ofw_bus.h> 70 #include <dev/ofw/ofw_bus_subr.h> 71 72 #include "if_dwc_if.h" 73 #include "miibus_if.h" 74 75 #define READ4(_sc, _reg) \ 76 bus_read_4((_sc)->res[0], _reg) 77 #define WRITE4(_sc, _reg, _val) \ 78 bus_write_4((_sc)->res[0], _reg, _val) 79 80 #define MAC_RESET_TIMEOUT 100 81 #define WATCHDOG_TIMEOUT_SECS 5 82 #define STATS_HARVEST_INTERVAL 2 83 84 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) 85 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 86 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 87 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 88 89 #define DDESC_TDES0_OWN (1U << 31) 90 #define DDESC_TDES0_TXINT (1U << 30) 91 #define DDESC_TDES0_TXLAST (1U << 29) 92 #define DDESC_TDES0_TXFIRST (1U << 28) 93 #define DDESC_TDES0_TXCRCDIS (1U << 27) 94 #define DDESC_TDES0_TXRINGEND (1U << 21) 95 #define DDESC_TDES0_TXCHAIN (1U << 20) 96 97 #define DDESC_RDES0_OWN (1U << 31) 98 #define DDESC_RDES0_FL_MASK 0x3fff 99 #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ 100 #define DDESC_RDES1_CHAINED (1U << 14) 101 102 /* Alt descriptor bits. */ 103 #define DDESC_CNTL_TXINT (1U << 31) 104 #define DDESC_CNTL_TXLAST (1U << 30) 105 #define DDESC_CNTL_TXFIRST (1U << 29) 106 #define DDESC_CNTL_TXCRCDIS (1U << 26) 107 #define DDESC_CNTL_TXRINGEND (1U << 25) 108 #define DDESC_CNTL_TXCHAIN (1U << 24) 109 110 #define DDESC_CNTL_CHAINED (1U << 24) 111 112 /* 113 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 114 * layout, but the bits in the fields have different meanings. 115 */ 116 struct dwc_hwdesc 117 { 118 uint32_t tdes0; /* status for alt layout */ 119 uint32_t tdes1; /* cntl for alt layout */ 120 uint32_t addr; /* pointer to buffer data */ 121 uint32_t addr_next; /* link to next descriptor */ 122 }; 123 124 /* 125 * The hardware imposes alignment restrictions on various objects involved in 126 * DMA transfers. These values are expressed in bytes (not bits). 127 */ 128 #define DWC_DESC_RING_ALIGN 2048 129 130 static struct resource_spec dwc_spec[] = { 131 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 132 { SYS_RES_IRQ, 0, RF_ACTIVE }, 133 { -1, 0 } 134 }; 135 136 static void dwc_txfinish_locked(struct dwc_softc *sc); 137 static void dwc_rxfinish_locked(struct dwc_softc *sc); 138 static void dwc_stop_locked(struct dwc_softc *sc); 139 static void dwc_setup_rxfilter(struct dwc_softc *sc); 140 141 static inline uint32_t 142 next_rxidx(struct dwc_softc *sc, uint32_t curidx) 143 { 144 145 return ((curidx + 1) % RX_DESC_COUNT); 146 } 147 148 static inline uint32_t 149 next_txidx(struct dwc_softc *sc, uint32_t curidx) 150 { 151 152 return ((curidx + 1) % TX_DESC_COUNT); 153 } 154 155 static void 156 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 157 { 158 159 if (error != 0) 160 return; 161 *(bus_addr_t *)arg = segs[0].ds_addr; 162 } 163 164 inline static uint32_t 165 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, 166 uint32_t len) 167 { 168 uint32_t flags; 169 uint32_t nidx; 170 171 nidx = next_txidx(sc, idx); 172 173 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 174 if (paddr == 0 || len == 0) { 175 flags = 0; 176 --sc->txcount; 177 } else { 178 if (sc->mactype == DWC_GMAC_ALT_DESC) 179 flags = DDESC_CNTL_TXCHAIN | DDESC_CNTL_TXFIRST 180 | DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT; 181 else 182 flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST 183 | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT; 184 ++sc->txcount; 185 } 186 187 sc->txdesc_ring[idx].addr = (uint32_t)(paddr); 188 if (sc->mactype == DWC_GMAC_ALT_DESC) { 189 sc->txdesc_ring[idx].tdes0 = 0; 190 sc->txdesc_ring[idx].tdes1 = flags | len; 191 } else { 192 sc->txdesc_ring[idx].tdes0 = flags; 193 sc->txdesc_ring[idx].tdes1 = len; 194 } 195 196 if (paddr && len) { 197 wmb(); 198 sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN; 199 wmb(); 200 } 201 202 return (nidx); 203 } 204 205 static int 206 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) 207 { 208 struct bus_dma_segment seg; 209 int error, nsegs; 210 struct mbuf * m; 211 212 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 213 return (ENOMEM); 214 *mp = m; 215 216 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 217 m, &seg, &nsegs, 0); 218 if (error != 0) { 219 return (ENOMEM); 220 } 221 222 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 223 224 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 225 BUS_DMASYNC_PREWRITE); 226 227 sc->txbuf_map[idx].mbuf = m; 228 229 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 230 231 return (0); 232 } 233 234 static void 235 dwc_txstart_locked(struct dwc_softc *sc) 236 { 237 struct ifnet *ifp; 238 struct mbuf *m; 239 int enqueued; 240 241 DWC_ASSERT_LOCKED(sc); 242 243 if (!sc->link_is_up) 244 return; 245 246 ifp = sc->ifp; 247 248 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 249 return; 250 } 251 252 enqueued = 0; 253 254 for (;;) { 255 if (sc->txcount == (TX_DESC_COUNT-1)) { 256 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 257 break; 258 } 259 260 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 261 if (m == NULL) 262 break; 263 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 264 IFQ_DRV_PREPEND(&ifp->if_snd, m); 265 break; 266 } 267 BPF_MTAP(ifp, m); 268 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 269 ++enqueued; 270 } 271 272 if (enqueued != 0) { 273 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 274 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 275 } 276 } 277 278 static void 279 dwc_txstart(struct ifnet *ifp) 280 { 281 struct dwc_softc *sc = ifp->if_softc; 282 283 DWC_LOCK(sc); 284 dwc_txstart_locked(sc); 285 DWC_UNLOCK(sc); 286 } 287 288 static void 289 dwc_stop_locked(struct dwc_softc *sc) 290 { 291 struct ifnet *ifp; 292 uint32_t reg; 293 294 DWC_ASSERT_LOCKED(sc); 295 296 ifp = sc->ifp; 297 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 298 sc->tx_watchdog_count = 0; 299 sc->stats_harvest_count = 0; 300 301 callout_stop(&sc->dwc_callout); 302 303 /* Stop DMA TX */ 304 reg = READ4(sc, OPERATION_MODE); 305 reg &= ~(MODE_ST); 306 WRITE4(sc, OPERATION_MODE, reg); 307 308 /* Flush TX */ 309 reg = READ4(sc, OPERATION_MODE); 310 reg |= (MODE_FTF); 311 WRITE4(sc, OPERATION_MODE, reg); 312 313 /* Stop transmitters */ 314 reg = READ4(sc, MAC_CONFIGURATION); 315 reg &= ~(CONF_TE | CONF_RE); 316 WRITE4(sc, MAC_CONFIGURATION, reg); 317 318 /* Stop DMA RX */ 319 reg = READ4(sc, OPERATION_MODE); 320 reg &= ~(MODE_SR); 321 WRITE4(sc, OPERATION_MODE, reg); 322 } 323 324 static void dwc_clear_stats(struct dwc_softc *sc) 325 { 326 uint32_t reg; 327 328 reg = READ4(sc, MMC_CONTROL); 329 reg |= (MMC_CONTROL_CNTRST); 330 WRITE4(sc, MMC_CONTROL, reg); 331 } 332 333 static void 334 dwc_harvest_stats(struct dwc_softc *sc) 335 { 336 struct ifnet *ifp; 337 338 /* We don't need to harvest too often. */ 339 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 340 return; 341 342 sc->stats_harvest_count = 0; 343 ifp = sc->ifp; 344 345 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); 346 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); 347 if_inc_counter(ifp, IFCOUNTER_IERRORS, 348 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + 349 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + 350 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + 351 READ4(sc, RXLENGTHERROR)); 352 353 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); 354 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); 355 if_inc_counter(ifp, IFCOUNTER_OERRORS, 356 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + 357 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); 358 359 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 360 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); 361 362 dwc_clear_stats(sc); 363 } 364 365 static void 366 dwc_tick(void *arg) 367 { 368 struct dwc_softc *sc; 369 struct ifnet *ifp; 370 int link_was_up; 371 372 sc = arg; 373 374 DWC_ASSERT_LOCKED(sc); 375 376 ifp = sc->ifp; 377 378 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 379 return; 380 381 /* 382 * Typical tx watchdog. If this fires it indicates that we enqueued 383 * packets for output and never got a txdone interrupt for them. Maybe 384 * it's a missed interrupt somehow, just pretend we got one. 385 */ 386 if (sc->tx_watchdog_count > 0) { 387 if (--sc->tx_watchdog_count == 0) { 388 dwc_txfinish_locked(sc); 389 } 390 } 391 392 /* Gather stats from hardware counters. */ 393 dwc_harvest_stats(sc); 394 395 /* Check the media status. */ 396 link_was_up = sc->link_is_up; 397 mii_tick(sc->mii_softc); 398 if (sc->link_is_up && !link_was_up) 399 dwc_txstart_locked(sc); 400 401 /* Schedule another check one second from now. */ 402 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 403 } 404 405 static void 406 dwc_init_locked(struct dwc_softc *sc) 407 { 408 struct ifnet *ifp = sc->ifp; 409 uint32_t reg; 410 411 DWC_ASSERT_LOCKED(sc); 412 413 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 414 return; 415 416 ifp->if_drv_flags |= IFF_DRV_RUNNING; 417 418 dwc_setup_rxfilter(sc); 419 420 /* Initializa DMA and enable transmitters */ 421 reg = READ4(sc, OPERATION_MODE); 422 reg |= (MODE_TSF | MODE_OSF | MODE_FUF); 423 reg &= ~(MODE_RSF); 424 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); 425 WRITE4(sc, OPERATION_MODE, reg); 426 427 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 428 429 /* Start DMA */ 430 reg = READ4(sc, OPERATION_MODE); 431 reg |= (MODE_ST | MODE_SR); 432 WRITE4(sc, OPERATION_MODE, reg); 433 434 /* Enable transmitters */ 435 reg = READ4(sc, MAC_CONFIGURATION); 436 reg |= (CONF_JD | CONF_ACS | CONF_BE); 437 reg |= (CONF_TE | CONF_RE); 438 WRITE4(sc, MAC_CONFIGURATION, reg); 439 440 /* 441 * Call mii_mediachg() which will call back into dwc_miibus_statchg() 442 * to set up the remaining config registers based on current media. 443 */ 444 mii_mediachg(sc->mii_softc); 445 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 446 } 447 448 static void 449 dwc_init(void *if_softc) 450 { 451 struct dwc_softc *sc = if_softc; 452 453 DWC_LOCK(sc); 454 dwc_init_locked(sc); 455 DWC_UNLOCK(sc); 456 } 457 458 inline static uint32_t 459 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) 460 { 461 uint32_t nidx; 462 463 sc->rxdesc_ring[idx].addr = (uint32_t)paddr; 464 nidx = next_rxidx(sc, idx); 465 sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \ 466 (nidx * sizeof(struct dwc_hwdesc)); 467 if (sc->mactype == DWC_GMAC_ALT_DESC) 468 sc->rxdesc_ring[idx].tdes1 = DDESC_CNTL_CHAINED | RX_MAX_PACKET; 469 else 470 sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; 471 472 wmb(); 473 sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; 474 wmb(); 475 476 return (nidx); 477 } 478 479 static int 480 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) 481 { 482 struct bus_dma_segment seg; 483 int error, nsegs; 484 485 m_adj(m, ETHER_ALIGN); 486 487 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 488 m, &seg, &nsegs, 0); 489 if (error != 0) { 490 return (error); 491 } 492 493 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 494 495 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 496 BUS_DMASYNC_PREREAD); 497 498 sc->rxbuf_map[idx].mbuf = m; 499 dwc_setup_rxdesc(sc, idx, seg.ds_addr); 500 501 return (0); 502 } 503 504 static struct mbuf * 505 dwc_alloc_mbufcl(struct dwc_softc *sc) 506 { 507 struct mbuf *m; 508 509 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 510 if (m != NULL) 511 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 512 513 return (m); 514 } 515 516 static void 517 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 518 { 519 struct dwc_softc *sc; 520 struct mii_data *mii; 521 522 sc = ifp->if_softc; 523 mii = sc->mii_softc; 524 DWC_LOCK(sc); 525 mii_pollstat(mii); 526 ifmr->ifm_active = mii->mii_media_active; 527 ifmr->ifm_status = mii->mii_media_status; 528 DWC_UNLOCK(sc); 529 } 530 531 static int 532 dwc_media_change_locked(struct dwc_softc *sc) 533 { 534 535 return (mii_mediachg(sc->mii_softc)); 536 } 537 538 static int 539 dwc_media_change(struct ifnet * ifp) 540 { 541 struct dwc_softc *sc; 542 int error; 543 544 sc = ifp->if_softc; 545 546 DWC_LOCK(sc); 547 error = dwc_media_change_locked(sc); 548 DWC_UNLOCK(sc); 549 return (error); 550 } 551 552 static const uint8_t nibbletab[] = { 553 /* 0x0 0000 -> 0000 */ 0x0, 554 /* 0x1 0001 -> 1000 */ 0x8, 555 /* 0x2 0010 -> 0100 */ 0x4, 556 /* 0x3 0011 -> 1100 */ 0xc, 557 /* 0x4 0100 -> 0010 */ 0x2, 558 /* 0x5 0101 -> 1010 */ 0xa, 559 /* 0x6 0110 -> 0110 */ 0x6, 560 /* 0x7 0111 -> 1110 */ 0xe, 561 /* 0x8 1000 -> 0001 */ 0x1, 562 /* 0x9 1001 -> 1001 */ 0x9, 563 /* 0xa 1010 -> 0101 */ 0x5, 564 /* 0xb 1011 -> 1101 */ 0xd, 565 /* 0xc 1100 -> 0011 */ 0x3, 566 /* 0xd 1101 -> 1011 */ 0xb, 567 /* 0xe 1110 -> 0111 */ 0x7, 568 /* 0xf 1111 -> 1111 */ 0xf, }; 569 570 static uint8_t 571 bitreverse(uint8_t x) 572 { 573 574 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; 575 } 576 577 static void 578 dwc_setup_rxfilter(struct dwc_softc *sc) 579 { 580 struct ifmultiaddr *ifma; 581 struct ifnet *ifp; 582 uint8_t *eaddr, val; 583 uint32_t crc, ffval, hashbit, hashreg, hi, lo, reg; 584 585 DWC_ASSERT_LOCKED(sc); 586 587 ifp = sc->ifp; 588 589 /* 590 * Set the multicast (group) filter hash. 591 */ 592 if ((ifp->if_flags & IFF_ALLMULTI)) 593 ffval = (FRAME_FILTER_PM); 594 else { 595 ffval = (FRAME_FILTER_HMC); 596 if_maddr_rlock(ifp); 597 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 598 if (ifma->ifma_addr->sa_family != AF_LINK) 599 continue; 600 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 601 ifma->ifma_addr), ETHER_ADDR_LEN); 602 603 /* Take lower 8 bits and reverse it */ 604 val = bitreverse(~crc & 0xff); 605 hashreg = (val >> 5); 606 hashbit = (val & 31); 607 608 reg = READ4(sc, HASH_TABLE_REG(hashreg)); 609 reg |= (1 << hashbit); 610 WRITE4(sc, HASH_TABLE_REG(hashreg), reg); 611 } 612 if_maddr_runlock(ifp); 613 } 614 615 /* 616 * Set the individual address filter hash. 617 */ 618 if (ifp->if_flags & IFF_PROMISC) 619 ffval |= (FRAME_FILTER_PR); 620 621 /* 622 * Set the primary address. 623 */ 624 eaddr = IF_LLADDR(ifp); 625 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 626 (eaddr[3] << 24); 627 hi = eaddr[4] | (eaddr[5] << 8); 628 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); 629 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); 630 WRITE4(sc, MAC_FRAME_FILTER, ffval); 631 } 632 633 static int 634 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 635 { 636 struct dwc_softc *sc; 637 struct mii_data *mii; 638 struct ifreq *ifr; 639 int mask, error; 640 641 sc = ifp->if_softc; 642 ifr = (struct ifreq *)data; 643 644 error = 0; 645 switch (cmd) { 646 case SIOCSIFFLAGS: 647 DWC_LOCK(sc); 648 if (ifp->if_flags & IFF_UP) { 649 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 650 if ((ifp->if_flags ^ sc->if_flags) & 651 (IFF_PROMISC | IFF_ALLMULTI)) 652 dwc_setup_rxfilter(sc); 653 } else { 654 if (!sc->is_detaching) 655 dwc_init_locked(sc); 656 } 657 } else { 658 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 659 dwc_stop_locked(sc); 660 } 661 sc->if_flags = ifp->if_flags; 662 DWC_UNLOCK(sc); 663 break; 664 case SIOCADDMULTI: 665 case SIOCDELMULTI: 666 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 667 DWC_LOCK(sc); 668 dwc_setup_rxfilter(sc); 669 DWC_UNLOCK(sc); 670 } 671 break; 672 case SIOCSIFMEDIA: 673 case SIOCGIFMEDIA: 674 mii = sc->mii_softc; 675 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 676 break; 677 case SIOCSIFCAP: 678 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 679 if (mask & IFCAP_VLAN_MTU) { 680 /* No work to do except acknowledge the change took */ 681 ifp->if_capenable ^= IFCAP_VLAN_MTU; 682 } 683 break; 684 685 default: 686 error = ether_ioctl(ifp, cmd, data); 687 break; 688 } 689 690 return (error); 691 } 692 693 static void 694 dwc_txfinish_locked(struct dwc_softc *sc) 695 { 696 struct dwc_bufmap *bmap; 697 struct dwc_hwdesc *desc; 698 struct ifnet *ifp; 699 700 DWC_ASSERT_LOCKED(sc); 701 702 ifp = sc->ifp; 703 while (sc->tx_idx_tail != sc->tx_idx_head) { 704 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 705 if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) 706 break; 707 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 708 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 709 BUS_DMASYNC_POSTWRITE); 710 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 711 m_freem(bmap->mbuf); 712 bmap->mbuf = NULL; 713 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 714 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 715 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 716 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 717 } 718 719 /* If there are no buffers outstanding, muzzle the watchdog. */ 720 if (sc->tx_idx_tail == sc->tx_idx_head) { 721 sc->tx_watchdog_count = 0; 722 } 723 } 724 725 static void 726 dwc_rxfinish_locked(struct dwc_softc *sc) 727 { 728 struct ifnet *ifp; 729 struct mbuf *m0; 730 struct mbuf *m; 731 int error, idx, len; 732 uint32_t rdes0; 733 734 ifp = sc->ifp; 735 736 for (;;) { 737 idx = sc->rx_idx; 738 739 rdes0 = sc->rxdesc_ring[idx].tdes0; 740 if ((rdes0 & DDESC_RDES0_OWN) != 0) 741 break; 742 743 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 744 BUS_DMASYNC_POSTREAD); 745 bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); 746 747 len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; 748 if (len != 0) { 749 m = sc->rxbuf_map[idx].mbuf; 750 m->m_pkthdr.rcvif = ifp; 751 m->m_pkthdr.len = len; 752 m->m_len = len; 753 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 754 755 DWC_UNLOCK(sc); 756 (*ifp->if_input)(ifp, m); 757 DWC_LOCK(sc); 758 } else { 759 /* XXX Zero-length packet ? */ 760 } 761 762 if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) { 763 if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { 764 /* 765 * XXX Now what? 766 * We've got a hole in the rx ring. 767 */ 768 } 769 } else 770 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 771 772 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 773 } 774 } 775 776 static void 777 dwc_intr(void *arg) 778 { 779 struct dwc_softc *sc; 780 uint32_t reg; 781 782 sc = arg; 783 784 DWC_LOCK(sc); 785 786 reg = READ4(sc, INTERRUPT_STATUS); 787 if (reg) 788 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); 789 790 reg = READ4(sc, DMA_STATUS); 791 if (reg & DMA_STATUS_NIS) { 792 if (reg & DMA_STATUS_RI) 793 dwc_rxfinish_locked(sc); 794 795 if (reg & DMA_STATUS_TI) { 796 dwc_txfinish_locked(sc); 797 dwc_txstart_locked(sc); 798 } 799 } 800 801 if (reg & DMA_STATUS_AIS) { 802 if (reg & DMA_STATUS_FBI) { 803 /* Fatal bus error */ 804 device_printf(sc->dev, 805 "Ethernet DMA error, restarting controller.\n"); 806 dwc_stop_locked(sc); 807 dwc_init_locked(sc); 808 } 809 } 810 811 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 812 DWC_UNLOCK(sc); 813 } 814 815 static int 816 setup_dma(struct dwc_softc *sc) 817 { 818 struct mbuf *m; 819 int error; 820 int nidx; 821 int idx; 822 823 /* 824 * Set up TX descriptor ring, descriptors, and dma maps. 825 */ 826 error = bus_dma_tag_create( 827 bus_get_dma_tag(sc->dev), /* Parent tag. */ 828 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 829 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 830 BUS_SPACE_MAXADDR, /* highaddr */ 831 NULL, NULL, /* filter, filterarg */ 832 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 833 TX_DESC_SIZE, /* maxsegsize */ 834 0, /* flags */ 835 NULL, NULL, /* lockfunc, lockarg */ 836 &sc->txdesc_tag); 837 if (error != 0) { 838 device_printf(sc->dev, 839 "could not create TX ring DMA tag.\n"); 840 goto out; 841 } 842 843 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 844 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 845 &sc->txdesc_map); 846 if (error != 0) { 847 device_printf(sc->dev, 848 "could not allocate TX descriptor ring.\n"); 849 goto out; 850 } 851 852 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, 853 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, 854 &sc->txdesc_ring_paddr, 0); 855 if (error != 0) { 856 device_printf(sc->dev, 857 "could not load TX descriptor ring map.\n"); 858 goto out; 859 } 860 861 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 862 nidx = next_txidx(sc, idx); 863 sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + 864 (nidx * sizeof(struct dwc_hwdesc)); 865 } 866 867 error = bus_dma_tag_create( 868 bus_get_dma_tag(sc->dev), /* Parent tag. */ 869 1, 0, /* alignment, boundary */ 870 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 871 BUS_SPACE_MAXADDR, /* highaddr */ 872 NULL, NULL, /* filter, filterarg */ 873 MCLBYTES, 1, /* maxsize, nsegments */ 874 MCLBYTES, /* maxsegsize */ 875 0, /* flags */ 876 NULL, NULL, /* lockfunc, lockarg */ 877 &sc->txbuf_tag); 878 if (error != 0) { 879 device_printf(sc->dev, 880 "could not create TX ring DMA tag.\n"); 881 goto out; 882 } 883 884 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 885 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, 886 &sc->txbuf_map[idx].map); 887 if (error != 0) { 888 device_printf(sc->dev, 889 "could not create TX buffer DMA map.\n"); 890 goto out; 891 } 892 dwc_setup_txdesc(sc, idx, 0, 0); 893 } 894 895 /* 896 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 897 */ 898 error = bus_dma_tag_create( 899 bus_get_dma_tag(sc->dev), /* Parent tag. */ 900 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 901 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 902 BUS_SPACE_MAXADDR, /* highaddr */ 903 NULL, NULL, /* filter, filterarg */ 904 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 905 RX_DESC_SIZE, /* maxsegsize */ 906 0, /* flags */ 907 NULL, NULL, /* lockfunc, lockarg */ 908 &sc->rxdesc_tag); 909 if (error != 0) { 910 device_printf(sc->dev, 911 "could not create RX ring DMA tag.\n"); 912 goto out; 913 } 914 915 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 916 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 917 &sc->rxdesc_map); 918 if (error != 0) { 919 device_printf(sc->dev, 920 "could not allocate RX descriptor ring.\n"); 921 goto out; 922 } 923 924 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, 925 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, 926 &sc->rxdesc_ring_paddr, 0); 927 if (error != 0) { 928 device_printf(sc->dev, 929 "could not load RX descriptor ring map.\n"); 930 goto out; 931 } 932 933 error = bus_dma_tag_create( 934 bus_get_dma_tag(sc->dev), /* Parent tag. */ 935 1, 0, /* alignment, boundary */ 936 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 937 BUS_SPACE_MAXADDR, /* highaddr */ 938 NULL, NULL, /* filter, filterarg */ 939 MCLBYTES, 1, /* maxsize, nsegments */ 940 MCLBYTES, /* maxsegsize */ 941 0, /* flags */ 942 NULL, NULL, /* lockfunc, lockarg */ 943 &sc->rxbuf_tag); 944 if (error != 0) { 945 device_printf(sc->dev, 946 "could not create RX buf DMA tag.\n"); 947 goto out; 948 } 949 950 for (idx = 0; idx < RX_DESC_COUNT; idx++) { 951 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, 952 &sc->rxbuf_map[idx].map); 953 if (error != 0) { 954 device_printf(sc->dev, 955 "could not create RX buffer DMA map.\n"); 956 goto out; 957 } 958 if ((m = dwc_alloc_mbufcl(sc)) == NULL) { 959 device_printf(sc->dev, "Could not alloc mbuf\n"); 960 error = ENOMEM; 961 goto out; 962 } 963 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { 964 device_printf(sc->dev, 965 "could not create new RX buffer.\n"); 966 goto out; 967 } 968 } 969 970 out: 971 if (error != 0) 972 return (ENXIO); 973 974 return (0); 975 } 976 977 static int 978 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) 979 { 980 uint32_t hi, lo, rnd; 981 982 /* 983 * Try to recover a MAC address from the running hardware. If there's 984 * something non-zero there, assume the bootloader did the right thing 985 * and just use it. 986 * 987 * Otherwise, set the address to a convenient locally assigned address, 988 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 989 * assigned bit set, and the broadcast/multicast bit clear. 990 */ 991 lo = READ4(sc, MAC_ADDRESS_LOW(0)); 992 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; 993 if ((lo != 0xffffffff) || (hi != 0xffff)) { 994 hwaddr[0] = (lo >> 0) & 0xff; 995 hwaddr[1] = (lo >> 8) & 0xff; 996 hwaddr[2] = (lo >> 16) & 0xff; 997 hwaddr[3] = (lo >> 24) & 0xff; 998 hwaddr[4] = (hi >> 0) & 0xff; 999 hwaddr[5] = (hi >> 8) & 0xff; 1000 } else { 1001 rnd = arc4random() & 0x00ffffff; 1002 hwaddr[0] = 'b'; 1003 hwaddr[1] = 's'; 1004 hwaddr[2] = 'd'; 1005 hwaddr[3] = rnd >> 16; 1006 hwaddr[4] = rnd >> 8; 1007 hwaddr[5] = rnd >> 0; 1008 } 1009 1010 return (0); 1011 } 1012 1013 static int 1014 dwc_probe(device_t dev) 1015 { 1016 1017 if (!ofw_bus_status_okay(dev)) 1018 return (ENXIO); 1019 1020 if (!ofw_bus_is_compatible(dev, "snps,dwmac")) 1021 return (ENXIO); 1022 1023 device_set_desc(dev, "Gigabit Ethernet Controller"); 1024 return (BUS_PROBE_DEFAULT); 1025 } 1026 1027 static int 1028 dwc_attach(device_t dev) 1029 { 1030 uint8_t macaddr[ETHER_ADDR_LEN]; 1031 struct dwc_softc *sc; 1032 struct ifnet *ifp; 1033 int error, i; 1034 uint32_t reg; 1035 1036 sc = device_get_softc(dev); 1037 sc->dev = dev; 1038 sc->rx_idx = 0; 1039 sc->txcount = TX_DESC_COUNT; 1040 sc->mii_clk = IF_DWC_MII_CLK(dev); 1041 sc->mactype = IF_DWC_MAC_TYPE(dev); 1042 1043 if (IF_DWC_INIT(dev) != 0) 1044 return (ENXIO); 1045 1046 if (bus_alloc_resources(dev, dwc_spec, sc->res)) { 1047 device_printf(dev, "could not allocate resources\n"); 1048 return (ENXIO); 1049 } 1050 1051 /* Memory interface */ 1052 sc->bst = rman_get_bustag(sc->res[0]); 1053 sc->bsh = rman_get_bushandle(sc->res[0]); 1054 1055 /* Read MAC before reset */ 1056 if (dwc_get_hwaddr(sc, macaddr)) { 1057 device_printf(sc->dev, "can't get mac\n"); 1058 return (ENXIO); 1059 } 1060 1061 /* Reset */ 1062 reg = READ4(sc, BUS_MODE); 1063 reg |= (BUS_MODE_SWR); 1064 WRITE4(sc, BUS_MODE, reg); 1065 1066 for (i = 0; i < MAC_RESET_TIMEOUT; i++) { 1067 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 1068 break; 1069 DELAY(10); 1070 } 1071 if (i >= MAC_RESET_TIMEOUT) { 1072 device_printf(sc->dev, "Can't reset DWC.\n"); 1073 return (ENXIO); 1074 } 1075 1076 if (sc->mactype == DWC_GMAC_ALT_DESC) { 1077 reg = BUS_MODE_FIXEDBURST; 1078 reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT); 1079 } else 1080 reg = (BUS_MODE_EIGHTXPBL); 1081 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); 1082 WRITE4(sc, BUS_MODE, reg); 1083 1084 /* 1085 * DMA must be stop while changing descriptor list addresses. 1086 */ 1087 reg = READ4(sc, OPERATION_MODE); 1088 reg &= ~(MODE_ST | MODE_SR); 1089 WRITE4(sc, OPERATION_MODE, reg); 1090 1091 if (setup_dma(sc)) 1092 return (ENXIO); 1093 1094 /* Setup addresses */ 1095 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 1096 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 1097 1098 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), 1099 MTX_NETWORK_LOCK, MTX_DEF); 1100 1101 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); 1102 1103 /* Setup interrupt handler. */ 1104 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 1105 NULL, dwc_intr, sc, &sc->intr_cookie); 1106 if (error != 0) { 1107 device_printf(dev, "could not setup interrupt handler.\n"); 1108 return (ENXIO); 1109 } 1110 1111 /* Set up the ethernet interface. */ 1112 sc->ifp = ifp = if_alloc(IFT_ETHER); 1113 1114 ifp->if_softc = sc; 1115 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1116 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1117 ifp->if_capabilities = IFCAP_VLAN_MTU; 1118 ifp->if_capenable = ifp->if_capabilities; 1119 ifp->if_start = dwc_txstart; 1120 ifp->if_ioctl = dwc_ioctl; 1121 ifp->if_init = dwc_init; 1122 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1123 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1124 IFQ_SET_READY(&ifp->if_snd); 1125 1126 /* Attach the mii driver. */ 1127 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, 1128 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 1129 MII_OFFSET_ANY, 0); 1130 1131 if (error != 0) { 1132 device_printf(dev, "PHY attach failed\n"); 1133 return (ENXIO); 1134 } 1135 sc->mii_softc = device_get_softc(sc->miibus); 1136 1137 /* All ready to run, attach the ethernet interface. */ 1138 ether_ifattach(ifp, macaddr); 1139 sc->is_attached = true; 1140 1141 return (0); 1142 } 1143 1144 static int 1145 dwc_miibus_read_reg(device_t dev, int phy, int reg) 1146 { 1147 struct dwc_softc *sc; 1148 uint16_t mii; 1149 size_t cnt; 1150 int rv = 0; 1151 1152 sc = device_get_softc(dev); 1153 1154 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1155 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1156 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1157 | GMII_ADDRESS_GB; /* Busy flag */ 1158 1159 WRITE4(sc, GMII_ADDRESS, mii); 1160 1161 for (cnt = 0; cnt < 1000; cnt++) { 1162 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1163 rv = READ4(sc, GMII_DATA); 1164 break; 1165 } 1166 DELAY(10); 1167 } 1168 1169 return rv; 1170 } 1171 1172 static int 1173 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) 1174 { 1175 struct dwc_softc *sc; 1176 uint16_t mii; 1177 size_t cnt; 1178 1179 sc = device_get_softc(dev); 1180 1181 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1182 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1183 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1184 | GMII_ADDRESS_GB | GMII_ADDRESS_GW; 1185 1186 WRITE4(sc, GMII_DATA, val); 1187 WRITE4(sc, GMII_ADDRESS, mii); 1188 1189 for (cnt = 0; cnt < 1000; cnt++) { 1190 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1191 break; 1192 } 1193 DELAY(10); 1194 } 1195 1196 return (0); 1197 } 1198 1199 static void 1200 dwc_miibus_statchg(device_t dev) 1201 { 1202 struct dwc_softc *sc; 1203 struct mii_data *mii; 1204 uint32_t reg; 1205 1206 /* 1207 * Called by the MII bus driver when the PHY establishes 1208 * link to set the MAC interface registers. 1209 */ 1210 1211 sc = device_get_softc(dev); 1212 1213 DWC_ASSERT_LOCKED(sc); 1214 1215 mii = sc->mii_softc; 1216 1217 if (mii->mii_media_status & IFM_ACTIVE) 1218 sc->link_is_up = true; 1219 else 1220 sc->link_is_up = false; 1221 1222 reg = READ4(sc, MAC_CONFIGURATION); 1223 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1224 case IFM_1000_T: 1225 case IFM_1000_SX: 1226 reg &= ~(CONF_FES | CONF_PS); 1227 break; 1228 case IFM_100_TX: 1229 reg |= (CONF_FES | CONF_PS); 1230 break; 1231 case IFM_10_T: 1232 reg &= ~(CONF_FES); 1233 reg |= (CONF_PS); 1234 break; 1235 case IFM_NONE: 1236 sc->link_is_up = false; 1237 return; 1238 default: 1239 sc->link_is_up = false; 1240 device_printf(dev, "Unsupported media %u\n", 1241 IFM_SUBTYPE(mii->mii_media_active)); 1242 return; 1243 } 1244 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1245 reg |= (CONF_DM); 1246 else 1247 reg &= ~(CONF_DM); 1248 WRITE4(sc, MAC_CONFIGURATION, reg); 1249 } 1250 1251 static device_method_t dwc_methods[] = { 1252 DEVMETHOD(device_probe, dwc_probe), 1253 DEVMETHOD(device_attach, dwc_attach), 1254 1255 /* MII Interface */ 1256 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), 1257 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), 1258 DEVMETHOD(miibus_statchg, dwc_miibus_statchg), 1259 1260 { 0, 0 } 1261 }; 1262 1263 driver_t dwc_driver = { 1264 "dwc", 1265 dwc_methods, 1266 sizeof(struct dwc_softc), 1267 }; 1268 1269 static devclass_t dwc_devclass; 1270 1271 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); 1272 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); 1273 1274 MODULE_DEPEND(dwc, ether, 1, 1, 1); 1275 MODULE_DEPEND(dwc, miibus, 1, 1, 1); 1276