1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * 4 * This software was developed by SRI International and the University of 5 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 6 * ("CTSRD"), as part of the DARPA CRASH research programme. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Ethernet media access controller (EMAC) 32 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 33 * 34 * EMAC is an instance of the Synopsys DesignWare 3504-0 35 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 36 */ 37 38 #include <sys/cdefs.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/gpio.h> 43 #include <sys/kernel.h> 44 #include <sys/lock.h> 45 #include <sys/malloc.h> 46 #include <sys/mbuf.h> 47 #include <sys/module.h> 48 #include <sys/mutex.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/ethernet.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_var.h> 60 61 #include <machine/bus.h> 62 63 #include <dev/extres/clk/clk.h> 64 #include <dev/extres/hwreset/hwreset.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/ofw/ofw_bus.h> 69 #include <dev/ofw/ofw_bus_subr.h> 70 #include <dev/mii/mii_fdt.h> 71 72 #include <dev/dwc/if_dwcvar.h> 73 #include <dev/dwc/dwc1000_reg.h> 74 #include <dev/dwc/dwc1000_core.h> 75 #include <dev/dwc/dwc1000_dma.h> 76 77 #include "if_dwc_if.h" 78 #include "gpio_if.h" 79 #include "miibus_if.h" 80 81 #define MAC_RESET_TIMEOUT 100 82 83 static struct resource_spec dwc_spec[] = { 84 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 85 { SYS_RES_IRQ, 0, RF_ACTIVE }, 86 { -1, 0 } 87 }; 88 89 static void dwc_stop_locked(struct dwc_softc *sc); 90 91 static void dwc_tick(void *arg); 92 93 /* 94 * Media functions 95 */ 96 97 static void 98 dwc_media_status(if_t ifp, struct ifmediareq *ifmr) 99 { 100 struct dwc_softc *sc; 101 struct mii_data *mii; 102 103 sc = if_getsoftc(ifp); 104 mii = sc->mii_softc; 105 DWC_LOCK(sc); 106 mii_pollstat(mii); 107 ifmr->ifm_active = mii->mii_media_active; 108 ifmr->ifm_status = mii->mii_media_status; 109 DWC_UNLOCK(sc); 110 } 111 112 static int 113 dwc_media_change_locked(struct dwc_softc *sc) 114 { 115 116 return (mii_mediachg(sc->mii_softc)); 117 } 118 119 static int 120 dwc_media_change(if_t ifp) 121 { 122 struct dwc_softc *sc; 123 int error; 124 125 sc = if_getsoftc(ifp); 126 127 DWC_LOCK(sc); 128 error = dwc_media_change_locked(sc); 129 DWC_UNLOCK(sc); 130 return (error); 131 } 132 133 /* 134 * if_ functions 135 */ 136 137 static void 138 dwc_txstart_locked(struct dwc_softc *sc) 139 { 140 if_t ifp; 141 142 DWC_ASSERT_LOCKED(sc); 143 144 if (!sc->link_is_up) 145 return; 146 147 ifp = sc->ifp; 148 149 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 150 IFF_DRV_RUNNING) 151 return; 152 dma1000_txstart(sc); 153 } 154 155 static void 156 dwc_txstart(if_t ifp) 157 { 158 struct dwc_softc *sc = if_getsoftc(ifp); 159 160 DWC_LOCK(sc); 161 dwc_txstart_locked(sc); 162 DWC_UNLOCK(sc); 163 } 164 165 static void 166 dwc_init_locked(struct dwc_softc *sc) 167 { 168 if_t ifp = sc->ifp; 169 170 DWC_ASSERT_LOCKED(sc); 171 172 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 173 return; 174 175 /* 176 * Call mii_mediachg() which will call back into dwc1000_miibus_statchg() 177 * to set up the remaining config registers based on current media. 178 */ 179 mii_mediachg(sc->mii_softc); 180 181 dwc1000_setup_rxfilter(sc); 182 dwc1000_core_setup(sc); 183 dwc1000_enable_mac(sc, true); 184 dwc1000_enable_csum_offload(sc); 185 dma1000_start(sc); 186 187 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 188 189 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 190 } 191 192 static void 193 dwc_init(void *if_softc) 194 { 195 struct dwc_softc *sc = if_softc; 196 197 DWC_LOCK(sc); 198 dwc_init_locked(sc); 199 DWC_UNLOCK(sc); 200 } 201 202 static void 203 dwc_stop_locked(struct dwc_softc *sc) 204 { 205 if_t ifp; 206 207 DWC_ASSERT_LOCKED(sc); 208 209 ifp = sc->ifp; 210 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 211 sc->tx_watchdog_count = 0; 212 sc->stats_harvest_count = 0; 213 214 callout_stop(&sc->dwc_callout); 215 216 dma1000_stop(sc); 217 dwc1000_enable_mac(sc, false); 218 } 219 220 static int 221 dwc_ioctl(if_t ifp, u_long cmd, caddr_t data) 222 { 223 struct dwc_softc *sc; 224 struct mii_data *mii; 225 struct ifreq *ifr; 226 int flags, mask, error; 227 228 sc = if_getsoftc(ifp); 229 ifr = (struct ifreq *)data; 230 231 error = 0; 232 switch (cmd) { 233 case SIOCSIFFLAGS: 234 DWC_LOCK(sc); 235 if (if_getflags(ifp) & IFF_UP) { 236 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 237 flags = if_getflags(ifp) ^ sc->if_flags; 238 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0) 239 dwc1000_setup_rxfilter(sc); 240 } else { 241 if (!sc->is_detaching) 242 dwc_init_locked(sc); 243 } 244 } else { 245 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 246 dwc_stop_locked(sc); 247 } 248 sc->if_flags = if_getflags(ifp); 249 DWC_UNLOCK(sc); 250 break; 251 case SIOCADDMULTI: 252 case SIOCDELMULTI: 253 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 254 DWC_LOCK(sc); 255 dwc1000_setup_rxfilter(sc); 256 DWC_UNLOCK(sc); 257 } 258 break; 259 case SIOCSIFMEDIA: 260 case SIOCGIFMEDIA: 261 mii = sc->mii_softc; 262 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 263 break; 264 case SIOCSIFCAP: 265 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 266 if (mask & IFCAP_VLAN_MTU) { 267 /* No work to do except acknowledge the change took */ 268 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 269 } 270 if (mask & IFCAP_RXCSUM) 271 if_togglecapenable(ifp, IFCAP_RXCSUM); 272 if (mask & IFCAP_TXCSUM) 273 if_togglecapenable(ifp, IFCAP_TXCSUM); 274 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 275 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0); 276 else 277 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP); 278 279 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 280 DWC_LOCK(sc); 281 dwc1000_enable_csum_offload(sc); 282 DWC_UNLOCK(sc); 283 } 284 break; 285 286 default: 287 error = ether_ioctl(ifp, cmd, data); 288 break; 289 } 290 291 return (error); 292 } 293 294 /* 295 * Interrupts functions 296 */ 297 298 299 static void 300 dwc_intr(void *arg) 301 { 302 struct dwc_softc *sc; 303 uint32_t reg; 304 305 sc = arg; 306 307 DWC_LOCK(sc); 308 309 reg = READ4(sc, INTERRUPT_STATUS); 310 if (reg) 311 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); 312 313 reg = READ4(sc, DMA_STATUS); 314 if (reg & DMA_STATUS_NIS) { 315 if (reg & DMA_STATUS_RI) 316 dma1000_rxfinish_locked(sc); 317 318 if (reg & DMA_STATUS_TI) { 319 dma1000_txfinish_locked(sc); 320 dwc_txstart_locked(sc); 321 } 322 } 323 324 if (reg & DMA_STATUS_AIS) { 325 if (reg & DMA_STATUS_FBI) { 326 /* Fatal bus error */ 327 device_printf(sc->dev, 328 "Ethernet DMA error, restarting controller.\n"); 329 dwc_stop_locked(sc); 330 dwc_init_locked(sc); 331 } 332 } 333 334 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 335 DWC_UNLOCK(sc); 336 } 337 338 static void 339 dwc_tick(void *arg) 340 { 341 struct dwc_softc *sc; 342 if_t ifp; 343 int link_was_up; 344 345 sc = arg; 346 347 DWC_ASSERT_LOCKED(sc); 348 349 ifp = sc->ifp; 350 351 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 352 return; 353 354 /* 355 * Typical tx watchdog. If this fires it indicates that we enqueued 356 * packets for output and never got a txdone interrupt for them. Maybe 357 * it's a missed interrupt somehow, just pretend we got one. 358 */ 359 if (sc->tx_watchdog_count > 0) { 360 if (--sc->tx_watchdog_count == 0) { 361 dma1000_txfinish_locked(sc); 362 } 363 } 364 365 /* Gather stats from hardware counters. */ 366 dwc1000_harvest_stats(sc); 367 368 /* Check the media status. */ 369 link_was_up = sc->link_is_up; 370 mii_tick(sc->mii_softc); 371 if (sc->link_is_up && !link_was_up) 372 dwc_txstart_locked(sc); 373 374 /* Schedule another check one second from now. */ 375 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 376 } 377 378 static int 379 dwc_reset_phy(struct dwc_softc *sc) 380 { 381 pcell_t gpio_prop[4]; 382 pcell_t delay_prop[3]; 383 phandle_t gpio_node; 384 device_t gpio; 385 uint32_t pin, flags; 386 uint32_t pin_value; 387 388 /* 389 * All those properties are deprecated but still used in some DTS. 390 * The new way to deal with this is to use the generic bindings 391 * present in the ethernet-phy node. 392 */ 393 if (OF_getencprop(sc->node, "snps,reset-gpio", 394 gpio_prop, sizeof(gpio_prop)) <= 0) 395 return (0); 396 397 if (OF_getencprop(sc->node, "snps,reset-delays-us", 398 delay_prop, sizeof(delay_prop)) <= 0) { 399 device_printf(sc->dev, 400 "Wrong property for snps,reset-delays-us"); 401 return (ENXIO); 402 } 403 404 gpio_node = OF_node_from_xref(gpio_prop[0]); 405 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) { 406 device_printf(sc->dev, 407 "Can't find gpio controller for phy reset\n"); 408 return (ENXIO); 409 } 410 411 if (GPIO_MAP_GPIOS(gpio, sc->node, gpio_node, 412 nitems(gpio_prop) - 1, 413 gpio_prop + 1, &pin, &flags) != 0) { 414 device_printf(sc->dev, "Can't map gpio for phy reset\n"); 415 return (ENXIO); 416 } 417 418 pin_value = GPIO_PIN_LOW; 419 if (OF_hasprop(sc->node, "snps,reset-active-low")) 420 pin_value = GPIO_PIN_HIGH; 421 422 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); 423 GPIO_PIN_SET(gpio, pin, pin_value); 424 DELAY(delay_prop[0] * 5); 425 GPIO_PIN_SET(gpio, pin, !pin_value); 426 DELAY(delay_prop[1] * 5); 427 GPIO_PIN_SET(gpio, pin, pin_value); 428 DELAY(delay_prop[2] * 5); 429 430 return (0); 431 } 432 433 static int 434 dwc_clock_init(struct dwc_softc *sc) 435 { 436 int rv; 437 int64_t freq; 438 439 /* Required clock */ 440 rv = clk_get_by_ofw_name(sc->dev, 0, "stmmaceth", &sc->clk_stmmaceth); 441 if (rv != 0) { 442 device_printf(sc->dev, "Cannot get GMAC main clock\n"); 443 return (ENXIO); 444 } 445 if ((rv = clk_enable(sc->clk_stmmaceth)) != 0) { 446 device_printf(sc->dev, "could not enable main clock\n"); 447 return (rv); 448 } 449 450 /* Optional clock */ 451 rv = clk_get_by_ofw_name(sc->dev, 0, "pclk", &sc->clk_pclk); 452 if (rv != 0) 453 return (0); 454 if ((rv = clk_enable(sc->clk_pclk)) != 0) { 455 device_printf(sc->dev, "could not enable peripheral clock\n"); 456 return (rv); 457 } 458 459 if (bootverbose) { 460 clk_get_freq(sc->clk_stmmaceth, &freq); 461 device_printf(sc->dev, "MAC clock(%s) freq: %jd\n", 462 clk_get_name(sc->clk_stmmaceth), (intmax_t)freq); 463 } 464 465 return (0); 466 } 467 468 static int 469 dwc_reset_deassert(struct dwc_softc *sc) 470 { 471 int rv; 472 473 /* Required reset */ 474 rv = hwreset_get_by_ofw_name(sc->dev, 0, "stmmaceth", &sc->rst_stmmaceth); 475 if (rv != 0) { 476 device_printf(sc->dev, "Cannot get GMAC reset\n"); 477 return (ENXIO); 478 } 479 rv = hwreset_deassert(sc->rst_stmmaceth); 480 if (rv != 0) { 481 device_printf(sc->dev, "could not de-assert GMAC reset\n"); 482 return (rv); 483 } 484 485 /* Optional reset */ 486 rv = hwreset_get_by_ofw_name(sc->dev, 0, "ahb", &sc->rst_ahb); 487 if (rv != 0) 488 return (0); 489 rv = hwreset_deassert(sc->rst_ahb); 490 if (rv != 0) { 491 device_printf(sc->dev, "could not de-assert AHB reset\n"); 492 return (rv); 493 } 494 495 return (0); 496 } 497 498 /* 499 * Probe/Attach functions 500 */ 501 502 static int 503 dwc_probe(device_t dev) 504 { 505 506 if (!ofw_bus_status_okay(dev)) 507 return (ENXIO); 508 509 if (!ofw_bus_is_compatible(dev, "snps,dwmac")) 510 return (ENXIO); 511 512 device_set_desc(dev, "Gigabit Ethernet Controller"); 513 return (BUS_PROBE_DEFAULT); 514 } 515 516 static int 517 dwc_attach(device_t dev) 518 { 519 uint8_t macaddr[ETHER_ADDR_LEN]; 520 struct dwc_softc *sc; 521 if_t ifp; 522 int error, i; 523 uint32_t reg; 524 uint32_t txpbl, rxpbl, pbl; 525 bool nopblx8 = false; 526 bool fixed_burst = false; 527 bool mixed_burst = false; 528 bool aal = false; 529 530 sc = device_get_softc(dev); 531 sc->dev = dev; 532 sc->rx_idx = 0; 533 sc->tx_desccount = TX_DESC_COUNT; 534 sc->tx_mapcount = 0; 535 sc->mii_clk = IF_DWC_MII_CLK(dev); 536 sc->mactype = IF_DWC_MAC_TYPE(dev); 537 538 sc->node = ofw_bus_get_node(dev); 539 switch (mii_fdt_get_contype(sc->node)) { 540 case MII_CONTYPE_RGMII: 541 case MII_CONTYPE_RGMII_ID: 542 case MII_CONTYPE_RGMII_RXID: 543 case MII_CONTYPE_RGMII_TXID: 544 sc->phy_mode = PHY_MODE_RGMII; 545 break; 546 case MII_CONTYPE_RMII: 547 sc->phy_mode = PHY_MODE_RMII; 548 break; 549 case MII_CONTYPE_MII: 550 sc->phy_mode = PHY_MODE_MII; 551 break; 552 default: 553 device_printf(dev, "Unsupported MII type\n"); 554 return (ENXIO); 555 } 556 557 if (OF_getencprop(sc->node, "snps,pbl", &pbl, sizeof(uint32_t)) <= 0) 558 pbl = BUS_MODE_DEFAULT_PBL; 559 if (OF_getencprop(sc->node, "snps,txpbl", &txpbl, sizeof(uint32_t)) <= 0) 560 txpbl = pbl; 561 if (OF_getencprop(sc->node, "snps,rxpbl", &rxpbl, sizeof(uint32_t)) <= 0) 562 rxpbl = pbl; 563 if (OF_hasprop(sc->node, "snps,no-pbl-x8") == 1) 564 nopblx8 = true; 565 if (OF_hasprop(sc->node, "snps,fixed-burst") == 1) 566 fixed_burst = true; 567 if (OF_hasprop(sc->node, "snps,mixed-burst") == 1) 568 mixed_burst = true; 569 if (OF_hasprop(sc->node, "snps,aal") == 1) 570 aal = true; 571 572 error = clk_set_assigned(dev, ofw_bus_get_node(dev)); 573 if (error != 0) { 574 device_printf(dev, "clk_set_assigned failed\n"); 575 return (error); 576 } 577 578 /* Enable main clock */ 579 if ((error = dwc_clock_init(sc)) != 0) 580 return (error); 581 /* De-assert main reset */ 582 if ((error = dwc_reset_deassert(sc)) != 0) 583 return (error); 584 585 if (IF_DWC_INIT(dev) != 0) 586 return (ENXIO); 587 588 if (bus_alloc_resources(dev, dwc_spec, sc->res)) { 589 device_printf(dev, "could not allocate resources\n"); 590 return (ENXIO); 591 } 592 593 /* Read MAC before reset */ 594 dwc1000_get_hwaddr(sc, macaddr); 595 596 /* Reset the PHY if needed */ 597 if (dwc_reset_phy(sc) != 0) { 598 device_printf(dev, "Can't reset the PHY\n"); 599 bus_release_resources(dev, dwc_spec, sc->res); 600 return (ENXIO); 601 } 602 603 /* Reset */ 604 reg = READ4(sc, BUS_MODE); 605 reg |= (BUS_MODE_SWR); 606 WRITE4(sc, BUS_MODE, reg); 607 608 for (i = 0; i < MAC_RESET_TIMEOUT; i++) { 609 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 610 break; 611 DELAY(10); 612 } 613 if (i >= MAC_RESET_TIMEOUT) { 614 device_printf(sc->dev, "Can't reset DWC.\n"); 615 bus_release_resources(dev, dwc_spec, sc->res); 616 return (ENXIO); 617 } 618 619 reg = BUS_MODE_USP; 620 if (!nopblx8) 621 reg |= BUS_MODE_EIGHTXPBL; 622 reg |= (txpbl << BUS_MODE_PBL_SHIFT); 623 reg |= (rxpbl << BUS_MODE_RPBL_SHIFT); 624 if (fixed_burst) 625 reg |= BUS_MODE_FIXEDBURST; 626 if (mixed_burst) 627 reg |= BUS_MODE_MIXEDBURST; 628 if (aal) 629 reg |= BUS_MODE_AAL; 630 631 WRITE4(sc, BUS_MODE, reg); 632 633 /* 634 * DMA must be stop while changing descriptor list addresses. 635 */ 636 reg = READ4(sc, OPERATION_MODE); 637 reg &= ~(MODE_ST | MODE_SR); 638 WRITE4(sc, OPERATION_MODE, reg); 639 640 if (dma1000_init(sc)) { 641 bus_release_resources(dev, dwc_spec, sc->res); 642 return (ENXIO); 643 } 644 645 /* Setup addresses */ 646 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 647 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 648 649 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), 650 MTX_NETWORK_LOCK, MTX_DEF); 651 652 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); 653 654 /* Setup interrupt handler. */ 655 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 656 NULL, dwc_intr, sc, &sc->intr_cookie); 657 if (error != 0) { 658 device_printf(dev, "could not setup interrupt handler.\n"); 659 bus_release_resources(dev, dwc_spec, sc->res); 660 return (ENXIO); 661 } 662 663 /* Set up the ethernet interface. */ 664 sc->ifp = ifp = if_alloc(IFT_ETHER); 665 666 if_setsoftc(ifp, sc); 667 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 668 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 669 if_setstartfn(ifp, dwc_txstart); 670 if_setioctlfn(ifp, dwc_ioctl); 671 if_setinitfn(ifp, dwc_init); 672 if_setsendqlen(ifp, TX_MAP_COUNT - 1); 673 if_setsendqready(sc->ifp); 674 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP); 675 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM); 676 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp)); 677 678 /* Attach the mii driver. */ 679 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, 680 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 681 MII_OFFSET_ANY, 0); 682 683 if (error != 0) { 684 device_printf(dev, "PHY attach failed\n"); 685 bus_teardown_intr(dev, sc->res[1], sc->intr_cookie); 686 bus_release_resources(dev, dwc_spec, sc->res); 687 return (ENXIO); 688 } 689 sc->mii_softc = device_get_softc(sc->miibus); 690 691 /* All ready to run, attach the ethernet interface. */ 692 ether_ifattach(ifp, macaddr); 693 sc->is_attached = true; 694 695 return (0); 696 } 697 698 static int 699 dwc_detach(device_t dev) 700 { 701 struct dwc_softc *sc; 702 703 sc = device_get_softc(dev); 704 705 /* 706 * Disable and tear down interrupts before anything else, so we don't 707 * race with the handler. 708 */ 709 WRITE4(sc, INTERRUPT_ENABLE, 0); 710 if (sc->intr_cookie != NULL) { 711 bus_teardown_intr(dev, sc->res[1], sc->intr_cookie); 712 } 713 714 if (sc->is_attached) { 715 DWC_LOCK(sc); 716 sc->is_detaching = true; 717 dwc_stop_locked(sc); 718 DWC_UNLOCK(sc); 719 callout_drain(&sc->dwc_callout); 720 ether_ifdetach(sc->ifp); 721 } 722 723 if (sc->miibus != NULL) { 724 device_delete_child(dev, sc->miibus); 725 sc->miibus = NULL; 726 } 727 bus_generic_detach(dev); 728 729 /* Free DMA descriptors */ 730 dma1000_free(sc); 731 732 if (sc->ifp != NULL) { 733 if_free(sc->ifp); 734 sc->ifp = NULL; 735 } 736 737 bus_release_resources(dev, dwc_spec, sc->res); 738 739 mtx_destroy(&sc->mtx); 740 return (0); 741 } 742 743 static device_method_t dwc_methods[] = { 744 DEVMETHOD(device_probe, dwc_probe), 745 DEVMETHOD(device_attach, dwc_attach), 746 DEVMETHOD(device_detach, dwc_detach), 747 748 /* MII Interface */ 749 DEVMETHOD(miibus_readreg, dwc1000_miibus_read_reg), 750 DEVMETHOD(miibus_writereg, dwc1000_miibus_write_reg), 751 DEVMETHOD(miibus_statchg, dwc1000_miibus_statchg), 752 753 { 0, 0 } 754 }; 755 756 driver_t dwc_driver = { 757 "dwc", 758 dwc_methods, 759 sizeof(struct dwc_softc), 760 }; 761 762 DRIVER_MODULE(dwc, simplebus, dwc_driver, 0, 0); 763 DRIVER_MODULE(miibus, dwc, miibus_driver, 0, 0); 764 765 MODULE_DEPEND(dwc, ether, 1, 1, 1); 766 MODULE_DEPEND(dwc, miibus, 1, 1, 1); 767