1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Ethernet media access controller (EMAC) 33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 * 35 * EMAC is an instance of the Synopsys DesignWare 3504-0 36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/gpio.h> 46 #include <sys/kernel.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/module.h> 51 #include <sys/mutex.h> 52 #include <sys/rman.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_var.h> 63 64 #include <machine/bus.h> 65 66 #include <dev/dwc/if_dwc.h> 67 #include <dev/dwc/if_dwcvar.h> 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 #include <dev/ofw/ofw_bus.h> 71 #include <dev/ofw/ofw_bus_subr.h> 72 73 #ifdef EXT_RESOURCES 74 #include <dev/extres/clk/clk.h> 75 #include <dev/extres/hwreset/hwreset.h> 76 #endif 77 78 #include "if_dwc_if.h" 79 #include "gpio_if.h" 80 #include "miibus_if.h" 81 82 #define READ4(_sc, _reg) \ 83 bus_read_4((_sc)->res[0], _reg) 84 #define WRITE4(_sc, _reg, _val) \ 85 bus_write_4((_sc)->res[0], _reg, _val) 86 87 #define MAC_RESET_TIMEOUT 100 88 #define WATCHDOG_TIMEOUT_SECS 5 89 #define STATS_HARVEST_INTERVAL 2 90 91 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) 92 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 93 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 94 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 95 96 /* TX descriptors - TDESC0 is almost unified */ 97 #define TDESC0_OWN (1U << 31) 98 #define TDESC0_IHE (1U << 16) /* IP Header Error */ 99 #define TDESC0_ES (1U << 15) /* Error Summary */ 100 #define TDESC0_JT (1U << 14) /* Jabber Timeout */ 101 #define TDESC0_FF (1U << 13) /* Frame Flushed */ 102 #define TDESC0_PCE (1U << 12) /* Payload Checksum Error */ 103 #define TDESC0_LOC (1U << 11) /* Loss of Carrier */ 104 #define TDESC0_NC (1U << 10) /* No Carrier */ 105 #define TDESC0_LC (1U << 9) /* Late Collision */ 106 #define TDESC0_EC (1U << 8) /* Excessive Collision */ 107 #define TDESC0_VF (1U << 7) /* VLAN Frame */ 108 #define TDESC0_CC_MASK 0xf 109 #define TDESC0_CC_SHIFT 3 /* Collision Count */ 110 #define TDESC0_ED (1U << 2) /* Excessive Deferral */ 111 #define TDESC0_UF (1U << 1) /* Underflow Error */ 112 #define TDESC0_DB (1U << 0) /* Deferred Bit */ 113 /* TX descriptors - TDESC0 extended format only */ 114 #define ETDESC0_IC (1U << 30) /* Interrupt on Completion */ 115 #define ETDESC0_LS (1U << 29) /* Last Segment */ 116 #define ETDESC0_FS (1U << 28) /* First Segment */ 117 #define ETDESC0_DC (1U << 27) /* Disable CRC */ 118 #define ETDESC0_DP (1U << 26) /* Disable Padding */ 119 #define ETDESC0_CIC_NONE (0U << 22) /* Checksum Insertion Control */ 120 #define ETDESC0_CIC_HDR (1U << 22) 121 #define ETDESC0_CIC_SEG (2U << 22) 122 #define ETDESC0_CIC_FULL (3U << 22) 123 #define ETDESC0_TER (1U << 21) /* Transmit End of Ring */ 124 #define ETDESC0_TCH (1U << 20) /* Second Address Chained */ 125 126 /* TX descriptors - TDESC1 normal format */ 127 #define NTDESC1_IC (1U << 31) /* Interrupt on Completion */ 128 #define NTDESC1_LS (1U << 30) /* Last Segment */ 129 #define NTDESC1_FS (1U << 29) /* First Segment */ 130 #define NTDESC1_CIC_NONE (0U << 27) /* Checksum Insertion Control */ 131 #define NTDESC1_CIC_HDR (1U << 27) 132 #define NTDESC1_CIC_SEG (2U << 27) 133 #define NTDESC1_CIC_FULL (3U << 27) 134 #define NTDESC1_DC (1U << 26) /* Disable CRC */ 135 #define NTDESC1_TER (1U << 25) /* Transmit End of Ring */ 136 #define NTDESC1_TCH (1U << 24) /* Second Address Chained */ 137 /* TX descriptors - TDESC1 extended format */ 138 #define ETDESC1_DP (1U << 23) /* Disable Padding */ 139 #define ETDESC1_TBS2_MASK 0x7ff 140 #define ETDESC1_TBS2_SHIFT 11 /* Receive Buffer 2 Size */ 141 #define ETDESC1_TBS1_MASK 0x7ff 142 #define ETDESC1_TBS1_SHIFT 0 /* Receive Buffer 1 Size */ 143 144 /* RX descriptor - RDESC0 is unified */ 145 #define RDESC0_OWN (1U << 31) 146 #define RDESC0_AFM (1U << 30) /* Dest. Address Filter Fail */ 147 #define RDESC0_FL_MASK 0x3fff 148 #define RDESC0_FL_SHIFT 16 /* Frame Length */ 149 #define RDESC0_ES (1U << 15) /* Error Summary */ 150 #define RDESC0_DE (1U << 14) /* Descriptor Error */ 151 #define RDESC0_SAF (1U << 13) /* Source Address Filter Fail */ 152 #define RDESC0_LE (1U << 12) /* Length Error */ 153 #define RDESC0_OE (1U << 11) /* Overflow Error */ 154 #define RDESC0_VLAN (1U << 10) /* VLAN Tag */ 155 #define RDESC0_FS (1U << 9) /* First Descriptor */ 156 #define RDESC0_LS (1U << 8) /* Last Descriptor */ 157 #define RDESC0_ICE (1U << 7) /* IPC Checksum Error */ 158 #define RDESC0_LC (1U << 6) /* Late Collision */ 159 #define RDESC0_FT (1U << 5) /* Frame Type */ 160 #define RDESC0_RWT (1U << 4) /* Receive Watchdog Timeout */ 161 #define RDESC0_RE (1U << 3) /* Receive Error */ 162 #define RDESC0_DBE (1U << 2) /* Dribble Bit Error */ 163 #define RDESC0_CE (1U << 1) /* CRC Error */ 164 #define RDESC0_PCE (1U << 0) /* Payload Checksum Error */ 165 #define RDESC0_RXMA (1U << 0) /* Rx MAC Address */ 166 167 /* RX descriptors - RDESC1 normal format */ 168 #define NRDESC1_DIC (1U << 31) /* Disable Intr on Completion */ 169 #define NRDESC1_RER (1U << 25) /* Receive End of Ring */ 170 #define NRDESC1_RCH (1U << 24) /* Second Address Chained */ 171 #define NRDESC1_RBS2_MASK 0x7ff 172 #define NRDESC1_RBS2_SHIFT 11 /* Receive Buffer 2 Size */ 173 #define NRDESC1_RBS1_MASK 0x7ff 174 #define NRDESC1_RBS1_SHIFT 0 /* Receive Buffer 1 Size */ 175 176 /* RX descriptors - RDESC1 enhanced format */ 177 #define ERDESC1_DIC (1U << 31) /* Disable Intr on Completion */ 178 #define ERDESC1_RBS2_MASK 0x7ffff 179 #define ERDESC1_RBS2_SHIFT 16 /* Receive Buffer 2 Size */ 180 #define ERDESC1_RER (1U << 15) /* Receive End of Ring */ 181 #define ERDESC1_RCH (1U << 14) /* Second Address Chained */ 182 #define ERDESC1_RBS1_MASK 0x7ffff 183 #define ERDESC1_RBS1_SHIFT 0 /* Receive Buffer 1 Size */ 184 185 /* 186 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 187 * layout, but the bits in the fields have different meanings. 188 */ 189 struct dwc_hwdesc 190 { 191 uint32_t desc0; 192 uint32_t desc1; 193 uint32_t addr1; /* ptr to first buffer data */ 194 uint32_t addr2; /* ptr to next descriptor / second buffer data*/ 195 }; 196 197 198 struct dwc_hash_maddr_ctx { 199 struct dwc_softc *sc; 200 uint32_t hash[8]; 201 }; 202 203 /* 204 * The hardware imposes alignment restrictions on various objects involved in 205 * DMA transfers. These values are expressed in bytes (not bits). 206 */ 207 #define DWC_DESC_RING_ALIGN 2048 208 209 static struct resource_spec dwc_spec[] = { 210 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 211 { SYS_RES_IRQ, 0, RF_ACTIVE }, 212 { -1, 0 } 213 }; 214 215 static void dwc_txfinish_locked(struct dwc_softc *sc); 216 static void dwc_rxfinish_locked(struct dwc_softc *sc); 217 static void dwc_stop_locked(struct dwc_softc *sc); 218 static void dwc_setup_rxfilter(struct dwc_softc *sc); 219 static void dwc_setup_core(struct dwc_softc *sc); 220 static void dwc_enable_mac(struct dwc_softc *sc, bool enable); 221 static void dwc_init_dma(struct dwc_softc *sc); 222 static void dwc_stop_dma(struct dwc_softc *sc); 223 224 static void dwc_tick(void *arg); 225 226 /* Pause time field in the transmitted control frame */ 227 static int dwc_pause_time = 0xffff; 228 TUNABLE_INT("hw.dwc.pause_time", &dwc_pause_time); 229 230 /* 231 * MIIBUS functions 232 */ 233 234 static int 235 dwc_miibus_read_reg(device_t dev, int phy, int reg) 236 { 237 struct dwc_softc *sc; 238 uint16_t mii; 239 size_t cnt; 240 int rv = 0; 241 242 sc = device_get_softc(dev); 243 244 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 245 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 246 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 247 | GMII_ADDRESS_GB; /* Busy flag */ 248 249 WRITE4(sc, GMII_ADDRESS, mii); 250 251 for (cnt = 0; cnt < 1000; cnt++) { 252 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 253 rv = READ4(sc, GMII_DATA); 254 break; 255 } 256 DELAY(10); 257 } 258 259 return rv; 260 } 261 262 static int 263 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) 264 { 265 struct dwc_softc *sc; 266 uint16_t mii; 267 size_t cnt; 268 269 sc = device_get_softc(dev); 270 271 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 272 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 273 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 274 | GMII_ADDRESS_GB | GMII_ADDRESS_GW; 275 276 WRITE4(sc, GMII_DATA, val); 277 WRITE4(sc, GMII_ADDRESS, mii); 278 279 for (cnt = 0; cnt < 1000; cnt++) { 280 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 281 break; 282 } 283 DELAY(10); 284 } 285 286 return (0); 287 } 288 289 static void 290 dwc_miibus_statchg(device_t dev) 291 { 292 struct dwc_softc *sc; 293 struct mii_data *mii; 294 uint32_t reg; 295 296 /* 297 * Called by the MII bus driver when the PHY establishes 298 * link to set the MAC interface registers. 299 */ 300 301 sc = device_get_softc(dev); 302 303 DWC_ASSERT_LOCKED(sc); 304 305 mii = sc->mii_softc; 306 307 if (mii->mii_media_status & IFM_ACTIVE) 308 sc->link_is_up = true; 309 else 310 sc->link_is_up = false; 311 312 reg = READ4(sc, MAC_CONFIGURATION); 313 switch (IFM_SUBTYPE(mii->mii_media_active)) { 314 case IFM_1000_T: 315 case IFM_1000_SX: 316 reg &= ~(CONF_FES | CONF_PS); 317 break; 318 case IFM_100_TX: 319 reg |= (CONF_FES | CONF_PS); 320 break; 321 case IFM_10_T: 322 reg &= ~(CONF_FES); 323 reg |= (CONF_PS); 324 break; 325 case IFM_NONE: 326 sc->link_is_up = false; 327 return; 328 default: 329 sc->link_is_up = false; 330 device_printf(dev, "Unsupported media %u\n", 331 IFM_SUBTYPE(mii->mii_media_active)); 332 return; 333 } 334 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 335 reg |= (CONF_DM); 336 else 337 reg &= ~(CONF_DM); 338 WRITE4(sc, MAC_CONFIGURATION, reg); 339 340 reg = FLOW_CONTROL_UP; 341 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 342 reg |= FLOW_CONTROL_TX; 343 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 344 reg |= FLOW_CONTROL_RX; 345 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 346 reg |= dwc_pause_time << FLOW_CONTROL_PT_SHIFT; 347 WRITE4(sc, FLOW_CONTROL, reg); 348 349 IF_DWC_SET_SPEED(dev, IFM_SUBTYPE(mii->mii_media_active)); 350 351 } 352 353 /* 354 * Media functions 355 */ 356 357 static void 358 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 359 { 360 struct dwc_softc *sc; 361 struct mii_data *mii; 362 363 sc = ifp->if_softc; 364 mii = sc->mii_softc; 365 DWC_LOCK(sc); 366 mii_pollstat(mii); 367 ifmr->ifm_active = mii->mii_media_active; 368 ifmr->ifm_status = mii->mii_media_status; 369 DWC_UNLOCK(sc); 370 } 371 372 static int 373 dwc_media_change_locked(struct dwc_softc *sc) 374 { 375 376 return (mii_mediachg(sc->mii_softc)); 377 } 378 379 static int 380 dwc_media_change(struct ifnet * ifp) 381 { 382 struct dwc_softc *sc; 383 int error; 384 385 sc = ifp->if_softc; 386 387 DWC_LOCK(sc); 388 error = dwc_media_change_locked(sc); 389 DWC_UNLOCK(sc); 390 return (error); 391 } 392 393 /* 394 * Core functions 395 */ 396 397 static const uint8_t nibbletab[] = { 398 /* 0x0 0000 -> 0000 */ 0x0, 399 /* 0x1 0001 -> 1000 */ 0x8, 400 /* 0x2 0010 -> 0100 */ 0x4, 401 /* 0x3 0011 -> 1100 */ 0xc, 402 /* 0x4 0100 -> 0010 */ 0x2, 403 /* 0x5 0101 -> 1010 */ 0xa, 404 /* 0x6 0110 -> 0110 */ 0x6, 405 /* 0x7 0111 -> 1110 */ 0xe, 406 /* 0x8 1000 -> 0001 */ 0x1, 407 /* 0x9 1001 -> 1001 */ 0x9, 408 /* 0xa 1010 -> 0101 */ 0x5, 409 /* 0xb 1011 -> 1101 */ 0xd, 410 /* 0xc 1100 -> 0011 */ 0x3, 411 /* 0xd 1101 -> 1011 */ 0xb, 412 /* 0xe 1110 -> 0111 */ 0x7, 413 /* 0xf 1111 -> 1111 */ 0xf, }; 414 415 static uint8_t 416 bitreverse(uint8_t x) 417 { 418 419 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; 420 } 421 422 static u_int 423 dwc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 424 { 425 struct dwc_hash_maddr_ctx *ctx = arg; 426 uint32_t crc, hashbit, hashreg; 427 uint8_t val; 428 429 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN); 430 /* Take lower 8 bits and reverse it */ 431 val = bitreverse(~crc & 0xff); 432 if (ctx->sc->mactype != DWC_GMAC_EXT_DESC) 433 val >>= 2; /* Only need lower 6 bits */ 434 hashreg = (val >> 5); 435 hashbit = (val & 31); 436 ctx->hash[hashreg] |= (1 << hashbit); 437 438 return (1); 439 } 440 441 static void 442 dwc_setup_rxfilter(struct dwc_softc *sc) 443 { 444 struct dwc_hash_maddr_ctx ctx; 445 struct ifnet *ifp; 446 uint8_t *eaddr; 447 uint32_t ffval, hi, lo; 448 int nhash, i; 449 450 DWC_ASSERT_LOCKED(sc); 451 452 ifp = sc->ifp; 453 nhash = sc->mactype != DWC_GMAC_EXT_DESC ? 2 : 8; 454 455 /* 456 * Set the multicast (group) filter hash. 457 */ 458 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 459 ffval = (FRAME_FILTER_PM); 460 for (i = 0; i < nhash; i++) 461 ctx.hash[i] = ~0; 462 } else { 463 ffval = (FRAME_FILTER_HMC); 464 for (i = 0; i < nhash; i++) 465 ctx.hash[i] = 0; 466 ctx.sc = sc; 467 if_foreach_llmaddr(ifp, dwc_hash_maddr, &ctx); 468 } 469 470 /* 471 * Set the individual address filter hash. 472 */ 473 if (ifp->if_flags & IFF_PROMISC) 474 ffval |= (FRAME_FILTER_PR); 475 476 /* 477 * Set the primary address. 478 */ 479 eaddr = IF_LLADDR(ifp); 480 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 481 (eaddr[3] << 24); 482 hi = eaddr[4] | (eaddr[5] << 8); 483 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); 484 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); 485 WRITE4(sc, MAC_FRAME_FILTER, ffval); 486 if (sc->mactype != DWC_GMAC_EXT_DESC) { 487 WRITE4(sc, GMAC_MAC_HTLOW, ctx.hash[0]); 488 WRITE4(sc, GMAC_MAC_HTHIGH, ctx.hash[1]); 489 } else { 490 for (i = 0; i < nhash; i++) 491 WRITE4(sc, HASH_TABLE_REG(i), ctx.hash[i]); 492 } 493 } 494 495 static void 496 dwc_setup_core(struct dwc_softc *sc) 497 { 498 uint32_t reg; 499 500 DWC_ASSERT_LOCKED(sc); 501 502 /* Enable core */ 503 reg = READ4(sc, MAC_CONFIGURATION); 504 reg |= (CONF_JD | CONF_ACS | CONF_BE); 505 WRITE4(sc, MAC_CONFIGURATION, reg); 506 } 507 508 static void 509 dwc_enable_mac(struct dwc_softc *sc, bool enable) 510 { 511 uint32_t reg; 512 513 DWC_ASSERT_LOCKED(sc); 514 reg = READ4(sc, MAC_CONFIGURATION); 515 if (enable) 516 reg |= CONF_TE | CONF_RE; 517 else 518 reg &= ~(CONF_TE | CONF_RE); 519 WRITE4(sc, MAC_CONFIGURATION, reg); 520 } 521 522 static void 523 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) 524 { 525 uint32_t hi, lo, rnd; 526 527 /* 528 * Try to recover a MAC address from the running hardware. If there's 529 * something non-zero there, assume the bootloader did the right thing 530 * and just use it. 531 * 532 * Otherwise, set the address to a convenient locally assigned address, 533 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 534 * assigned bit set, and the broadcast/multicast bit clear. 535 */ 536 lo = READ4(sc, MAC_ADDRESS_LOW(0)); 537 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; 538 if ((lo != 0xffffffff) || (hi != 0xffff)) { 539 hwaddr[0] = (lo >> 0) & 0xff; 540 hwaddr[1] = (lo >> 8) & 0xff; 541 hwaddr[2] = (lo >> 16) & 0xff; 542 hwaddr[3] = (lo >> 24) & 0xff; 543 hwaddr[4] = (hi >> 0) & 0xff; 544 hwaddr[5] = (hi >> 8) & 0xff; 545 } else { 546 rnd = arc4random() & 0x00ffffff; 547 hwaddr[0] = 'b'; 548 hwaddr[1] = 's'; 549 hwaddr[2] = 'd'; 550 hwaddr[3] = rnd >> 16; 551 hwaddr[4] = rnd >> 8; 552 hwaddr[5] = rnd >> 0; 553 } 554 } 555 556 /* 557 * DMA functions 558 */ 559 560 static void 561 dwc_init_dma(struct dwc_softc *sc) 562 { 563 uint32_t reg; 564 565 DWC_ASSERT_LOCKED(sc); 566 567 /* Initializa DMA and enable transmitters */ 568 reg = READ4(sc, OPERATION_MODE); 569 reg |= (MODE_TSF | MODE_OSF | MODE_FUF); 570 reg &= ~(MODE_RSF); 571 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); 572 WRITE4(sc, OPERATION_MODE, reg); 573 574 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 575 576 /* Start DMA */ 577 reg = READ4(sc, OPERATION_MODE); 578 reg |= (MODE_ST | MODE_SR); 579 WRITE4(sc, OPERATION_MODE, reg); 580 } 581 582 static void 583 dwc_stop_dma(struct dwc_softc *sc) 584 { 585 uint32_t reg; 586 587 DWC_ASSERT_LOCKED(sc); 588 589 /* Stop DMA TX */ 590 reg = READ4(sc, OPERATION_MODE); 591 reg &= ~(MODE_ST); 592 WRITE4(sc, OPERATION_MODE, reg); 593 594 /* Flush TX */ 595 reg = READ4(sc, OPERATION_MODE); 596 reg |= (MODE_FTF); 597 WRITE4(sc, OPERATION_MODE, reg); 598 599 /* Stop DMA RX */ 600 reg = READ4(sc, OPERATION_MODE); 601 reg &= ~(MODE_SR); 602 WRITE4(sc, OPERATION_MODE, reg); 603 } 604 605 static inline uint32_t 606 next_rxidx(struct dwc_softc *sc, uint32_t curidx) 607 { 608 609 return ((curidx + 1) % RX_DESC_COUNT); 610 } 611 612 static inline uint32_t 613 next_txidx(struct dwc_softc *sc, uint32_t curidx) 614 { 615 616 return ((curidx + 1) % TX_DESC_COUNT); 617 } 618 619 static void 620 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 621 { 622 623 if (error != 0) 624 return; 625 *(bus_addr_t *)arg = segs[0].ds_addr; 626 } 627 628 inline static void 629 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, 630 uint32_t len, uint32_t flags) 631 { 632 uint32_t desc0, desc1; 633 634 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 635 if (paddr == 0 || len == 0) { 636 desc0 = 0; 637 desc1 = 0; 638 --sc->txcount; 639 } else { 640 if (sc->mactype != DWC_GMAC_EXT_DESC) { 641 desc0 = 0; 642 desc1 = NTDESC1_TCH | NTDESC1_FS | NTDESC1_LS | 643 NTDESC1_IC | len | flags; 644 } else { 645 desc0 = ETDESC0_TCH | ETDESC0_FS | ETDESC0_LS | 646 ETDESC0_IC | flags; 647 desc1 = len; 648 } 649 ++sc->txcount; 650 } 651 652 sc->txdesc_ring[idx].addr1 = (uint32_t)(paddr); 653 sc->txdesc_ring[idx].desc0 = desc0; 654 sc->txdesc_ring[idx].desc1 = desc1; 655 656 if (paddr && len) { 657 wmb(); 658 sc->txdesc_ring[idx].desc0 |= TDESC0_OWN; 659 wmb(); 660 } 661 } 662 663 static int 664 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) 665 { 666 struct bus_dma_segment seg; 667 int error, nsegs; 668 struct mbuf * m; 669 uint32_t flags = 0; 670 671 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 672 return (ENOMEM); 673 *mp = m; 674 675 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 676 m, &seg, &nsegs, 0); 677 if (error != 0) { 678 return (ENOMEM); 679 } 680 681 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 682 683 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 684 BUS_DMASYNC_PREWRITE); 685 686 sc->txbuf_map[idx].mbuf = m; 687 688 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) { 689 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) { 690 if (sc->mactype != DWC_GMAC_EXT_DESC) 691 flags = NTDESC1_CIC_FULL; 692 else 693 flags = ETDESC0_CIC_FULL; 694 } else { 695 if (sc->mactype != DWC_GMAC_EXT_DESC) 696 flags = NTDESC1_CIC_HDR; 697 else 698 flags = ETDESC0_CIC_HDR; 699 } 700 } 701 702 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len, flags); 703 704 return (0); 705 } 706 707 inline static uint32_t 708 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) 709 { 710 uint32_t nidx; 711 712 sc->rxdesc_ring[idx].addr1 = (uint32_t)paddr; 713 nidx = next_rxidx(sc, idx); 714 sc->rxdesc_ring[idx].addr2 = sc->rxdesc_ring_paddr + 715 (nidx * sizeof(struct dwc_hwdesc)); 716 if (sc->mactype != DWC_GMAC_EXT_DESC) 717 sc->rxdesc_ring[idx].desc1 = NRDESC1_RCH | 718 MIN(MCLBYTES, NRDESC1_RBS1_MASK); 719 else 720 sc->rxdesc_ring[idx].desc1 = ERDESC1_RCH | 721 MIN(MCLBYTES, ERDESC1_RBS1_MASK); 722 723 wmb(); 724 sc->rxdesc_ring[idx].desc0 = RDESC0_OWN; 725 wmb(); 726 return (nidx); 727 } 728 729 static int 730 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) 731 { 732 struct bus_dma_segment seg; 733 int error, nsegs; 734 735 m_adj(m, ETHER_ALIGN); 736 737 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 738 m, &seg, &nsegs, 0); 739 if (error != 0) 740 return (error); 741 742 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 743 744 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 745 BUS_DMASYNC_PREREAD); 746 747 sc->rxbuf_map[idx].mbuf = m; 748 dwc_setup_rxdesc(sc, idx, seg.ds_addr); 749 750 return (0); 751 } 752 753 static struct mbuf * 754 dwc_alloc_mbufcl(struct dwc_softc *sc) 755 { 756 struct mbuf *m; 757 758 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 759 if (m != NULL) 760 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 761 762 return (m); 763 } 764 765 static struct mbuf * 766 dwc_rxfinish_one(struct dwc_softc *sc, struct dwc_hwdesc *desc, 767 struct dwc_bufmap *map) 768 { 769 struct ifnet *ifp; 770 struct mbuf *m, *m0; 771 int len; 772 uint32_t rdesc0; 773 774 m = map->mbuf; 775 ifp = sc->ifp; 776 rdesc0 = desc ->desc0; 777 /* Validate descriptor. */ 778 if (rdesc0 & RDESC0_ES) { 779 /* 780 * Errored packet. Statistic counters are updated 781 * globally, so do nothing 782 */ 783 return (NULL); 784 } 785 786 if ((rdesc0 & (RDESC0_FS | RDESC0_LS)) != 787 (RDESC0_FS | RDESC0_LS)) { 788 /* 789 * Something very wrong happens. The whole packet should be 790 * recevied in one descriptr. Report problem. 791 */ 792 device_printf(sc->dev, 793 "%s: RX descriptor without FIRST and LAST bit set: 0x%08X", 794 __func__, rdesc0); 795 return (NULL); 796 } 797 798 len = (rdesc0 >> RDESC0_FL_SHIFT) & RDESC0_FL_MASK; 799 if (len < 64) { 800 /* 801 * Lenght is invalid, recycle old mbuf 802 * Probably impossible case 803 */ 804 return (NULL); 805 } 806 807 /* Allocate new buffer */ 808 m0 = dwc_alloc_mbufcl(sc); 809 if (m0 == NULL) { 810 /* no new mbuf available, recycle old */ 811 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 812 return (NULL); 813 } 814 /* Do dmasync for newly received packet */ 815 bus_dmamap_sync(sc->rxbuf_tag, map->map, BUS_DMASYNC_POSTREAD); 816 bus_dmamap_unload(sc->rxbuf_tag, map->map); 817 818 /* Received packet is valid, process it */ 819 m->m_pkthdr.rcvif = ifp; 820 m->m_pkthdr.len = len; 821 m->m_len = len; 822 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 823 824 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 825 (rdesc0 & RDESC0_FT) != 0) { 826 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 827 if ((rdesc0 & RDESC0_ICE) == 0) 828 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 829 if ((rdesc0 & RDESC0_PCE) == 0) { 830 m->m_pkthdr.csum_flags |= 831 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 832 m->m_pkthdr.csum_data = 0xffff; 833 } 834 } 835 836 /* Remove trailing FCS */ 837 m_adj(m, -ETHER_CRC_LEN); 838 839 DWC_UNLOCK(sc); 840 (*ifp->if_input)(ifp, m); 841 DWC_LOCK(sc); 842 return (m0); 843 } 844 845 static int 846 setup_dma(struct dwc_softc *sc) 847 { 848 struct mbuf *m; 849 int error; 850 int nidx; 851 int idx; 852 853 /* 854 * Set up TX descriptor ring, descriptors, and dma maps. 855 */ 856 error = bus_dma_tag_create( 857 bus_get_dma_tag(sc->dev), /* Parent tag. */ 858 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 859 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 860 BUS_SPACE_MAXADDR, /* highaddr */ 861 NULL, NULL, /* filter, filterarg */ 862 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 863 TX_DESC_SIZE, /* maxsegsize */ 864 0, /* flags */ 865 NULL, NULL, /* lockfunc, lockarg */ 866 &sc->txdesc_tag); 867 if (error != 0) { 868 device_printf(sc->dev, 869 "could not create TX ring DMA tag.\n"); 870 goto out; 871 } 872 873 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 874 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 875 &sc->txdesc_map); 876 if (error != 0) { 877 device_printf(sc->dev, 878 "could not allocate TX descriptor ring.\n"); 879 goto out; 880 } 881 882 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, 883 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, 884 &sc->txdesc_ring_paddr, 0); 885 if (error != 0) { 886 device_printf(sc->dev, 887 "could not load TX descriptor ring map.\n"); 888 goto out; 889 } 890 891 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 892 nidx = next_txidx(sc, idx); 893 sc->txdesc_ring[idx].addr2 = sc->txdesc_ring_paddr + 894 (nidx * sizeof(struct dwc_hwdesc)); 895 } 896 897 error = bus_dma_tag_create( 898 bus_get_dma_tag(sc->dev), /* Parent tag. */ 899 1, 0, /* alignment, boundary */ 900 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 901 BUS_SPACE_MAXADDR, /* highaddr */ 902 NULL, NULL, /* filter, filterarg */ 903 MCLBYTES, 1, /* maxsize, nsegments */ 904 MCLBYTES, /* maxsegsize */ 905 0, /* flags */ 906 NULL, NULL, /* lockfunc, lockarg */ 907 &sc->txbuf_tag); 908 if (error != 0) { 909 device_printf(sc->dev, 910 "could not create TX ring DMA tag.\n"); 911 goto out; 912 } 913 914 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 915 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, 916 &sc->txbuf_map[idx].map); 917 if (error != 0) { 918 device_printf(sc->dev, 919 "could not create TX buffer DMA map.\n"); 920 goto out; 921 } 922 dwc_setup_txdesc(sc, idx, 0, 0, 0); 923 } 924 925 /* 926 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 927 */ 928 error = bus_dma_tag_create( 929 bus_get_dma_tag(sc->dev), /* Parent tag. */ 930 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 931 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 932 BUS_SPACE_MAXADDR, /* highaddr */ 933 NULL, NULL, /* filter, filterarg */ 934 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 935 RX_DESC_SIZE, /* maxsegsize */ 936 0, /* flags */ 937 NULL, NULL, /* lockfunc, lockarg */ 938 &sc->rxdesc_tag); 939 if (error != 0) { 940 device_printf(sc->dev, 941 "could not create RX ring DMA tag.\n"); 942 goto out; 943 } 944 945 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 946 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 947 &sc->rxdesc_map); 948 if (error != 0) { 949 device_printf(sc->dev, 950 "could not allocate RX descriptor ring.\n"); 951 goto out; 952 } 953 954 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, 955 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, 956 &sc->rxdesc_ring_paddr, 0); 957 if (error != 0) { 958 device_printf(sc->dev, 959 "could not load RX descriptor ring map.\n"); 960 goto out; 961 } 962 963 error = bus_dma_tag_create( 964 bus_get_dma_tag(sc->dev), /* Parent tag. */ 965 1, 0, /* alignment, boundary */ 966 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 967 BUS_SPACE_MAXADDR, /* highaddr */ 968 NULL, NULL, /* filter, filterarg */ 969 MCLBYTES, 1, /* maxsize, nsegments */ 970 MCLBYTES, /* maxsegsize */ 971 0, /* flags */ 972 NULL, NULL, /* lockfunc, lockarg */ 973 &sc->rxbuf_tag); 974 if (error != 0) { 975 device_printf(sc->dev, 976 "could not create RX buf DMA tag.\n"); 977 goto out; 978 } 979 980 for (idx = 0; idx < RX_DESC_COUNT; idx++) { 981 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, 982 &sc->rxbuf_map[idx].map); 983 if (error != 0) { 984 device_printf(sc->dev, 985 "could not create RX buffer DMA map.\n"); 986 goto out; 987 } 988 if ((m = dwc_alloc_mbufcl(sc)) == NULL) { 989 device_printf(sc->dev, "Could not alloc mbuf\n"); 990 error = ENOMEM; 991 goto out; 992 } 993 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { 994 device_printf(sc->dev, 995 "could not create new RX buffer.\n"); 996 goto out; 997 } 998 } 999 1000 out: 1001 if (error != 0) 1002 return (ENXIO); 1003 1004 return (0); 1005 } 1006 1007 /* 1008 * if_ functions 1009 */ 1010 1011 static void 1012 dwc_txstart_locked(struct dwc_softc *sc) 1013 { 1014 struct ifnet *ifp; 1015 struct mbuf *m; 1016 int enqueued; 1017 1018 DWC_ASSERT_LOCKED(sc); 1019 1020 if (!sc->link_is_up) 1021 return; 1022 1023 ifp = sc->ifp; 1024 1025 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 1026 IFF_DRV_RUNNING) 1027 return; 1028 1029 enqueued = 0; 1030 1031 for (;;) { 1032 if (sc->txcount == (TX_DESC_COUNT - 1)) { 1033 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1034 break; 1035 } 1036 1037 m = if_dequeue(ifp); 1038 if (m == NULL) 1039 break; 1040 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 1041 if_sendq_prepend(ifp, m); 1042 break; 1043 } 1044 if_bpfmtap(ifp, m); 1045 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 1046 ++enqueued; 1047 } 1048 1049 if (enqueued != 0) { 1050 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 1051 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 1052 } 1053 } 1054 1055 static void 1056 dwc_txstart(struct ifnet *ifp) 1057 { 1058 struct dwc_softc *sc = ifp->if_softc; 1059 1060 DWC_LOCK(sc); 1061 dwc_txstart_locked(sc); 1062 DWC_UNLOCK(sc); 1063 } 1064 1065 static void 1066 dwc_init_locked(struct dwc_softc *sc) 1067 { 1068 struct ifnet *ifp = sc->ifp; 1069 1070 DWC_ASSERT_LOCKED(sc); 1071 1072 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1073 return; 1074 1075 dwc_setup_rxfilter(sc); 1076 dwc_setup_core(sc); 1077 dwc_enable_mac(sc, true); 1078 dwc_init_dma(sc); 1079 1080 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 1081 1082 /* 1083 * Call mii_mediachg() which will call back into dwc_miibus_statchg() 1084 * to set up the remaining config registers based on current media. 1085 */ 1086 mii_mediachg(sc->mii_softc); 1087 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 1088 } 1089 1090 static void 1091 dwc_init(void *if_softc) 1092 { 1093 struct dwc_softc *sc = if_softc; 1094 1095 DWC_LOCK(sc); 1096 dwc_init_locked(sc); 1097 DWC_UNLOCK(sc); 1098 } 1099 1100 static void 1101 dwc_stop_locked(struct dwc_softc *sc) 1102 { 1103 struct ifnet *ifp; 1104 1105 DWC_ASSERT_LOCKED(sc); 1106 1107 ifp = sc->ifp; 1108 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1109 sc->tx_watchdog_count = 0; 1110 sc->stats_harvest_count = 0; 1111 1112 callout_stop(&sc->dwc_callout); 1113 1114 dwc_stop_dma(sc); 1115 dwc_enable_mac(sc, false); 1116 } 1117 1118 static int 1119 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1120 { 1121 struct dwc_softc *sc; 1122 struct mii_data *mii; 1123 struct ifreq *ifr; 1124 int flags, mask, error; 1125 1126 sc = ifp->if_softc; 1127 ifr = (struct ifreq *)data; 1128 1129 error = 0; 1130 switch (cmd) { 1131 case SIOCSIFFLAGS: 1132 DWC_LOCK(sc); 1133 if (if_getflags(ifp) & IFF_UP) { 1134 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1135 flags = if_getflags(ifp) ^ sc->if_flags; 1136 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0) 1137 dwc_setup_rxfilter(sc); 1138 } else { 1139 if (!sc->is_detaching) 1140 dwc_init_locked(sc); 1141 } 1142 } else { 1143 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1144 dwc_stop_locked(sc); 1145 } 1146 sc->if_flags = if_getflags(ifp); 1147 DWC_UNLOCK(sc); 1148 break; 1149 case SIOCADDMULTI: 1150 case SIOCDELMULTI: 1151 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1152 DWC_LOCK(sc); 1153 dwc_setup_rxfilter(sc); 1154 DWC_UNLOCK(sc); 1155 } 1156 break; 1157 case SIOCSIFMEDIA: 1158 case SIOCGIFMEDIA: 1159 mii = sc->mii_softc; 1160 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1161 break; 1162 case SIOCSIFCAP: 1163 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1164 if (mask & IFCAP_VLAN_MTU) { 1165 /* No work to do except acknowledge the change took */ 1166 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 1167 } 1168 if (mask & IFCAP_RXCSUM) 1169 if_togglecapenable(ifp, IFCAP_RXCSUM); 1170 if (mask & IFCAP_TXCSUM) 1171 if_togglecapenable(ifp, IFCAP_TXCSUM); 1172 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1173 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0); 1174 else 1175 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP); 1176 break; 1177 1178 default: 1179 error = ether_ioctl(ifp, cmd, data); 1180 break; 1181 } 1182 1183 return (error); 1184 } 1185 1186 /* 1187 * Interrupts functions 1188 */ 1189 1190 static void 1191 dwc_txfinish_locked(struct dwc_softc *sc) 1192 { 1193 struct dwc_bufmap *bmap; 1194 struct dwc_hwdesc *desc; 1195 struct ifnet *ifp; 1196 1197 DWC_ASSERT_LOCKED(sc); 1198 1199 ifp = sc->ifp; 1200 while (sc->tx_idx_tail != sc->tx_idx_head) { 1201 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 1202 if ((desc->desc0 & TDESC0_OWN) != 0) 1203 break; 1204 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 1205 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 1206 BUS_DMASYNC_POSTWRITE); 1207 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1208 m_freem(bmap->mbuf); 1209 bmap->mbuf = NULL; 1210 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0, 0); 1211 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 1212 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1213 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1214 } 1215 1216 /* If there are no buffers outstanding, muzzle the watchdog. */ 1217 if (sc->tx_idx_tail == sc->tx_idx_head) { 1218 sc->tx_watchdog_count = 0; 1219 } 1220 } 1221 1222 static void 1223 dwc_rxfinish_locked(struct dwc_softc *sc) 1224 { 1225 struct ifnet *ifp; 1226 struct mbuf *m; 1227 int error, idx; 1228 struct dwc_hwdesc *desc; 1229 1230 DWC_ASSERT_LOCKED(sc); 1231 ifp = sc->ifp; 1232 for (;;) { 1233 idx = sc->rx_idx; 1234 desc = sc->rxdesc_ring + idx; 1235 if ((desc->desc0 & RDESC0_OWN) != 0) 1236 break; 1237 1238 m = dwc_rxfinish_one(sc, desc, sc->rxbuf_map + idx); 1239 if (m == NULL) { 1240 wmb(); 1241 desc->desc0 = RDESC0_OWN; 1242 wmb(); 1243 } else { 1244 /* We cannot create hole in RX ring */ 1245 error = dwc_setup_rxbuf(sc, idx, m); 1246 if (error != 0) 1247 panic("dwc_setup_rxbuf failed: error %d\n", 1248 error); 1249 1250 } 1251 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 1252 } 1253 } 1254 1255 static void 1256 dwc_intr(void *arg) 1257 { 1258 struct dwc_softc *sc; 1259 uint32_t reg; 1260 1261 sc = arg; 1262 1263 DWC_LOCK(sc); 1264 1265 reg = READ4(sc, INTERRUPT_STATUS); 1266 if (reg) 1267 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); 1268 1269 reg = READ4(sc, DMA_STATUS); 1270 if (reg & DMA_STATUS_NIS) { 1271 if (reg & DMA_STATUS_RI) 1272 dwc_rxfinish_locked(sc); 1273 1274 if (reg & DMA_STATUS_TI) { 1275 dwc_txfinish_locked(sc); 1276 dwc_txstart_locked(sc); 1277 } 1278 } 1279 1280 if (reg & DMA_STATUS_AIS) { 1281 if (reg & DMA_STATUS_FBI) { 1282 /* Fatal bus error */ 1283 device_printf(sc->dev, 1284 "Ethernet DMA error, restarting controller.\n"); 1285 dwc_stop_locked(sc); 1286 dwc_init_locked(sc); 1287 } 1288 } 1289 1290 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 1291 DWC_UNLOCK(sc); 1292 } 1293 1294 /* 1295 * Stats 1296 */ 1297 1298 static void dwc_clear_stats(struct dwc_softc *sc) 1299 { 1300 uint32_t reg; 1301 1302 reg = READ4(sc, MMC_CONTROL); 1303 reg |= (MMC_CONTROL_CNTRST); 1304 WRITE4(sc, MMC_CONTROL, reg); 1305 } 1306 1307 static void 1308 dwc_harvest_stats(struct dwc_softc *sc) 1309 { 1310 struct ifnet *ifp; 1311 1312 /* We don't need to harvest too often. */ 1313 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 1314 return; 1315 1316 sc->stats_harvest_count = 0; 1317 ifp = sc->ifp; 1318 1319 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); 1320 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); 1321 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1322 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + 1323 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + 1324 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + 1325 READ4(sc, RXLENGTHERROR)); 1326 1327 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); 1328 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); 1329 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1330 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + 1331 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); 1332 1333 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1334 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); 1335 1336 dwc_clear_stats(sc); 1337 } 1338 1339 static void 1340 dwc_tick(void *arg) 1341 { 1342 struct dwc_softc *sc; 1343 struct ifnet *ifp; 1344 int link_was_up; 1345 1346 sc = arg; 1347 1348 DWC_ASSERT_LOCKED(sc); 1349 1350 ifp = sc->ifp; 1351 1352 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1353 return; 1354 1355 /* 1356 * Typical tx watchdog. If this fires it indicates that we enqueued 1357 * packets for output and never got a txdone interrupt for them. Maybe 1358 * it's a missed interrupt somehow, just pretend we got one. 1359 */ 1360 if (sc->tx_watchdog_count > 0) { 1361 if (--sc->tx_watchdog_count == 0) { 1362 dwc_txfinish_locked(sc); 1363 } 1364 } 1365 1366 /* Gather stats from hardware counters. */ 1367 dwc_harvest_stats(sc); 1368 1369 /* Check the media status. */ 1370 link_was_up = sc->link_is_up; 1371 mii_tick(sc->mii_softc); 1372 if (sc->link_is_up && !link_was_up) 1373 dwc_txstart_locked(sc); 1374 1375 /* Schedule another check one second from now. */ 1376 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 1377 } 1378 1379 /* 1380 * Probe/Attach functions 1381 */ 1382 1383 #define GPIO_ACTIVE_LOW 1 1384 1385 static int 1386 dwc_reset(device_t dev) 1387 { 1388 pcell_t gpio_prop[4]; 1389 pcell_t delay_prop[3]; 1390 phandle_t node, gpio_node; 1391 device_t gpio; 1392 uint32_t pin, flags; 1393 uint32_t pin_value; 1394 1395 node = ofw_bus_get_node(dev); 1396 if (OF_getencprop(node, "snps,reset-gpio", 1397 gpio_prop, sizeof(gpio_prop)) <= 0) 1398 return (0); 1399 1400 if (OF_getencprop(node, "snps,reset-delays-us", 1401 delay_prop, sizeof(delay_prop)) <= 0) { 1402 device_printf(dev, 1403 "Wrong property for snps,reset-delays-us"); 1404 return (ENXIO); 1405 } 1406 1407 gpio_node = OF_node_from_xref(gpio_prop[0]); 1408 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) { 1409 device_printf(dev, 1410 "Can't find gpio controller for phy reset\n"); 1411 return (ENXIO); 1412 } 1413 1414 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, 1415 nitems(gpio_prop) - 1, 1416 gpio_prop + 1, &pin, &flags) != 0) { 1417 device_printf(dev, "Can't map gpio for phy reset\n"); 1418 return (ENXIO); 1419 } 1420 1421 pin_value = GPIO_PIN_LOW; 1422 if (OF_hasprop(node, "snps,reset-active-low")) 1423 pin_value = GPIO_PIN_HIGH; 1424 1425 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); 1426 GPIO_PIN_SET(gpio, pin, pin_value); 1427 DELAY(delay_prop[0] * 5); 1428 GPIO_PIN_SET(gpio, pin, !pin_value); 1429 DELAY(delay_prop[1] * 5); 1430 GPIO_PIN_SET(gpio, pin, pin_value); 1431 DELAY(delay_prop[2] * 5); 1432 1433 return (0); 1434 } 1435 1436 #ifdef EXT_RESOURCES 1437 static int 1438 dwc_clock_init(device_t dev) 1439 { 1440 hwreset_t rst; 1441 clk_t clk; 1442 int error; 1443 int64_t freq; 1444 1445 /* Enable clocks */ 1446 if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk) == 0) { 1447 error = clk_enable(clk); 1448 if (error != 0) { 1449 device_printf(dev, "could not enable main clock\n"); 1450 return (error); 1451 } 1452 if (bootverbose) { 1453 clk_get_freq(clk, &freq); 1454 device_printf(dev, "MAC clock(%s) freq: %jd\n", 1455 clk_get_name(clk), (intmax_t)freq); 1456 } 1457 } 1458 else { 1459 device_printf(dev, "could not find clock stmmaceth\n"); 1460 } 1461 1462 /* De-assert reset */ 1463 if (hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst) == 0) { 1464 error = hwreset_deassert(rst); 1465 if (error != 0) { 1466 device_printf(dev, "could not de-assert reset\n"); 1467 return (error); 1468 } 1469 } 1470 1471 return (0); 1472 } 1473 #endif 1474 1475 static int 1476 dwc_probe(device_t dev) 1477 { 1478 1479 if (!ofw_bus_status_okay(dev)) 1480 return (ENXIO); 1481 1482 if (!ofw_bus_is_compatible(dev, "snps,dwmac")) 1483 return (ENXIO); 1484 1485 device_set_desc(dev, "Gigabit Ethernet Controller"); 1486 return (BUS_PROBE_DEFAULT); 1487 } 1488 1489 static int 1490 dwc_attach(device_t dev) 1491 { 1492 uint8_t macaddr[ETHER_ADDR_LEN]; 1493 struct dwc_softc *sc; 1494 struct ifnet *ifp; 1495 int error, i; 1496 uint32_t reg; 1497 char *phy_mode; 1498 phandle_t node; 1499 uint32_t txpbl, rxpbl, pbl; 1500 bool nopblx8 = false; 1501 bool fixed_burst = false; 1502 1503 sc = device_get_softc(dev); 1504 sc->dev = dev; 1505 sc->rx_idx = 0; 1506 sc->txcount = TX_DESC_COUNT; 1507 sc->mii_clk = IF_DWC_MII_CLK(dev); 1508 sc->mactype = IF_DWC_MAC_TYPE(dev); 1509 1510 node = ofw_bus_get_node(dev); 1511 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_mode)) { 1512 if (strcmp(phy_mode, "rgmii") == 0) 1513 sc->phy_mode = PHY_MODE_RGMII; 1514 if (strcmp(phy_mode, "rmii") == 0) 1515 sc->phy_mode = PHY_MODE_RMII; 1516 OF_prop_free(phy_mode); 1517 } 1518 1519 if (OF_getencprop(node, "snps,pbl", &pbl, sizeof(uint32_t)) <= 0) 1520 pbl = BUS_MODE_DEFAULT_PBL; 1521 if (OF_getencprop(node, "snps,txpbl", &txpbl, sizeof(uint32_t)) <= 0) 1522 txpbl = pbl; 1523 if (OF_getencprop(node, "snps,rxpbl", &rxpbl, sizeof(uint32_t)) <= 0) 1524 rxpbl = pbl; 1525 if (OF_hasprop(node, "snps,no-pbl-x8") == 1) 1526 nopblx8 = true; 1527 if (OF_hasprop(node, "snps,fixed-burst") == 1) 1528 fixed_burst = true; 1529 1530 if (IF_DWC_INIT(dev) != 0) 1531 return (ENXIO); 1532 1533 #ifdef EXT_RESOURCES 1534 if (dwc_clock_init(dev) != 0) 1535 return (ENXIO); 1536 #endif 1537 1538 if (bus_alloc_resources(dev, dwc_spec, sc->res)) { 1539 device_printf(dev, "could not allocate resources\n"); 1540 return (ENXIO); 1541 } 1542 1543 /* Read MAC before reset */ 1544 dwc_get_hwaddr(sc, macaddr); 1545 1546 /* Reset the PHY if needed */ 1547 if (dwc_reset(dev) != 0) { 1548 device_printf(dev, "Can't reset the PHY\n"); 1549 return (ENXIO); 1550 } 1551 1552 /* Reset */ 1553 reg = READ4(sc, BUS_MODE); 1554 reg |= (BUS_MODE_SWR); 1555 WRITE4(sc, BUS_MODE, reg); 1556 1557 for (i = 0; i < MAC_RESET_TIMEOUT; i++) { 1558 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 1559 break; 1560 DELAY(10); 1561 } 1562 if (i >= MAC_RESET_TIMEOUT) { 1563 device_printf(sc->dev, "Can't reset DWC.\n"); 1564 return (ENXIO); 1565 } 1566 1567 reg = BUS_MODE_USP; 1568 if (!nopblx8) 1569 reg |= BUS_MODE_EIGHTXPBL; 1570 reg |= (txpbl << BUS_MODE_PBL_SHIFT); 1571 reg |= (rxpbl << BUS_MODE_RPBL_SHIFT); 1572 if (fixed_burst) 1573 reg |= BUS_MODE_FIXEDBURST; 1574 1575 WRITE4(sc, BUS_MODE, reg); 1576 1577 /* 1578 * DMA must be stop while changing descriptor list addresses. 1579 */ 1580 reg = READ4(sc, OPERATION_MODE); 1581 reg &= ~(MODE_ST | MODE_SR); 1582 WRITE4(sc, OPERATION_MODE, reg); 1583 1584 if (setup_dma(sc)) 1585 return (ENXIO); 1586 1587 /* Setup addresses */ 1588 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 1589 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 1590 1591 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), 1592 MTX_NETWORK_LOCK, MTX_DEF); 1593 1594 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); 1595 1596 /* Setup interrupt handler. */ 1597 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 1598 NULL, dwc_intr, sc, &sc->intr_cookie); 1599 if (error != 0) { 1600 device_printf(dev, "could not setup interrupt handler.\n"); 1601 return (ENXIO); 1602 } 1603 1604 /* Set up the ethernet interface. */ 1605 sc->ifp = ifp = if_alloc(IFT_ETHER); 1606 1607 ifp->if_softc = sc; 1608 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1609 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1610 if_setstartfn(ifp, dwc_txstart); 1611 if_setioctlfn(ifp, dwc_ioctl); 1612 if_setinitfn(ifp, dwc_init); 1613 if_setsendqlen(ifp, TX_DESC_COUNT - 1); 1614 if_setsendqready(sc->ifp); 1615 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP); 1616 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM); 1617 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp)); 1618 1619 /* Attach the mii driver. */ 1620 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, 1621 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 1622 MII_OFFSET_ANY, 0); 1623 1624 if (error != 0) { 1625 device_printf(dev, "PHY attach failed\n"); 1626 return (ENXIO); 1627 } 1628 sc->mii_softc = device_get_softc(sc->miibus); 1629 1630 /* All ready to run, attach the ethernet interface. */ 1631 ether_ifattach(ifp, macaddr); 1632 sc->is_attached = true; 1633 1634 return (0); 1635 } 1636 1637 static device_method_t dwc_methods[] = { 1638 DEVMETHOD(device_probe, dwc_probe), 1639 DEVMETHOD(device_attach, dwc_attach), 1640 1641 /* MII Interface */ 1642 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), 1643 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), 1644 DEVMETHOD(miibus_statchg, dwc_miibus_statchg), 1645 1646 { 0, 0 } 1647 }; 1648 1649 driver_t dwc_driver = { 1650 "dwc", 1651 dwc_methods, 1652 sizeof(struct dwc_softc), 1653 }; 1654 1655 static devclass_t dwc_devclass; 1656 1657 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); 1658 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); 1659 1660 MODULE_DEPEND(dwc, ether, 1, 1, 1); 1661 MODULE_DEPEND(dwc, miibus, 1, 1, 1); 1662