1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Ethernet media access controller (EMAC) 33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 * 35 * EMAC is an instance of the Synopsys DesignWare 3504-0 36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/gpio.h> 46 #include <sys/kernel.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/module.h> 51 #include <sys/mutex.h> 52 #include <sys/rman.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_var.h> 63 64 #include <machine/bus.h> 65 66 #include <dev/dwc/if_dwc.h> 67 #include <dev/dwc/if_dwcvar.h> 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 #include <dev/ofw/ofw_bus.h> 71 #include <dev/ofw/ofw_bus_subr.h> 72 73 #ifdef EXT_RESOURCES 74 #include <dev/extres/clk/clk.h> 75 #include <dev/extres/hwreset/hwreset.h> 76 #endif 77 78 #include "if_dwc_if.h" 79 #include "gpio_if.h" 80 #include "miibus_if.h" 81 82 #define READ4(_sc, _reg) \ 83 bus_read_4((_sc)->res[0], _reg) 84 #define WRITE4(_sc, _reg, _val) \ 85 bus_write_4((_sc)->res[0], _reg, _val) 86 87 #define MAC_RESET_TIMEOUT 100 88 #define WATCHDOG_TIMEOUT_SECS 5 89 #define STATS_HARVEST_INTERVAL 2 90 91 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) 92 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 93 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 94 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 95 96 #define DDESC_TDES0_OWN (1U << 31) 97 #define DDESC_TDES0_TXINT (1U << 30) 98 #define DDESC_TDES0_TXLAST (1U << 29) 99 #define DDESC_TDES0_TXFIRST (1U << 28) 100 #define DDESC_TDES0_TXCRCDIS (1U << 27) 101 #define DDESC_TDES0_TXRINGEND (1U << 21) 102 #define DDESC_TDES0_TXCHAIN (1U << 20) 103 104 #define DDESC_RDES0_OWN (1U << 31) 105 #define DDESC_RDES0_FL_MASK 0x3fff 106 #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ 107 #define DDESC_RDES1_CHAINED (1U << 14) 108 109 /* Alt descriptor bits. */ 110 #define DDESC_CNTL_TXINT (1U << 31) 111 #define DDESC_CNTL_TXLAST (1U << 30) 112 #define DDESC_CNTL_TXFIRST (1U << 29) 113 #define DDESC_CNTL_TXCRCDIS (1U << 26) 114 #define DDESC_CNTL_TXRINGEND (1U << 25) 115 #define DDESC_CNTL_TXCHAIN (1U << 24) 116 117 #define DDESC_CNTL_CHAINED (1U << 24) 118 119 /* 120 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 121 * layout, but the bits in the fields have different meanings. 122 */ 123 struct dwc_hwdesc 124 { 125 uint32_t tdes0; /* status for alt layout */ 126 uint32_t tdes1; /* cntl for alt layout */ 127 uint32_t addr; /* pointer to buffer data */ 128 uint32_t addr_next; /* link to next descriptor */ 129 }; 130 131 /* 132 * The hardware imposes alignment restrictions on various objects involved in 133 * DMA transfers. These values are expressed in bytes (not bits). 134 */ 135 #define DWC_DESC_RING_ALIGN 2048 136 137 static struct resource_spec dwc_spec[] = { 138 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 139 { SYS_RES_IRQ, 0, RF_ACTIVE }, 140 { -1, 0 } 141 }; 142 143 static void dwc_txfinish_locked(struct dwc_softc *sc); 144 static void dwc_rxfinish_locked(struct dwc_softc *sc); 145 static void dwc_stop_locked(struct dwc_softc *sc); 146 static void dwc_setup_rxfilter(struct dwc_softc *sc); 147 148 static inline uint32_t 149 next_rxidx(struct dwc_softc *sc, uint32_t curidx) 150 { 151 152 return ((curidx + 1) % RX_DESC_COUNT); 153 } 154 155 static inline uint32_t 156 next_txidx(struct dwc_softc *sc, uint32_t curidx) 157 { 158 159 return ((curidx + 1) % TX_DESC_COUNT); 160 } 161 162 static void 163 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 164 { 165 166 if (error != 0) 167 return; 168 *(bus_addr_t *)arg = segs[0].ds_addr; 169 } 170 171 inline static uint32_t 172 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, 173 uint32_t len) 174 { 175 uint32_t flags; 176 uint32_t nidx; 177 178 nidx = next_txidx(sc, idx); 179 180 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 181 if (paddr == 0 || len == 0) { 182 flags = 0; 183 --sc->txcount; 184 } else { 185 if (sc->mactype == DWC_GMAC_ALT_DESC) 186 flags = DDESC_CNTL_TXCHAIN | DDESC_CNTL_TXFIRST 187 | DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT; 188 else 189 flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST 190 | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT; 191 ++sc->txcount; 192 } 193 194 sc->txdesc_ring[idx].addr = (uint32_t)(paddr); 195 if (sc->mactype == DWC_GMAC_ALT_DESC) { 196 sc->txdesc_ring[idx].tdes0 = 0; 197 sc->txdesc_ring[idx].tdes1 = flags | len; 198 } else { 199 sc->txdesc_ring[idx].tdes0 = flags; 200 sc->txdesc_ring[idx].tdes1 = len; 201 } 202 203 if (paddr && len) { 204 wmb(); 205 sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN; 206 wmb(); 207 } 208 209 return (nidx); 210 } 211 212 static int 213 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) 214 { 215 struct bus_dma_segment seg; 216 int error, nsegs; 217 struct mbuf * m; 218 219 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 220 return (ENOMEM); 221 *mp = m; 222 223 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 224 m, &seg, &nsegs, 0); 225 if (error != 0) { 226 return (ENOMEM); 227 } 228 229 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 230 231 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 232 BUS_DMASYNC_PREWRITE); 233 234 sc->txbuf_map[idx].mbuf = m; 235 236 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 237 238 return (0); 239 } 240 241 static void 242 dwc_txstart_locked(struct dwc_softc *sc) 243 { 244 struct ifnet *ifp; 245 struct mbuf *m; 246 int enqueued; 247 248 DWC_ASSERT_LOCKED(sc); 249 250 if (!sc->link_is_up) 251 return; 252 253 ifp = sc->ifp; 254 255 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 256 return; 257 } 258 259 enqueued = 0; 260 261 for (;;) { 262 if (sc->txcount == (TX_DESC_COUNT-1)) { 263 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 264 break; 265 } 266 267 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 268 if (m == NULL) 269 break; 270 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 271 IFQ_DRV_PREPEND(&ifp->if_snd, m); 272 break; 273 } 274 BPF_MTAP(ifp, m); 275 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 276 ++enqueued; 277 } 278 279 if (enqueued != 0) { 280 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 281 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 282 } 283 } 284 285 static void 286 dwc_txstart(struct ifnet *ifp) 287 { 288 struct dwc_softc *sc = ifp->if_softc; 289 290 DWC_LOCK(sc); 291 dwc_txstart_locked(sc); 292 DWC_UNLOCK(sc); 293 } 294 295 static void 296 dwc_stop_locked(struct dwc_softc *sc) 297 { 298 struct ifnet *ifp; 299 uint32_t reg; 300 301 DWC_ASSERT_LOCKED(sc); 302 303 ifp = sc->ifp; 304 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 305 sc->tx_watchdog_count = 0; 306 sc->stats_harvest_count = 0; 307 308 callout_stop(&sc->dwc_callout); 309 310 /* Stop DMA TX */ 311 reg = READ4(sc, OPERATION_MODE); 312 reg &= ~(MODE_ST); 313 WRITE4(sc, OPERATION_MODE, reg); 314 315 /* Flush TX */ 316 reg = READ4(sc, OPERATION_MODE); 317 reg |= (MODE_FTF); 318 WRITE4(sc, OPERATION_MODE, reg); 319 320 /* Stop transmitters */ 321 reg = READ4(sc, MAC_CONFIGURATION); 322 reg &= ~(CONF_TE | CONF_RE); 323 WRITE4(sc, MAC_CONFIGURATION, reg); 324 325 /* Stop DMA RX */ 326 reg = READ4(sc, OPERATION_MODE); 327 reg &= ~(MODE_SR); 328 WRITE4(sc, OPERATION_MODE, reg); 329 } 330 331 static void dwc_clear_stats(struct dwc_softc *sc) 332 { 333 uint32_t reg; 334 335 reg = READ4(sc, MMC_CONTROL); 336 reg |= (MMC_CONTROL_CNTRST); 337 WRITE4(sc, MMC_CONTROL, reg); 338 } 339 340 static void 341 dwc_harvest_stats(struct dwc_softc *sc) 342 { 343 struct ifnet *ifp; 344 345 /* We don't need to harvest too often. */ 346 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 347 return; 348 349 sc->stats_harvest_count = 0; 350 ifp = sc->ifp; 351 352 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); 353 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); 354 if_inc_counter(ifp, IFCOUNTER_IERRORS, 355 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + 356 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + 357 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + 358 READ4(sc, RXLENGTHERROR)); 359 360 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); 361 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); 362 if_inc_counter(ifp, IFCOUNTER_OERRORS, 363 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + 364 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); 365 366 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 367 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); 368 369 dwc_clear_stats(sc); 370 } 371 372 static void 373 dwc_tick(void *arg) 374 { 375 struct dwc_softc *sc; 376 struct ifnet *ifp; 377 int link_was_up; 378 379 sc = arg; 380 381 DWC_ASSERT_LOCKED(sc); 382 383 ifp = sc->ifp; 384 385 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 386 return; 387 388 /* 389 * Typical tx watchdog. If this fires it indicates that we enqueued 390 * packets for output and never got a txdone interrupt for them. Maybe 391 * it's a missed interrupt somehow, just pretend we got one. 392 */ 393 if (sc->tx_watchdog_count > 0) { 394 if (--sc->tx_watchdog_count == 0) { 395 dwc_txfinish_locked(sc); 396 } 397 } 398 399 /* Gather stats from hardware counters. */ 400 dwc_harvest_stats(sc); 401 402 /* Check the media status. */ 403 link_was_up = sc->link_is_up; 404 mii_tick(sc->mii_softc); 405 if (sc->link_is_up && !link_was_up) 406 dwc_txstart_locked(sc); 407 408 /* Schedule another check one second from now. */ 409 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 410 } 411 412 static void 413 dwc_init_locked(struct dwc_softc *sc) 414 { 415 struct ifnet *ifp = sc->ifp; 416 uint32_t reg; 417 418 DWC_ASSERT_LOCKED(sc); 419 420 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 421 return; 422 423 ifp->if_drv_flags |= IFF_DRV_RUNNING; 424 425 dwc_setup_rxfilter(sc); 426 427 /* Initializa DMA and enable transmitters */ 428 reg = READ4(sc, OPERATION_MODE); 429 reg |= (MODE_TSF | MODE_OSF | MODE_FUF); 430 reg &= ~(MODE_RSF); 431 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); 432 WRITE4(sc, OPERATION_MODE, reg); 433 434 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 435 436 /* Start DMA */ 437 reg = READ4(sc, OPERATION_MODE); 438 reg |= (MODE_ST | MODE_SR); 439 WRITE4(sc, OPERATION_MODE, reg); 440 441 /* Enable transmitters */ 442 reg = READ4(sc, MAC_CONFIGURATION); 443 reg |= (CONF_JD | CONF_ACS | CONF_BE); 444 reg |= (CONF_TE | CONF_RE); 445 WRITE4(sc, MAC_CONFIGURATION, reg); 446 447 /* 448 * Call mii_mediachg() which will call back into dwc_miibus_statchg() 449 * to set up the remaining config registers based on current media. 450 */ 451 mii_mediachg(sc->mii_softc); 452 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 453 } 454 455 static void 456 dwc_init(void *if_softc) 457 { 458 struct dwc_softc *sc = if_softc; 459 460 DWC_LOCK(sc); 461 dwc_init_locked(sc); 462 DWC_UNLOCK(sc); 463 } 464 465 inline static uint32_t 466 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) 467 { 468 uint32_t nidx; 469 470 sc->rxdesc_ring[idx].addr = (uint32_t)paddr; 471 nidx = next_rxidx(sc, idx); 472 sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \ 473 (nidx * sizeof(struct dwc_hwdesc)); 474 if (sc->mactype == DWC_GMAC_ALT_DESC) 475 sc->rxdesc_ring[idx].tdes1 = DDESC_CNTL_CHAINED | RX_MAX_PACKET; 476 else 477 sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; 478 479 wmb(); 480 sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; 481 wmb(); 482 483 return (nidx); 484 } 485 486 static int 487 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) 488 { 489 struct bus_dma_segment seg; 490 int error, nsegs; 491 492 m_adj(m, ETHER_ALIGN); 493 494 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 495 m, &seg, &nsegs, 0); 496 if (error != 0) { 497 return (error); 498 } 499 500 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 501 502 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 503 BUS_DMASYNC_PREREAD); 504 505 sc->rxbuf_map[idx].mbuf = m; 506 dwc_setup_rxdesc(sc, idx, seg.ds_addr); 507 508 return (0); 509 } 510 511 static struct mbuf * 512 dwc_alloc_mbufcl(struct dwc_softc *sc) 513 { 514 struct mbuf *m; 515 516 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 517 if (m != NULL) 518 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 519 520 return (m); 521 } 522 523 static void 524 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 525 { 526 struct dwc_softc *sc; 527 struct mii_data *mii; 528 529 sc = ifp->if_softc; 530 mii = sc->mii_softc; 531 DWC_LOCK(sc); 532 mii_pollstat(mii); 533 ifmr->ifm_active = mii->mii_media_active; 534 ifmr->ifm_status = mii->mii_media_status; 535 DWC_UNLOCK(sc); 536 } 537 538 static int 539 dwc_media_change_locked(struct dwc_softc *sc) 540 { 541 542 return (mii_mediachg(sc->mii_softc)); 543 } 544 545 static int 546 dwc_media_change(struct ifnet * ifp) 547 { 548 struct dwc_softc *sc; 549 int error; 550 551 sc = ifp->if_softc; 552 553 DWC_LOCK(sc); 554 error = dwc_media_change_locked(sc); 555 DWC_UNLOCK(sc); 556 return (error); 557 } 558 559 static const uint8_t nibbletab[] = { 560 /* 0x0 0000 -> 0000 */ 0x0, 561 /* 0x1 0001 -> 1000 */ 0x8, 562 /* 0x2 0010 -> 0100 */ 0x4, 563 /* 0x3 0011 -> 1100 */ 0xc, 564 /* 0x4 0100 -> 0010 */ 0x2, 565 /* 0x5 0101 -> 1010 */ 0xa, 566 /* 0x6 0110 -> 0110 */ 0x6, 567 /* 0x7 0111 -> 1110 */ 0xe, 568 /* 0x8 1000 -> 0001 */ 0x1, 569 /* 0x9 1001 -> 1001 */ 0x9, 570 /* 0xa 1010 -> 0101 */ 0x5, 571 /* 0xb 1011 -> 1101 */ 0xd, 572 /* 0xc 1100 -> 0011 */ 0x3, 573 /* 0xd 1101 -> 1011 */ 0xb, 574 /* 0xe 1110 -> 0111 */ 0x7, 575 /* 0xf 1111 -> 1111 */ 0xf, }; 576 577 static uint8_t 578 bitreverse(uint8_t x) 579 { 580 581 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; 582 } 583 584 static void 585 dwc_setup_rxfilter(struct dwc_softc *sc) 586 { 587 struct ifmultiaddr *ifma; 588 struct ifnet *ifp; 589 uint8_t *eaddr, val; 590 uint32_t crc, ffval, hashbit, hashreg, hi, lo, reg; 591 592 DWC_ASSERT_LOCKED(sc); 593 594 ifp = sc->ifp; 595 596 /* 597 * Set the multicast (group) filter hash. 598 */ 599 if ((ifp->if_flags & IFF_ALLMULTI)) 600 ffval = (FRAME_FILTER_PM); 601 else { 602 ffval = (FRAME_FILTER_HMC); 603 if_maddr_rlock(ifp); 604 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 605 if (ifma->ifma_addr->sa_family != AF_LINK) 606 continue; 607 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 608 ifma->ifma_addr), ETHER_ADDR_LEN); 609 610 /* Take lower 8 bits and reverse it */ 611 val = bitreverse(~crc & 0xff); 612 hashreg = (val >> 5); 613 hashbit = (val & 31); 614 615 reg = READ4(sc, HASH_TABLE_REG(hashreg)); 616 reg |= (1 << hashbit); 617 WRITE4(sc, HASH_TABLE_REG(hashreg), reg); 618 } 619 if_maddr_runlock(ifp); 620 } 621 622 /* 623 * Set the individual address filter hash. 624 */ 625 if (ifp->if_flags & IFF_PROMISC) 626 ffval |= (FRAME_FILTER_PR); 627 628 /* 629 * Set the primary address. 630 */ 631 eaddr = IF_LLADDR(ifp); 632 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 633 (eaddr[3] << 24); 634 hi = eaddr[4] | (eaddr[5] << 8); 635 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); 636 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); 637 WRITE4(sc, MAC_FRAME_FILTER, ffval); 638 } 639 640 static int 641 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 642 { 643 struct dwc_softc *sc; 644 struct mii_data *mii; 645 struct ifreq *ifr; 646 int mask, error; 647 648 sc = ifp->if_softc; 649 ifr = (struct ifreq *)data; 650 651 error = 0; 652 switch (cmd) { 653 case SIOCSIFFLAGS: 654 DWC_LOCK(sc); 655 if (ifp->if_flags & IFF_UP) { 656 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 657 if ((ifp->if_flags ^ sc->if_flags) & 658 (IFF_PROMISC | IFF_ALLMULTI)) 659 dwc_setup_rxfilter(sc); 660 } else { 661 if (!sc->is_detaching) 662 dwc_init_locked(sc); 663 } 664 } else { 665 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 666 dwc_stop_locked(sc); 667 } 668 sc->if_flags = ifp->if_flags; 669 DWC_UNLOCK(sc); 670 break; 671 case SIOCADDMULTI: 672 case SIOCDELMULTI: 673 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 674 DWC_LOCK(sc); 675 dwc_setup_rxfilter(sc); 676 DWC_UNLOCK(sc); 677 } 678 break; 679 case SIOCSIFMEDIA: 680 case SIOCGIFMEDIA: 681 mii = sc->mii_softc; 682 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 683 break; 684 case SIOCSIFCAP: 685 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 686 if (mask & IFCAP_VLAN_MTU) { 687 /* No work to do except acknowledge the change took */ 688 ifp->if_capenable ^= IFCAP_VLAN_MTU; 689 } 690 break; 691 692 default: 693 error = ether_ioctl(ifp, cmd, data); 694 break; 695 } 696 697 return (error); 698 } 699 700 static void 701 dwc_txfinish_locked(struct dwc_softc *sc) 702 { 703 struct dwc_bufmap *bmap; 704 struct dwc_hwdesc *desc; 705 struct ifnet *ifp; 706 707 DWC_ASSERT_LOCKED(sc); 708 709 ifp = sc->ifp; 710 while (sc->tx_idx_tail != sc->tx_idx_head) { 711 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 712 if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) 713 break; 714 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 715 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 716 BUS_DMASYNC_POSTWRITE); 717 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 718 m_freem(bmap->mbuf); 719 bmap->mbuf = NULL; 720 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 721 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 722 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 723 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 724 } 725 726 /* If there are no buffers outstanding, muzzle the watchdog. */ 727 if (sc->tx_idx_tail == sc->tx_idx_head) { 728 sc->tx_watchdog_count = 0; 729 } 730 } 731 732 static void 733 dwc_rxfinish_locked(struct dwc_softc *sc) 734 { 735 struct ifnet *ifp; 736 struct mbuf *m0; 737 struct mbuf *m; 738 int error, idx, len; 739 uint32_t rdes0; 740 741 ifp = sc->ifp; 742 743 for (;;) { 744 idx = sc->rx_idx; 745 746 rdes0 = sc->rxdesc_ring[idx].tdes0; 747 if ((rdes0 & DDESC_RDES0_OWN) != 0) 748 break; 749 750 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 751 BUS_DMASYNC_POSTREAD); 752 bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); 753 754 len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; 755 if (len != 0) { 756 m = sc->rxbuf_map[idx].mbuf; 757 m->m_pkthdr.rcvif = ifp; 758 m->m_pkthdr.len = len; 759 m->m_len = len; 760 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 761 762 DWC_UNLOCK(sc); 763 (*ifp->if_input)(ifp, m); 764 DWC_LOCK(sc); 765 } else { 766 /* XXX Zero-length packet ? */ 767 } 768 769 if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) { 770 if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { 771 /* 772 * XXX Now what? 773 * We've got a hole in the rx ring. 774 */ 775 } 776 } else 777 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 778 779 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 780 } 781 } 782 783 static void 784 dwc_intr(void *arg) 785 { 786 struct dwc_softc *sc; 787 uint32_t reg; 788 789 sc = arg; 790 791 DWC_LOCK(sc); 792 793 reg = READ4(sc, INTERRUPT_STATUS); 794 if (reg) 795 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); 796 797 reg = READ4(sc, DMA_STATUS); 798 if (reg & DMA_STATUS_NIS) { 799 if (reg & DMA_STATUS_RI) 800 dwc_rxfinish_locked(sc); 801 802 if (reg & DMA_STATUS_TI) { 803 dwc_txfinish_locked(sc); 804 dwc_txstart_locked(sc); 805 } 806 } 807 808 if (reg & DMA_STATUS_AIS) { 809 if (reg & DMA_STATUS_FBI) { 810 /* Fatal bus error */ 811 device_printf(sc->dev, 812 "Ethernet DMA error, restarting controller.\n"); 813 dwc_stop_locked(sc); 814 dwc_init_locked(sc); 815 } 816 } 817 818 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 819 DWC_UNLOCK(sc); 820 } 821 822 static int 823 setup_dma(struct dwc_softc *sc) 824 { 825 struct mbuf *m; 826 int error; 827 int nidx; 828 int idx; 829 830 /* 831 * Set up TX descriptor ring, descriptors, and dma maps. 832 */ 833 error = bus_dma_tag_create( 834 bus_get_dma_tag(sc->dev), /* Parent tag. */ 835 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 836 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 837 BUS_SPACE_MAXADDR, /* highaddr */ 838 NULL, NULL, /* filter, filterarg */ 839 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 840 TX_DESC_SIZE, /* maxsegsize */ 841 0, /* flags */ 842 NULL, NULL, /* lockfunc, lockarg */ 843 &sc->txdesc_tag); 844 if (error != 0) { 845 device_printf(sc->dev, 846 "could not create TX ring DMA tag.\n"); 847 goto out; 848 } 849 850 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 851 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 852 &sc->txdesc_map); 853 if (error != 0) { 854 device_printf(sc->dev, 855 "could not allocate TX descriptor ring.\n"); 856 goto out; 857 } 858 859 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, 860 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, 861 &sc->txdesc_ring_paddr, 0); 862 if (error != 0) { 863 device_printf(sc->dev, 864 "could not load TX descriptor ring map.\n"); 865 goto out; 866 } 867 868 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 869 nidx = next_txidx(sc, idx); 870 sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + 871 (nidx * sizeof(struct dwc_hwdesc)); 872 } 873 874 error = bus_dma_tag_create( 875 bus_get_dma_tag(sc->dev), /* Parent tag. */ 876 1, 0, /* alignment, boundary */ 877 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 878 BUS_SPACE_MAXADDR, /* highaddr */ 879 NULL, NULL, /* filter, filterarg */ 880 MCLBYTES, 1, /* maxsize, nsegments */ 881 MCLBYTES, /* maxsegsize */ 882 0, /* flags */ 883 NULL, NULL, /* lockfunc, lockarg */ 884 &sc->txbuf_tag); 885 if (error != 0) { 886 device_printf(sc->dev, 887 "could not create TX ring DMA tag.\n"); 888 goto out; 889 } 890 891 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 892 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, 893 &sc->txbuf_map[idx].map); 894 if (error != 0) { 895 device_printf(sc->dev, 896 "could not create TX buffer DMA map.\n"); 897 goto out; 898 } 899 dwc_setup_txdesc(sc, idx, 0, 0); 900 } 901 902 /* 903 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 904 */ 905 error = bus_dma_tag_create( 906 bus_get_dma_tag(sc->dev), /* Parent tag. */ 907 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 908 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 909 BUS_SPACE_MAXADDR, /* highaddr */ 910 NULL, NULL, /* filter, filterarg */ 911 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 912 RX_DESC_SIZE, /* maxsegsize */ 913 0, /* flags */ 914 NULL, NULL, /* lockfunc, lockarg */ 915 &sc->rxdesc_tag); 916 if (error != 0) { 917 device_printf(sc->dev, 918 "could not create RX ring DMA tag.\n"); 919 goto out; 920 } 921 922 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 923 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 924 &sc->rxdesc_map); 925 if (error != 0) { 926 device_printf(sc->dev, 927 "could not allocate RX descriptor ring.\n"); 928 goto out; 929 } 930 931 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, 932 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, 933 &sc->rxdesc_ring_paddr, 0); 934 if (error != 0) { 935 device_printf(sc->dev, 936 "could not load RX descriptor ring map.\n"); 937 goto out; 938 } 939 940 error = bus_dma_tag_create( 941 bus_get_dma_tag(sc->dev), /* Parent tag. */ 942 1, 0, /* alignment, boundary */ 943 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 944 BUS_SPACE_MAXADDR, /* highaddr */ 945 NULL, NULL, /* filter, filterarg */ 946 MCLBYTES, 1, /* maxsize, nsegments */ 947 MCLBYTES, /* maxsegsize */ 948 0, /* flags */ 949 NULL, NULL, /* lockfunc, lockarg */ 950 &sc->rxbuf_tag); 951 if (error != 0) { 952 device_printf(sc->dev, 953 "could not create RX buf DMA tag.\n"); 954 goto out; 955 } 956 957 for (idx = 0; idx < RX_DESC_COUNT; idx++) { 958 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, 959 &sc->rxbuf_map[idx].map); 960 if (error != 0) { 961 device_printf(sc->dev, 962 "could not create RX buffer DMA map.\n"); 963 goto out; 964 } 965 if ((m = dwc_alloc_mbufcl(sc)) == NULL) { 966 device_printf(sc->dev, "Could not alloc mbuf\n"); 967 error = ENOMEM; 968 goto out; 969 } 970 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { 971 device_printf(sc->dev, 972 "could not create new RX buffer.\n"); 973 goto out; 974 } 975 } 976 977 out: 978 if (error != 0) 979 return (ENXIO); 980 981 return (0); 982 } 983 984 static int 985 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) 986 { 987 uint32_t hi, lo, rnd; 988 989 /* 990 * Try to recover a MAC address from the running hardware. If there's 991 * something non-zero there, assume the bootloader did the right thing 992 * and just use it. 993 * 994 * Otherwise, set the address to a convenient locally assigned address, 995 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 996 * assigned bit set, and the broadcast/multicast bit clear. 997 */ 998 lo = READ4(sc, MAC_ADDRESS_LOW(0)); 999 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; 1000 if ((lo != 0xffffffff) || (hi != 0xffff)) { 1001 hwaddr[0] = (lo >> 0) & 0xff; 1002 hwaddr[1] = (lo >> 8) & 0xff; 1003 hwaddr[2] = (lo >> 16) & 0xff; 1004 hwaddr[3] = (lo >> 24) & 0xff; 1005 hwaddr[4] = (hi >> 0) & 0xff; 1006 hwaddr[5] = (hi >> 8) & 0xff; 1007 } else { 1008 rnd = arc4random() & 0x00ffffff; 1009 hwaddr[0] = 'b'; 1010 hwaddr[1] = 's'; 1011 hwaddr[2] = 'd'; 1012 hwaddr[3] = rnd >> 16; 1013 hwaddr[4] = rnd >> 8; 1014 hwaddr[5] = rnd >> 0; 1015 } 1016 1017 return (0); 1018 } 1019 1020 #define GPIO_ACTIVE_LOW 1 1021 1022 static int 1023 dwc_reset(device_t dev) 1024 { 1025 pcell_t gpio_prop[4]; 1026 pcell_t delay_prop[3]; 1027 phandle_t node, gpio_node; 1028 device_t gpio; 1029 uint32_t pin, flags; 1030 uint32_t pin_value; 1031 1032 node = ofw_bus_get_node(dev); 1033 if (OF_getencprop(node, "snps,reset-gpio", 1034 gpio_prop, sizeof(gpio_prop)) <= 0) 1035 return (0); 1036 1037 if (OF_getencprop(node, "snps,reset-delays-us", 1038 delay_prop, sizeof(delay_prop)) <= 0) { 1039 device_printf(dev, 1040 "Wrong property for snps,reset-delays-us"); 1041 return (ENXIO); 1042 } 1043 1044 gpio_node = OF_node_from_xref(gpio_prop[0]); 1045 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) { 1046 device_printf(dev, 1047 "Can't find gpio controller for phy reset\n"); 1048 return (ENXIO); 1049 } 1050 1051 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, 1052 nitems(gpio_prop) - 1, 1053 gpio_prop + 1, &pin, &flags) != 0) { 1054 device_printf(dev, "Can't map gpio for phy reset\n"); 1055 return (ENXIO); 1056 } 1057 1058 pin_value = GPIO_PIN_LOW; 1059 if (OF_hasprop(node, "snps,reset-active-low")) 1060 pin_value = GPIO_PIN_HIGH; 1061 1062 if (flags & GPIO_ACTIVE_LOW) 1063 pin_value = !pin_value; 1064 1065 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); 1066 GPIO_PIN_SET(gpio, pin, pin_value); 1067 DELAY(delay_prop[0]); 1068 GPIO_PIN_SET(gpio, pin, !pin_value); 1069 DELAY(delay_prop[1]); 1070 GPIO_PIN_SET(gpio, pin, pin_value); 1071 DELAY(delay_prop[2]); 1072 1073 return (0); 1074 } 1075 1076 #ifdef EXT_RESOURCES 1077 static int 1078 dwc_clock_init(device_t dev) 1079 { 1080 hwreset_t rst; 1081 clk_t clk; 1082 int error; 1083 1084 /* Enable clock */ 1085 if (clk_get_by_ofw_name(dev, "stmmaceth", &clk) == 0) { 1086 error = clk_enable(clk); 1087 if (error != 0) { 1088 device_printf(dev, "could not enable main clock\n"); 1089 return (error); 1090 } 1091 } 1092 1093 /* De-assert reset */ 1094 if (hwreset_get_by_ofw_name(dev, "stmmaceth", &rst) == 0) { 1095 error = hwreset_deassert(rst); 1096 if (error != 0) { 1097 device_printf(dev, "could not de-assert reset\n"); 1098 return (error); 1099 } 1100 } 1101 1102 return (0); 1103 } 1104 #endif 1105 1106 static int 1107 dwc_probe(device_t dev) 1108 { 1109 1110 if (!ofw_bus_status_okay(dev)) 1111 return (ENXIO); 1112 1113 if (!ofw_bus_is_compatible(dev, "snps,dwmac")) 1114 return (ENXIO); 1115 1116 device_set_desc(dev, "Gigabit Ethernet Controller"); 1117 return (BUS_PROBE_DEFAULT); 1118 } 1119 1120 static int 1121 dwc_attach(device_t dev) 1122 { 1123 uint8_t macaddr[ETHER_ADDR_LEN]; 1124 struct dwc_softc *sc; 1125 struct ifnet *ifp; 1126 int error, i; 1127 uint32_t reg; 1128 1129 sc = device_get_softc(dev); 1130 sc->dev = dev; 1131 sc->rx_idx = 0; 1132 sc->txcount = TX_DESC_COUNT; 1133 sc->mii_clk = IF_DWC_MII_CLK(dev); 1134 sc->mactype = IF_DWC_MAC_TYPE(dev); 1135 1136 if (IF_DWC_INIT(dev) != 0) 1137 return (ENXIO); 1138 1139 #ifdef EXT_RESOURCES 1140 if (dwc_clock_init(dev) != 0) 1141 return (ENXIO); 1142 #endif 1143 1144 if (bus_alloc_resources(dev, dwc_spec, sc->res)) { 1145 device_printf(dev, "could not allocate resources\n"); 1146 return (ENXIO); 1147 } 1148 1149 /* Memory interface */ 1150 sc->bst = rman_get_bustag(sc->res[0]); 1151 sc->bsh = rman_get_bushandle(sc->res[0]); 1152 1153 /* Read MAC before reset */ 1154 if (dwc_get_hwaddr(sc, macaddr)) { 1155 device_printf(sc->dev, "can't get mac\n"); 1156 return (ENXIO); 1157 } 1158 1159 /* Reset the PHY if needed */ 1160 if (dwc_reset(dev) != 0) { 1161 device_printf(dev, "Can't reset the PHY\n"); 1162 return (ENXIO); 1163 } 1164 1165 /* Reset */ 1166 reg = READ4(sc, BUS_MODE); 1167 reg |= (BUS_MODE_SWR); 1168 WRITE4(sc, BUS_MODE, reg); 1169 1170 for (i = 0; i < MAC_RESET_TIMEOUT; i++) { 1171 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 1172 break; 1173 DELAY(10); 1174 } 1175 if (i >= MAC_RESET_TIMEOUT) { 1176 device_printf(sc->dev, "Can't reset DWC.\n"); 1177 return (ENXIO); 1178 } 1179 1180 if (sc->mactype == DWC_GMAC_ALT_DESC) { 1181 reg = BUS_MODE_FIXEDBURST; 1182 reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT); 1183 } else 1184 reg = (BUS_MODE_EIGHTXPBL); 1185 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); 1186 WRITE4(sc, BUS_MODE, reg); 1187 1188 /* 1189 * DMA must be stop while changing descriptor list addresses. 1190 */ 1191 reg = READ4(sc, OPERATION_MODE); 1192 reg &= ~(MODE_ST | MODE_SR); 1193 WRITE4(sc, OPERATION_MODE, reg); 1194 1195 if (setup_dma(sc)) 1196 return (ENXIO); 1197 1198 /* Setup addresses */ 1199 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 1200 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 1201 1202 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), 1203 MTX_NETWORK_LOCK, MTX_DEF); 1204 1205 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); 1206 1207 /* Setup interrupt handler. */ 1208 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 1209 NULL, dwc_intr, sc, &sc->intr_cookie); 1210 if (error != 0) { 1211 device_printf(dev, "could not setup interrupt handler.\n"); 1212 return (ENXIO); 1213 } 1214 1215 /* Set up the ethernet interface. */ 1216 sc->ifp = ifp = if_alloc(IFT_ETHER); 1217 1218 ifp->if_softc = sc; 1219 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1220 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1221 ifp->if_capabilities = IFCAP_VLAN_MTU; 1222 ifp->if_capenable = ifp->if_capabilities; 1223 ifp->if_start = dwc_txstart; 1224 ifp->if_ioctl = dwc_ioctl; 1225 ifp->if_init = dwc_init; 1226 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1227 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1228 IFQ_SET_READY(&ifp->if_snd); 1229 1230 /* Attach the mii driver. */ 1231 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, 1232 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 1233 MII_OFFSET_ANY, 0); 1234 1235 if (error != 0) { 1236 device_printf(dev, "PHY attach failed\n"); 1237 return (ENXIO); 1238 } 1239 sc->mii_softc = device_get_softc(sc->miibus); 1240 1241 /* All ready to run, attach the ethernet interface. */ 1242 ether_ifattach(ifp, macaddr); 1243 sc->is_attached = true; 1244 1245 return (0); 1246 } 1247 1248 static int 1249 dwc_miibus_read_reg(device_t dev, int phy, int reg) 1250 { 1251 struct dwc_softc *sc; 1252 uint16_t mii; 1253 size_t cnt; 1254 int rv = 0; 1255 1256 sc = device_get_softc(dev); 1257 1258 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1259 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1260 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1261 | GMII_ADDRESS_GB; /* Busy flag */ 1262 1263 WRITE4(sc, GMII_ADDRESS, mii); 1264 1265 for (cnt = 0; cnt < 1000; cnt++) { 1266 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1267 rv = READ4(sc, GMII_DATA); 1268 break; 1269 } 1270 DELAY(10); 1271 } 1272 1273 return rv; 1274 } 1275 1276 static int 1277 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) 1278 { 1279 struct dwc_softc *sc; 1280 uint16_t mii; 1281 size_t cnt; 1282 1283 sc = device_get_softc(dev); 1284 1285 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1286 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1287 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1288 | GMII_ADDRESS_GB | GMII_ADDRESS_GW; 1289 1290 WRITE4(sc, GMII_DATA, val); 1291 WRITE4(sc, GMII_ADDRESS, mii); 1292 1293 for (cnt = 0; cnt < 1000; cnt++) { 1294 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1295 break; 1296 } 1297 DELAY(10); 1298 } 1299 1300 return (0); 1301 } 1302 1303 static void 1304 dwc_miibus_statchg(device_t dev) 1305 { 1306 struct dwc_softc *sc; 1307 struct mii_data *mii; 1308 uint32_t reg; 1309 1310 /* 1311 * Called by the MII bus driver when the PHY establishes 1312 * link to set the MAC interface registers. 1313 */ 1314 1315 sc = device_get_softc(dev); 1316 1317 DWC_ASSERT_LOCKED(sc); 1318 1319 mii = sc->mii_softc; 1320 1321 if (mii->mii_media_status & IFM_ACTIVE) 1322 sc->link_is_up = true; 1323 else 1324 sc->link_is_up = false; 1325 1326 reg = READ4(sc, MAC_CONFIGURATION); 1327 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1328 case IFM_1000_T: 1329 case IFM_1000_SX: 1330 reg &= ~(CONF_FES | CONF_PS); 1331 break; 1332 case IFM_100_TX: 1333 reg |= (CONF_FES | CONF_PS); 1334 break; 1335 case IFM_10_T: 1336 reg &= ~(CONF_FES); 1337 reg |= (CONF_PS); 1338 break; 1339 case IFM_NONE: 1340 sc->link_is_up = false; 1341 return; 1342 default: 1343 sc->link_is_up = false; 1344 device_printf(dev, "Unsupported media %u\n", 1345 IFM_SUBTYPE(mii->mii_media_active)); 1346 return; 1347 } 1348 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1349 reg |= (CONF_DM); 1350 else 1351 reg &= ~(CONF_DM); 1352 WRITE4(sc, MAC_CONFIGURATION, reg); 1353 } 1354 1355 static device_method_t dwc_methods[] = { 1356 DEVMETHOD(device_probe, dwc_probe), 1357 DEVMETHOD(device_attach, dwc_attach), 1358 1359 /* MII Interface */ 1360 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), 1361 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), 1362 DEVMETHOD(miibus_statchg, dwc_miibus_statchg), 1363 1364 { 0, 0 } 1365 }; 1366 1367 driver_t dwc_driver = { 1368 "dwc", 1369 dwc_methods, 1370 sizeof(struct dwc_softc), 1371 }; 1372 1373 static devclass_t dwc_devclass; 1374 1375 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); 1376 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); 1377 1378 MODULE_DEPEND(dwc, ether, 1, 1, 1); 1379 MODULE_DEPEND(dwc, miibus, 1, 1, 1); 1380