xref: /freebsd/sys/dev/dwc/if_dwc.c (revision 6966ac055c3b7a39266fb982493330df7a097997)
1 /*-
2  * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3  * All rights reserved.
4  *
5  * This software was developed by SRI International and the University of
6  * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7  * ("CTSRD"), as part of the DARPA CRASH research programme.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  */
30 
31 /*
32  * Ethernet media access controller (EMAC)
33  * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
34  *
35  * EMAC is an instance of the Synopsys DesignWare 3504-0
36  * Universal 10/100/1000 Ethernet MAC (DWC_gmac).
37  */
38 
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
41 
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/bus.h>
45 #include <sys/gpio.h>
46 #include <sys/kernel.h>
47 #include <sys/lock.h>
48 #include <sys/malloc.h>
49 #include <sys/mbuf.h>
50 #include <sys/module.h>
51 #include <sys/mutex.h>
52 #include <sys/rman.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 
56 #include <net/bpf.h>
57 #include <net/if.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_var.h>
63 
64 #include <machine/bus.h>
65 
66 #include <dev/dwc/if_dwc.h>
67 #include <dev/dwc/if_dwcvar.h>
68 #include <dev/mii/mii.h>
69 #include <dev/mii/miivar.h>
70 #include <dev/ofw/ofw_bus.h>
71 #include <dev/ofw/ofw_bus_subr.h>
72 
73 #ifdef EXT_RESOURCES
74 #include <dev/extres/clk/clk.h>
75 #include <dev/extres/hwreset/hwreset.h>
76 #endif
77 
78 #include "if_dwc_if.h"
79 #include "gpio_if.h"
80 #include "miibus_if.h"
81 
82 #define	READ4(_sc, _reg) \
83 	bus_read_4((_sc)->res[0], _reg)
84 #define	WRITE4(_sc, _reg, _val) \
85 	bus_write_4((_sc)->res[0], _reg, _val)
86 
87 #define	MAC_RESET_TIMEOUT	100
88 #define	WATCHDOG_TIMEOUT_SECS	5
89 #define	STATS_HARVEST_INTERVAL	2
90 
91 #define	DWC_LOCK(sc)			mtx_lock(&(sc)->mtx)
92 #define	DWC_UNLOCK(sc)			mtx_unlock(&(sc)->mtx)
93 #define	DWC_ASSERT_LOCKED(sc)		mtx_assert(&(sc)->mtx, MA_OWNED)
94 #define	DWC_ASSERT_UNLOCKED(sc)		mtx_assert(&(sc)->mtx, MA_NOTOWNED)
95 
96 #define	DDESC_TDES0_OWN			(1U << 31)
97 #define	DDESC_TDES0_TXINT		(1U << 30)
98 #define	DDESC_TDES0_TXLAST		(1U << 29)
99 #define	DDESC_TDES0_TXFIRST		(1U << 28)
100 #define	DDESC_TDES0_TXCRCDIS		(1U << 27)
101 #define	DDESC_TDES0_TXRINGEND		(1U << 21)
102 #define	DDESC_TDES0_TXCHAIN		(1U << 20)
103 
104 #define	DDESC_RDES0_OWN			(1U << 31)
105 #define	DDESC_RDES0_FL_MASK		0x3fff
106 #define	DDESC_RDES0_FL_SHIFT		16	/* Frame Length */
107 #define	DDESC_RDES1_CHAINED		(1U << 14)
108 
109 /* Alt descriptor bits. */
110 #define	DDESC_CNTL_TXINT		(1U << 31)
111 #define	DDESC_CNTL_TXLAST		(1U << 30)
112 #define	DDESC_CNTL_TXFIRST		(1U << 29)
113 #define	DDESC_CNTL_TXCRCDIS		(1U << 26)
114 #define	DDESC_CNTL_TXRINGEND		(1U << 25)
115 #define	DDESC_CNTL_TXCHAIN		(1U << 24)
116 
117 #define	DDESC_CNTL_CHAINED		(1U << 24)
118 
119 /*
120  * A hardware buffer descriptor.  Rx and Tx buffers have the same descriptor
121  * layout, but the bits in the fields have different meanings.
122  */
123 struct dwc_hwdesc
124 {
125 	uint32_t tdes0;		/* status for alt layout */
126 	uint32_t tdes1;		/* cntl for alt layout */
127 	uint32_t addr;		/* pointer to buffer data */
128 	uint32_t addr_next;	/* link to next descriptor */
129 };
130 
131 /*
132  * The hardware imposes alignment restrictions on various objects involved in
133  * DMA transfers.  These values are expressed in bytes (not bits).
134  */
135 #define	DWC_DESC_RING_ALIGN		2048
136 
137 static struct resource_spec dwc_spec[] = {
138 	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
139 	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
140 	{ -1, 0 }
141 };
142 
143 static void dwc_txfinish_locked(struct dwc_softc *sc);
144 static void dwc_rxfinish_locked(struct dwc_softc *sc);
145 static void dwc_stop_locked(struct dwc_softc *sc);
146 static void dwc_setup_rxfilter(struct dwc_softc *sc);
147 
148 static inline uint32_t
149 next_rxidx(struct dwc_softc *sc, uint32_t curidx)
150 {
151 
152 	return ((curidx + 1) % RX_DESC_COUNT);
153 }
154 
155 static inline uint32_t
156 next_txidx(struct dwc_softc *sc, uint32_t curidx)
157 {
158 
159 	return ((curidx + 1) % TX_DESC_COUNT);
160 }
161 
162 static void
163 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
164 {
165 
166 	if (error != 0)
167 		return;
168 	*(bus_addr_t *)arg = segs[0].ds_addr;
169 }
170 
171 inline static uint32_t
172 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr,
173     uint32_t len)
174 {
175 	uint32_t flags;
176 	uint32_t nidx;
177 
178 	nidx = next_txidx(sc, idx);
179 
180 	/* Addr/len 0 means we're clearing the descriptor after xmit done. */
181 	if (paddr == 0 || len == 0) {
182 		flags = 0;
183 		--sc->txcount;
184 	} else {
185 		if (sc->mactype == DWC_GMAC_ALT_DESC)
186 			flags = DDESC_CNTL_TXCHAIN | DDESC_CNTL_TXFIRST
187 			    | DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT;
188 		else
189 			flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST
190 			    | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT;
191 		++sc->txcount;
192 	}
193 
194 	sc->txdesc_ring[idx].addr = (uint32_t)(paddr);
195 	if (sc->mactype == DWC_GMAC_ALT_DESC) {
196 		sc->txdesc_ring[idx].tdes0 = 0;
197 		sc->txdesc_ring[idx].tdes1 = flags | len;
198 	} else {
199 		sc->txdesc_ring[idx].tdes0 = flags;
200 		sc->txdesc_ring[idx].tdes1 = len;
201 	}
202 
203 	if (paddr && len) {
204 		wmb();
205 		sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN;
206 		wmb();
207 	}
208 
209 	return (nidx);
210 }
211 
212 static int
213 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp)
214 {
215 	struct bus_dma_segment seg;
216 	int error, nsegs;
217 	struct mbuf * m;
218 
219 	if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
220 		return (ENOMEM);
221 	*mp = m;
222 
223 	error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
224 	    m, &seg, &nsegs, 0);
225 	if (error != 0) {
226 		return (ENOMEM);
227 	}
228 
229 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
230 
231 	bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
232 	    BUS_DMASYNC_PREWRITE);
233 
234 	sc->txbuf_map[idx].mbuf = m;
235 
236 	dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
237 
238 	return (0);
239 }
240 
241 static void
242 dwc_txstart_locked(struct dwc_softc *sc)
243 {
244 	struct ifnet *ifp;
245 	struct mbuf *m;
246 	int enqueued;
247 
248 	DWC_ASSERT_LOCKED(sc);
249 
250 	if (!sc->link_is_up)
251 		return;
252 
253 	ifp = sc->ifp;
254 
255 	if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
256 		return;
257 	}
258 
259 	enqueued = 0;
260 
261 	for (;;) {
262 		if (sc->txcount == (TX_DESC_COUNT-1)) {
263 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
264 			break;
265 		}
266 
267 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
268 		if (m == NULL)
269 			break;
270 		if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
271 			IFQ_DRV_PREPEND(&ifp->if_snd, m);
272 			break;
273 		}
274 		BPF_MTAP(ifp, m);
275 		sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
276 		++enqueued;
277 	}
278 
279 	if (enqueued != 0) {
280 		WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1);
281 		sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
282 	}
283 }
284 
285 static void
286 dwc_txstart(struct ifnet *ifp)
287 {
288 	struct dwc_softc *sc = ifp->if_softc;
289 
290 	DWC_LOCK(sc);
291 	dwc_txstart_locked(sc);
292 	DWC_UNLOCK(sc);
293 }
294 
295 static void
296 dwc_stop_locked(struct dwc_softc *sc)
297 {
298 	struct ifnet *ifp;
299 	uint32_t reg;
300 
301 	DWC_ASSERT_LOCKED(sc);
302 
303 	ifp = sc->ifp;
304 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
305 	sc->tx_watchdog_count = 0;
306 	sc->stats_harvest_count = 0;
307 
308 	callout_stop(&sc->dwc_callout);
309 
310 	/* Stop DMA TX */
311 	reg = READ4(sc, OPERATION_MODE);
312 	reg &= ~(MODE_ST);
313 	WRITE4(sc, OPERATION_MODE, reg);
314 
315 	/* Flush TX */
316 	reg = READ4(sc, OPERATION_MODE);
317 	reg |= (MODE_FTF);
318 	WRITE4(sc, OPERATION_MODE, reg);
319 
320 	/* Stop transmitters */
321 	reg = READ4(sc, MAC_CONFIGURATION);
322 	reg &= ~(CONF_TE | CONF_RE);
323 	WRITE4(sc, MAC_CONFIGURATION, reg);
324 
325 	/* Stop DMA RX */
326 	reg = READ4(sc, OPERATION_MODE);
327 	reg &= ~(MODE_SR);
328 	WRITE4(sc, OPERATION_MODE, reg);
329 }
330 
331 static void dwc_clear_stats(struct dwc_softc *sc)
332 {
333 	uint32_t reg;
334 
335 	reg = READ4(sc, MMC_CONTROL);
336 	reg |= (MMC_CONTROL_CNTRST);
337 	WRITE4(sc, MMC_CONTROL, reg);
338 }
339 
340 static void
341 dwc_harvest_stats(struct dwc_softc *sc)
342 {
343 	struct ifnet *ifp;
344 
345 	/* We don't need to harvest too often. */
346 	if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
347 		return;
348 
349 	sc->stats_harvest_count = 0;
350 	ifp = sc->ifp;
351 
352 	if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB));
353 	if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G));
354 	if_inc_counter(ifp, IFCOUNTER_IERRORS,
355 	    READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) +
356 	    READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) +
357 	    READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) +
358 	    READ4(sc, RXLENGTHERROR));
359 
360 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G));
361 	if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G));
362 	if_inc_counter(ifp, IFCOUNTER_OERRORS,
363 	    READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) +
364 	    READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR));
365 
366 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
367 	    READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL));
368 
369 	dwc_clear_stats(sc);
370 }
371 
372 static void
373 dwc_tick(void *arg)
374 {
375 	struct dwc_softc *sc;
376 	struct ifnet *ifp;
377 	int link_was_up;
378 
379 	sc = arg;
380 
381 	DWC_ASSERT_LOCKED(sc);
382 
383 	ifp = sc->ifp;
384 
385 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
386 	    return;
387 
388 	/*
389 	 * Typical tx watchdog.  If this fires it indicates that we enqueued
390 	 * packets for output and never got a txdone interrupt for them.  Maybe
391 	 * it's a missed interrupt somehow, just pretend we got one.
392 	 */
393 	if (sc->tx_watchdog_count > 0) {
394 		if (--sc->tx_watchdog_count == 0) {
395 			dwc_txfinish_locked(sc);
396 		}
397 	}
398 
399 	/* Gather stats from hardware counters. */
400 	dwc_harvest_stats(sc);
401 
402 	/* Check the media status. */
403 	link_was_up = sc->link_is_up;
404 	mii_tick(sc->mii_softc);
405 	if (sc->link_is_up && !link_was_up)
406 		dwc_txstart_locked(sc);
407 
408 	/* Schedule another check one second from now. */
409 	callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
410 }
411 
412 static void
413 dwc_init_locked(struct dwc_softc *sc)
414 {
415 	struct ifnet *ifp = sc->ifp;
416 	uint32_t reg;
417 
418 	DWC_ASSERT_LOCKED(sc);
419 
420 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
421 		return;
422 
423 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
424 
425 	dwc_setup_rxfilter(sc);
426 
427 	/* Initializa DMA and enable transmitters */
428 	reg = READ4(sc, OPERATION_MODE);
429 	reg |= (MODE_TSF | MODE_OSF | MODE_FUF);
430 	reg &= ~(MODE_RSF);
431 	reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
432 	WRITE4(sc, OPERATION_MODE, reg);
433 
434 	WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
435 
436 	/* Start DMA */
437 	reg = READ4(sc, OPERATION_MODE);
438 	reg |= (MODE_ST | MODE_SR);
439 	WRITE4(sc, OPERATION_MODE, reg);
440 
441 	/* Enable transmitters */
442 	reg = READ4(sc, MAC_CONFIGURATION);
443 	reg |= (CONF_JD | CONF_ACS | CONF_BE);
444 	reg |= (CONF_TE | CONF_RE);
445 	WRITE4(sc, MAC_CONFIGURATION, reg);
446 
447 	/*
448 	 * Call mii_mediachg() which will call back into dwc_miibus_statchg()
449 	 * to set up the remaining config registers based on current media.
450 	 */
451 	mii_mediachg(sc->mii_softc);
452 	callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
453 }
454 
455 static void
456 dwc_init(void *if_softc)
457 {
458 	struct dwc_softc *sc = if_softc;
459 
460 	DWC_LOCK(sc);
461 	dwc_init_locked(sc);
462 	DWC_UNLOCK(sc);
463 }
464 
465 inline static uint32_t
466 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr)
467 {
468 	uint32_t nidx;
469 
470 	sc->rxdesc_ring[idx].addr = (uint32_t)paddr;
471 	nidx = next_rxidx(sc, idx);
472 	sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr +	\
473 	    (nidx * sizeof(struct dwc_hwdesc));
474 	if (sc->mactype == DWC_GMAC_ALT_DESC)
475 		sc->rxdesc_ring[idx].tdes1 = DDESC_CNTL_CHAINED | RX_MAX_PACKET;
476 	else
477 		sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES;
478 
479 	wmb();
480 	sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN;
481 	wmb();
482 
483 	return (nidx);
484 }
485 
486 static int
487 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m)
488 {
489 	struct bus_dma_segment seg;
490 	int error, nsegs;
491 
492 	m_adj(m, ETHER_ALIGN);
493 
494 	error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
495 	    m, &seg, &nsegs, 0);
496 	if (error != 0) {
497 		return (error);
498 	}
499 
500 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
501 
502 	bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
503 	    BUS_DMASYNC_PREREAD);
504 
505 	sc->rxbuf_map[idx].mbuf = m;
506 	dwc_setup_rxdesc(sc, idx, seg.ds_addr);
507 
508 	return (0);
509 }
510 
511 static struct mbuf *
512 dwc_alloc_mbufcl(struct dwc_softc *sc)
513 {
514 	struct mbuf *m;
515 
516 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
517 	if (m != NULL)
518 		m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
519 
520 	return (m);
521 }
522 
523 static void
524 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
525 {
526 	struct dwc_softc *sc;
527 	struct mii_data *mii;
528 
529 	sc = ifp->if_softc;
530 	mii = sc->mii_softc;
531 	DWC_LOCK(sc);
532 	mii_pollstat(mii);
533 	ifmr->ifm_active = mii->mii_media_active;
534 	ifmr->ifm_status = mii->mii_media_status;
535 	DWC_UNLOCK(sc);
536 }
537 
538 static int
539 dwc_media_change_locked(struct dwc_softc *sc)
540 {
541 
542 	return (mii_mediachg(sc->mii_softc));
543 }
544 
545 static int
546 dwc_media_change(struct ifnet * ifp)
547 {
548 	struct dwc_softc *sc;
549 	int error;
550 
551 	sc = ifp->if_softc;
552 
553 	DWC_LOCK(sc);
554 	error = dwc_media_change_locked(sc);
555 	DWC_UNLOCK(sc);
556 	return (error);
557 }
558 
559 static const uint8_t nibbletab[] = {
560 	/* 0x0 0000 -> 0000 */  0x0,
561 	/* 0x1 0001 -> 1000 */  0x8,
562 	/* 0x2 0010 -> 0100 */  0x4,
563 	/* 0x3 0011 -> 1100 */  0xc,
564 	/* 0x4 0100 -> 0010 */  0x2,
565 	/* 0x5 0101 -> 1010 */  0xa,
566 	/* 0x6 0110 -> 0110 */  0x6,
567 	/* 0x7 0111 -> 1110 */  0xe,
568 	/* 0x8 1000 -> 0001 */  0x1,
569 	/* 0x9 1001 -> 1001 */  0x9,
570 	/* 0xa 1010 -> 0101 */  0x5,
571 	/* 0xb 1011 -> 1101 */  0xd,
572 	/* 0xc 1100 -> 0011 */  0x3,
573 	/* 0xd 1101 -> 1011 */  0xb,
574 	/* 0xe 1110 -> 0111 */  0x7,
575 	/* 0xf 1111 -> 1111 */  0xf, };
576 
577 static uint8_t
578 bitreverse(uint8_t x)
579 {
580 
581 	return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4];
582 }
583 
584 struct dwc_hash_maddr_ctx {
585 	struct dwc_softc *sc;
586 	uint32_t hash[8];
587 };
588 
589 static u_int
590 dwc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
591 {
592 	struct dwc_hash_maddr_ctx *ctx = arg;
593 	uint32_t crc, hashbit, hashreg;
594 	uint8_t val;
595 
596 	crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN);
597 	/* Take lower 8 bits and reverse it */
598 	val = bitreverse(~crc & 0xff);
599 	if (ctx->sc->mactype == DWC_GMAC_ALT_DESC)
600 		val >>= 2; /* Only need lower 6 bits */
601 	hashreg = (val >> 5);
602 	hashbit = (val & 31);
603 	ctx->hash[hashreg] |= (1 << hashbit);
604 
605 	return (1);
606 }
607 
608 static void
609 dwc_setup_rxfilter(struct dwc_softc *sc)
610 {
611 	struct dwc_hash_maddr_ctx ctx;
612 	struct ifnet *ifp;
613 	uint8_t *eaddr;
614 	uint32_t ffval, hi, lo;
615 	int nhash, i;
616 
617 	DWC_ASSERT_LOCKED(sc);
618 
619 	ifp = sc->ifp;
620 	nhash = sc->mactype == DWC_GMAC_ALT_DESC ? 2 : 8;
621 
622 	/*
623 	 * Set the multicast (group) filter hash.
624 	 */
625 	if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
626 		ffval = (FRAME_FILTER_PM);
627 		for (i = 0; i < nhash; i++)
628 			ctx.hash[i] = ~0;
629 	} else {
630 		ffval = (FRAME_FILTER_HMC);
631 		for (i = 0; i < nhash; i++)
632 			ctx.hash[i] = 0;
633 		ctx.sc = sc;
634 		if_foreach_llmaddr(ifp, dwc_hash_maddr, &ctx);
635 	}
636 
637 	/*
638 	 * Set the individual address filter hash.
639 	 */
640 	if (ifp->if_flags & IFF_PROMISC)
641 		ffval |= (FRAME_FILTER_PR);
642 
643 	/*
644 	 * Set the primary address.
645 	 */
646 	eaddr = IF_LLADDR(ifp);
647 	lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) |
648 	    (eaddr[3] << 24);
649 	hi = eaddr[4] | (eaddr[5] << 8);
650 	WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
651 	WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
652 	WRITE4(sc, MAC_FRAME_FILTER, ffval);
653 	if (sc->mactype == DWC_GMAC_ALT_DESC) {
654 		WRITE4(sc, GMAC_MAC_HTLOW, ctx.hash[0]);
655 		WRITE4(sc, GMAC_MAC_HTHIGH, ctx.hash[1]);
656 	} else {
657 		for (i = 0; i < nhash; i++)
658 			WRITE4(sc, HASH_TABLE_REG(i), ctx.hash[i]);
659 	}
660 }
661 
662 static int
663 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
664 {
665 	struct dwc_softc *sc;
666 	struct mii_data *mii;
667 	struct ifreq *ifr;
668 	int mask, error;
669 
670 	sc = ifp->if_softc;
671 	ifr = (struct ifreq *)data;
672 
673 	error = 0;
674 	switch (cmd) {
675 	case SIOCSIFFLAGS:
676 		DWC_LOCK(sc);
677 		if (ifp->if_flags & IFF_UP) {
678 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
679 				if ((ifp->if_flags ^ sc->if_flags) &
680 				    (IFF_PROMISC | IFF_ALLMULTI))
681 					dwc_setup_rxfilter(sc);
682 			} else {
683 				if (!sc->is_detaching)
684 					dwc_init_locked(sc);
685 			}
686 		} else {
687 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
688 				dwc_stop_locked(sc);
689 		}
690 		sc->if_flags = ifp->if_flags;
691 		DWC_UNLOCK(sc);
692 		break;
693 	case SIOCADDMULTI:
694 	case SIOCDELMULTI:
695 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
696 			DWC_LOCK(sc);
697 			dwc_setup_rxfilter(sc);
698 			DWC_UNLOCK(sc);
699 		}
700 		break;
701 	case SIOCSIFMEDIA:
702 	case SIOCGIFMEDIA:
703 		mii = sc->mii_softc;
704 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
705 		break;
706 	case SIOCSIFCAP:
707 		mask = ifp->if_capenable ^ ifr->ifr_reqcap;
708 		if (mask & IFCAP_VLAN_MTU) {
709 			/* No work to do except acknowledge the change took */
710 			ifp->if_capenable ^= IFCAP_VLAN_MTU;
711 		}
712 		break;
713 
714 	default:
715 		error = ether_ioctl(ifp, cmd, data);
716 		break;
717 	}
718 
719 	return (error);
720 }
721 
722 static void
723 dwc_txfinish_locked(struct dwc_softc *sc)
724 {
725 	struct dwc_bufmap *bmap;
726 	struct dwc_hwdesc *desc;
727 	struct ifnet *ifp;
728 
729 	DWC_ASSERT_LOCKED(sc);
730 
731 	ifp = sc->ifp;
732 	while (sc->tx_idx_tail != sc->tx_idx_head) {
733 		desc = &sc->txdesc_ring[sc->tx_idx_tail];
734 		if ((desc->tdes0 & DDESC_TDES0_OWN) != 0)
735 			break;
736 		bmap = &sc->txbuf_map[sc->tx_idx_tail];
737 		bus_dmamap_sync(sc->txbuf_tag, bmap->map,
738 		    BUS_DMASYNC_POSTWRITE);
739 		bus_dmamap_unload(sc->txbuf_tag, bmap->map);
740 		m_freem(bmap->mbuf);
741 		bmap->mbuf = NULL;
742 		dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
743 		sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
744 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
745 		if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
746 	}
747 
748 	/* If there are no buffers outstanding, muzzle the watchdog. */
749 	if (sc->tx_idx_tail == sc->tx_idx_head) {
750 		sc->tx_watchdog_count = 0;
751 	}
752 }
753 
754 static void
755 dwc_rxfinish_locked(struct dwc_softc *sc)
756 {
757 	struct ifnet *ifp;
758 	struct mbuf *m0;
759 	struct mbuf *m;
760 	int error, idx, len;
761 	uint32_t rdes0;
762 
763 	ifp = sc->ifp;
764 
765 	for (;;) {
766 		idx = sc->rx_idx;
767 
768 		rdes0 = sc->rxdesc_ring[idx].tdes0;
769 		if ((rdes0 & DDESC_RDES0_OWN) != 0)
770 			break;
771 
772 		bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
773 		    BUS_DMASYNC_POSTREAD);
774 		bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map);
775 
776 		len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK;
777 		if (len != 0) {
778 			m = sc->rxbuf_map[idx].mbuf;
779 			m->m_pkthdr.rcvif = ifp;
780 			m->m_pkthdr.len = len;
781 			m->m_len = len;
782 			if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
783 
784 			/* Remove trailing FCS */
785 			m_adj(m, -ETHER_CRC_LEN);
786 
787 			DWC_UNLOCK(sc);
788 			(*ifp->if_input)(ifp, m);
789 			DWC_LOCK(sc);
790 		} else {
791 			/* XXX Zero-length packet ? */
792 		}
793 
794 		if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) {
795 			if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) {
796 				/*
797 				 * XXX Now what?
798 				 * We've got a hole in the rx ring.
799 				 */
800 			}
801 		} else
802 			if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
803 
804 		sc->rx_idx = next_rxidx(sc, sc->rx_idx);
805 	}
806 }
807 
808 static void
809 dwc_intr(void *arg)
810 {
811 	struct dwc_softc *sc;
812 	uint32_t reg;
813 
814 	sc = arg;
815 
816 	DWC_LOCK(sc);
817 
818 	reg = READ4(sc, INTERRUPT_STATUS);
819 	if (reg)
820 		READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
821 
822 	reg = READ4(sc, DMA_STATUS);
823 	if (reg & DMA_STATUS_NIS) {
824 		if (reg & DMA_STATUS_RI)
825 			dwc_rxfinish_locked(sc);
826 
827 		if (reg & DMA_STATUS_TI) {
828 			dwc_txfinish_locked(sc);
829 			dwc_txstart_locked(sc);
830 		}
831 	}
832 
833 	if (reg & DMA_STATUS_AIS) {
834 		if (reg & DMA_STATUS_FBI) {
835 			/* Fatal bus error */
836 			device_printf(sc->dev,
837 			    "Ethernet DMA error, restarting controller.\n");
838 			dwc_stop_locked(sc);
839 			dwc_init_locked(sc);
840 		}
841 	}
842 
843 	WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
844 	DWC_UNLOCK(sc);
845 }
846 
847 static int
848 setup_dma(struct dwc_softc *sc)
849 {
850 	struct mbuf *m;
851 	int error;
852 	int nidx;
853 	int idx;
854 
855 	/*
856 	 * Set up TX descriptor ring, descriptors, and dma maps.
857 	 */
858 	error = bus_dma_tag_create(
859 	    bus_get_dma_tag(sc->dev),	/* Parent tag. */
860 	    DWC_DESC_RING_ALIGN, 0,	/* alignment, boundary */
861 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
862 	    BUS_SPACE_MAXADDR,		/* highaddr */
863 	    NULL, NULL,			/* filter, filterarg */
864 	    TX_DESC_SIZE, 1, 		/* maxsize, nsegments */
865 	    TX_DESC_SIZE,		/* maxsegsize */
866 	    0,				/* flags */
867 	    NULL, NULL,			/* lockfunc, lockarg */
868 	    &sc->txdesc_tag);
869 	if (error != 0) {
870 		device_printf(sc->dev,
871 		    "could not create TX ring DMA tag.\n");
872 		goto out;
873 	}
874 
875 	error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
876 	    BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
877 	    &sc->txdesc_map);
878 	if (error != 0) {
879 		device_printf(sc->dev,
880 		    "could not allocate TX descriptor ring.\n");
881 		goto out;
882 	}
883 
884 	error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map,
885 	    sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr,
886 	    &sc->txdesc_ring_paddr, 0);
887 	if (error != 0) {
888 		device_printf(sc->dev,
889 		    "could not load TX descriptor ring map.\n");
890 		goto out;
891 	}
892 
893 	for (idx = 0; idx < TX_DESC_COUNT; idx++) {
894 		nidx = next_txidx(sc, idx);
895 		sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr +
896 		    (nidx * sizeof(struct dwc_hwdesc));
897 	}
898 
899 	error = bus_dma_tag_create(
900 	    bus_get_dma_tag(sc->dev),	/* Parent tag. */
901 	    1, 0,			/* alignment, boundary */
902 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
903 	    BUS_SPACE_MAXADDR,		/* highaddr */
904 	    NULL, NULL,			/* filter, filterarg */
905 	    MCLBYTES, 1, 		/* maxsize, nsegments */
906 	    MCLBYTES,			/* maxsegsize */
907 	    0,				/* flags */
908 	    NULL, NULL,			/* lockfunc, lockarg */
909 	    &sc->txbuf_tag);
910 	if (error != 0) {
911 		device_printf(sc->dev,
912 		    "could not create TX ring DMA tag.\n");
913 		goto out;
914 	}
915 
916 	for (idx = 0; idx < TX_DESC_COUNT; idx++) {
917 		error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT,
918 		    &sc->txbuf_map[idx].map);
919 		if (error != 0) {
920 			device_printf(sc->dev,
921 			    "could not create TX buffer DMA map.\n");
922 			goto out;
923 		}
924 		dwc_setup_txdesc(sc, idx, 0, 0);
925 	}
926 
927 	/*
928 	 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
929 	 */
930 	error = bus_dma_tag_create(
931 	    bus_get_dma_tag(sc->dev),	/* Parent tag. */
932 	    DWC_DESC_RING_ALIGN, 0,	/* alignment, boundary */
933 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
934 	    BUS_SPACE_MAXADDR,		/* highaddr */
935 	    NULL, NULL,			/* filter, filterarg */
936 	    RX_DESC_SIZE, 1, 		/* maxsize, nsegments */
937 	    RX_DESC_SIZE,		/* maxsegsize */
938 	    0,				/* flags */
939 	    NULL, NULL,			/* lockfunc, lockarg */
940 	    &sc->rxdesc_tag);
941 	if (error != 0) {
942 		device_printf(sc->dev,
943 		    "could not create RX ring DMA tag.\n");
944 		goto out;
945 	}
946 
947 	error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
948 	    BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
949 	    &sc->rxdesc_map);
950 	if (error != 0) {
951 		device_printf(sc->dev,
952 		    "could not allocate RX descriptor ring.\n");
953 		goto out;
954 	}
955 
956 	error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map,
957 	    sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr,
958 	    &sc->rxdesc_ring_paddr, 0);
959 	if (error != 0) {
960 		device_printf(sc->dev,
961 		    "could not load RX descriptor ring map.\n");
962 		goto out;
963 	}
964 
965 	error = bus_dma_tag_create(
966 	    bus_get_dma_tag(sc->dev),	/* Parent tag. */
967 	    1, 0,			/* alignment, boundary */
968 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
969 	    BUS_SPACE_MAXADDR,		/* highaddr */
970 	    NULL, NULL,			/* filter, filterarg */
971 	    MCLBYTES, 1, 		/* maxsize, nsegments */
972 	    MCLBYTES,			/* maxsegsize */
973 	    0,				/* flags */
974 	    NULL, NULL,			/* lockfunc, lockarg */
975 	    &sc->rxbuf_tag);
976 	if (error != 0) {
977 		device_printf(sc->dev,
978 		    "could not create RX buf DMA tag.\n");
979 		goto out;
980 	}
981 
982 	for (idx = 0; idx < RX_DESC_COUNT; idx++) {
983 		error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT,
984 		    &sc->rxbuf_map[idx].map);
985 		if (error != 0) {
986 			device_printf(sc->dev,
987 			    "could not create RX buffer DMA map.\n");
988 			goto out;
989 		}
990 		if ((m = dwc_alloc_mbufcl(sc)) == NULL) {
991 			device_printf(sc->dev, "Could not alloc mbuf\n");
992 			error = ENOMEM;
993 			goto out;
994 		}
995 		if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) {
996 			device_printf(sc->dev,
997 			    "could not create new RX buffer.\n");
998 			goto out;
999 		}
1000 	}
1001 
1002 out:
1003 	if (error != 0)
1004 		return (ENXIO);
1005 
1006 	return (0);
1007 }
1008 
1009 static int
1010 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr)
1011 {
1012 	uint32_t hi, lo, rnd;
1013 
1014 	/*
1015 	 * Try to recover a MAC address from the running hardware. If there's
1016 	 * something non-zero there, assume the bootloader did the right thing
1017 	 * and just use it.
1018 	 *
1019 	 * Otherwise, set the address to a convenient locally assigned address,
1020 	 * 'bsd' + random 24 low-order bits.  'b' is 0x62, which has the locally
1021 	 * assigned bit set, and the broadcast/multicast bit clear.
1022 	 */
1023 	lo = READ4(sc, MAC_ADDRESS_LOW(0));
1024 	hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff;
1025 	if ((lo != 0xffffffff) || (hi != 0xffff)) {
1026 		hwaddr[0] = (lo >>  0) & 0xff;
1027 		hwaddr[1] = (lo >>  8) & 0xff;
1028 		hwaddr[2] = (lo >> 16) & 0xff;
1029 		hwaddr[3] = (lo >> 24) & 0xff;
1030 		hwaddr[4] = (hi >>  0) & 0xff;
1031 		hwaddr[5] = (hi >>  8) & 0xff;
1032 	} else {
1033 		rnd = arc4random() & 0x00ffffff;
1034 		hwaddr[0] = 'b';
1035 		hwaddr[1] = 's';
1036 		hwaddr[2] = 'd';
1037 		hwaddr[3] = rnd >> 16;
1038 		hwaddr[4] = rnd >>  8;
1039 		hwaddr[5] = rnd >>  0;
1040 	}
1041 
1042 	return (0);
1043 }
1044 
1045 #define	GPIO_ACTIVE_LOW 1
1046 
1047 static int
1048 dwc_reset(device_t dev)
1049 {
1050 	pcell_t gpio_prop[4];
1051 	pcell_t delay_prop[3];
1052 	phandle_t node, gpio_node;
1053 	device_t gpio;
1054 	uint32_t pin, flags;
1055 	uint32_t pin_value;
1056 
1057 	node = ofw_bus_get_node(dev);
1058 	if (OF_getencprop(node, "snps,reset-gpio",
1059 	    gpio_prop, sizeof(gpio_prop)) <= 0)
1060 		return (0);
1061 
1062 	if (OF_getencprop(node, "snps,reset-delays-us",
1063 	    delay_prop, sizeof(delay_prop)) <= 0) {
1064 		device_printf(dev,
1065 		    "Wrong property for snps,reset-delays-us");
1066 		return (ENXIO);
1067 	}
1068 
1069 	gpio_node = OF_node_from_xref(gpio_prop[0]);
1070 	if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) {
1071 		device_printf(dev,
1072 		    "Can't find gpio controller for phy reset\n");
1073 		return (ENXIO);
1074 	}
1075 
1076 	if (GPIO_MAP_GPIOS(gpio, node, gpio_node,
1077 	    nitems(gpio_prop) - 1,
1078 	    gpio_prop + 1, &pin, &flags) != 0) {
1079 		device_printf(dev, "Can't map gpio for phy reset\n");
1080 		return (ENXIO);
1081 	}
1082 
1083 	pin_value = GPIO_PIN_LOW;
1084 	if (OF_hasprop(node, "snps,reset-active-low"))
1085 		pin_value = GPIO_PIN_HIGH;
1086 
1087 	GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
1088 	GPIO_PIN_SET(gpio, pin, pin_value);
1089 	DELAY(delay_prop[0] * 5);
1090 	GPIO_PIN_SET(gpio, pin, !pin_value);
1091 	DELAY(delay_prop[1] * 5);
1092 	GPIO_PIN_SET(gpio, pin, pin_value);
1093 	DELAY(delay_prop[2] * 5);
1094 
1095 	return (0);
1096 }
1097 
1098 #ifdef EXT_RESOURCES
1099 static int
1100 dwc_clock_init(device_t dev)
1101 {
1102 	hwreset_t rst;
1103 	clk_t clk;
1104 	int error;
1105 
1106 	/* Enable clock */
1107 	if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk) == 0) {
1108 		error = clk_enable(clk);
1109 		if (error != 0) {
1110 			device_printf(dev, "could not enable main clock\n");
1111 			return (error);
1112 		}
1113 	}
1114 
1115 	/* De-assert reset */
1116 	if (hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst) == 0) {
1117 		error = hwreset_deassert(rst);
1118 		if (error != 0) {
1119 			device_printf(dev, "could not de-assert reset\n");
1120 			return (error);
1121 		}
1122 	}
1123 
1124 	return (0);
1125 }
1126 #endif
1127 
1128 static int
1129 dwc_probe(device_t dev)
1130 {
1131 
1132 	if (!ofw_bus_status_okay(dev))
1133 		return (ENXIO);
1134 
1135 	if (!ofw_bus_is_compatible(dev, "snps,dwmac"))
1136 		return (ENXIO);
1137 
1138 	device_set_desc(dev, "Gigabit Ethernet Controller");
1139 	return (BUS_PROBE_DEFAULT);
1140 }
1141 
1142 static int
1143 dwc_attach(device_t dev)
1144 {
1145 	uint8_t macaddr[ETHER_ADDR_LEN];
1146 	struct dwc_softc *sc;
1147 	struct ifnet *ifp;
1148 	int error, i;
1149 	uint32_t reg;
1150 
1151 	sc = device_get_softc(dev);
1152 	sc->dev = dev;
1153 	sc->rx_idx = 0;
1154 	sc->txcount = TX_DESC_COUNT;
1155 	sc->mii_clk = IF_DWC_MII_CLK(dev);
1156 	sc->mactype = IF_DWC_MAC_TYPE(dev);
1157 
1158 	if (IF_DWC_INIT(dev) != 0)
1159 		return (ENXIO);
1160 
1161 #ifdef EXT_RESOURCES
1162 	if (dwc_clock_init(dev) != 0)
1163 		return (ENXIO);
1164 #endif
1165 
1166 	if (bus_alloc_resources(dev, dwc_spec, sc->res)) {
1167 		device_printf(dev, "could not allocate resources\n");
1168 		return (ENXIO);
1169 	}
1170 
1171 	/* Memory interface */
1172 	sc->bst = rman_get_bustag(sc->res[0]);
1173 	sc->bsh = rman_get_bushandle(sc->res[0]);
1174 
1175 	/* Read MAC before reset */
1176 	if (dwc_get_hwaddr(sc, macaddr)) {
1177 		device_printf(sc->dev, "can't get mac\n");
1178 		return (ENXIO);
1179 	}
1180 
1181 	/* Reset the PHY if needed */
1182 	if (dwc_reset(dev) != 0) {
1183 		device_printf(dev, "Can't reset the PHY\n");
1184 		return (ENXIO);
1185 	}
1186 
1187 	/* Reset */
1188 	reg = READ4(sc, BUS_MODE);
1189 	reg |= (BUS_MODE_SWR);
1190 	WRITE4(sc, BUS_MODE, reg);
1191 
1192 	for (i = 0; i < MAC_RESET_TIMEOUT; i++) {
1193 		if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)
1194 			break;
1195 		DELAY(10);
1196 	}
1197 	if (i >= MAC_RESET_TIMEOUT) {
1198 		device_printf(sc->dev, "Can't reset DWC.\n");
1199 		return (ENXIO);
1200 	}
1201 
1202 	if (sc->mactype == DWC_GMAC_ALT_DESC) {
1203 		reg = BUS_MODE_FIXEDBURST;
1204 		reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT);
1205 	} else
1206 		reg = (BUS_MODE_EIGHTXPBL);
1207 	reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT);
1208 	WRITE4(sc, BUS_MODE, reg);
1209 
1210 	/*
1211 	 * DMA must be stop while changing descriptor list addresses.
1212 	 */
1213 	reg = READ4(sc, OPERATION_MODE);
1214 	reg &= ~(MODE_ST | MODE_SR);
1215 	WRITE4(sc, OPERATION_MODE, reg);
1216 
1217 	if (setup_dma(sc))
1218 	        return (ENXIO);
1219 
1220 	/* Setup addresses */
1221 	WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);
1222 	WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);
1223 
1224 	mtx_init(&sc->mtx, device_get_nameunit(sc->dev),
1225 	    MTX_NETWORK_LOCK, MTX_DEF);
1226 
1227 	callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0);
1228 
1229 	/* Setup interrupt handler. */
1230 	error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
1231 	    NULL, dwc_intr, sc, &sc->intr_cookie);
1232 	if (error != 0) {
1233 		device_printf(dev, "could not setup interrupt handler.\n");
1234 		return (ENXIO);
1235 	}
1236 
1237 	/* Set up the ethernet interface. */
1238 	sc->ifp = ifp = if_alloc(IFT_ETHER);
1239 
1240 	ifp->if_softc = sc;
1241 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1242 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1243 	ifp->if_capabilities = IFCAP_VLAN_MTU;
1244 	ifp->if_capenable = ifp->if_capabilities;
1245 	ifp->if_start = dwc_txstart;
1246 	ifp->if_ioctl = dwc_ioctl;
1247 	ifp->if_init = dwc_init;
1248 	IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1249 	ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1250 	IFQ_SET_READY(&ifp->if_snd);
1251 
1252 	/* Attach the mii driver. */
1253 	error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change,
1254 	    dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY,
1255 	    MII_OFFSET_ANY, 0);
1256 
1257 	if (error != 0) {
1258 		device_printf(dev, "PHY attach failed\n");
1259 		return (ENXIO);
1260 	}
1261 	sc->mii_softc = device_get_softc(sc->miibus);
1262 
1263 	/* All ready to run, attach the ethernet interface. */
1264 	ether_ifattach(ifp, macaddr);
1265 	sc->is_attached = true;
1266 
1267 	return (0);
1268 }
1269 
1270 static int
1271 dwc_miibus_read_reg(device_t dev, int phy, int reg)
1272 {
1273 	struct dwc_softc *sc;
1274 	uint16_t mii;
1275 	size_t cnt;
1276 	int rv = 0;
1277 
1278 	sc = device_get_softc(dev);
1279 
1280 	mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1281 	    | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1282 	    | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1283 	    | GMII_ADDRESS_GB; /* Busy flag */
1284 
1285 	WRITE4(sc, GMII_ADDRESS, mii);
1286 
1287 	for (cnt = 0; cnt < 1000; cnt++) {
1288 		if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1289 			rv = READ4(sc, GMII_DATA);
1290 			break;
1291 		}
1292 		DELAY(10);
1293 	}
1294 
1295 	return rv;
1296 }
1297 
1298 static int
1299 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val)
1300 {
1301 	struct dwc_softc *sc;
1302 	uint16_t mii;
1303 	size_t cnt;
1304 
1305 	sc = device_get_softc(dev);
1306 
1307 	mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1308 	    | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1309 	    | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1310 	    | GMII_ADDRESS_GB | GMII_ADDRESS_GW;
1311 
1312 	WRITE4(sc, GMII_DATA, val);
1313 	WRITE4(sc, GMII_ADDRESS, mii);
1314 
1315 	for (cnt = 0; cnt < 1000; cnt++) {
1316 		if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1317 			break;
1318                 }
1319 		DELAY(10);
1320 	}
1321 
1322 	return (0);
1323 }
1324 
1325 static void
1326 dwc_miibus_statchg(device_t dev)
1327 {
1328 	struct dwc_softc *sc;
1329 	struct mii_data *mii;
1330 	uint32_t reg;
1331 
1332 	/*
1333 	 * Called by the MII bus driver when the PHY establishes
1334 	 * link to set the MAC interface registers.
1335 	 */
1336 
1337 	sc = device_get_softc(dev);
1338 
1339 	DWC_ASSERT_LOCKED(sc);
1340 
1341 	mii = sc->mii_softc;
1342 
1343 	if (mii->mii_media_status & IFM_ACTIVE)
1344 		sc->link_is_up = true;
1345 	else
1346 		sc->link_is_up = false;
1347 
1348 	reg = READ4(sc, MAC_CONFIGURATION);
1349 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
1350 	case IFM_1000_T:
1351 	case IFM_1000_SX:
1352 		reg &= ~(CONF_FES | CONF_PS);
1353 		break;
1354 	case IFM_100_TX:
1355 		reg |= (CONF_FES | CONF_PS);
1356 		break;
1357 	case IFM_10_T:
1358 		reg &= ~(CONF_FES);
1359 		reg |= (CONF_PS);
1360 		break;
1361 	case IFM_NONE:
1362 		sc->link_is_up = false;
1363 		return;
1364 	default:
1365 		sc->link_is_up = false;
1366 		device_printf(dev, "Unsupported media %u\n",
1367 		    IFM_SUBTYPE(mii->mii_media_active));
1368 		return;
1369 	}
1370 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1371 		reg |= (CONF_DM);
1372 	else
1373 		reg &= ~(CONF_DM);
1374 	WRITE4(sc, MAC_CONFIGURATION, reg);
1375 }
1376 
1377 static device_method_t dwc_methods[] = {
1378 	DEVMETHOD(device_probe,		dwc_probe),
1379 	DEVMETHOD(device_attach,	dwc_attach),
1380 
1381 	/* MII Interface */
1382 	DEVMETHOD(miibus_readreg,	dwc_miibus_read_reg),
1383 	DEVMETHOD(miibus_writereg,	dwc_miibus_write_reg),
1384 	DEVMETHOD(miibus_statchg,	dwc_miibus_statchg),
1385 
1386 	{ 0, 0 }
1387 };
1388 
1389 driver_t dwc_driver = {
1390 	"dwc",
1391 	dwc_methods,
1392 	sizeof(struct dwc_softc),
1393 };
1394 
1395 static devclass_t dwc_devclass;
1396 
1397 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0);
1398 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0);
1399 
1400 MODULE_DEPEND(dwc, ether, 1, 1, 1);
1401 MODULE_DEPEND(dwc, miibus, 1, 1, 1);
1402