1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Ethernet media access controller (EMAC) 33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 * 35 * EMAC is an instance of the Synopsys DesignWare 3504-0 36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/malloc.h> 48 #include <sys/rman.h> 49 #include <sys/endian.h> 50 #include <sys/lock.h> 51 #include <sys/mbuf.h> 52 #include <sys/mutex.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 #include <sys/sysctl.h> 56 57 #include <dev/fdt/fdt_common.h> 58 #include <dev/ofw/openfirm.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 62 #include <net/bpf.h> 63 #include <net/if.h> 64 #include <net/ethernet.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 #include <net/if_var.h> 69 #include <net/if_vlan_var.h> 70 71 #include <machine/bus.h> 72 #include <machine/fdt.h> 73 74 #include <dev/mii/mii.h> 75 #include <dev/mii/miivar.h> 76 #include "miibus_if.h" 77 78 #define READ4(_sc, _reg) \ 79 bus_read_4((_sc)->res[0], _reg) 80 #define WRITE4(_sc, _reg, _val) \ 81 bus_write_4((_sc)->res[0], _reg, _val) 82 83 #define MAC_RESET_TIMEOUT 100 84 #define WATCHDOG_TIMEOUT_SECS 5 85 #define STATS_HARVEST_INTERVAL 2 86 #define MII_CLK_VAL 2 87 88 #include <dev/dwc/if_dwc.h> 89 90 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) 91 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 92 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 93 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 94 95 #define DDESC_TDES0_OWN (1 << 31) 96 #define DDESC_TDES0_TXINT (1 << 30) 97 #define DDESC_TDES0_TXLAST (1 << 29) 98 #define DDESC_TDES0_TXFIRST (1 << 28) 99 #define DDESC_TDES0_TXCRCDIS (1 << 27) 100 #define DDESC_TDES0_TXRINGEND (1 << 21) 101 #define DDESC_TDES0_TXCHAIN (1 << 20) 102 103 #define DDESC_RDES0_OWN (1 << 31) 104 #define DDESC_RDES0_FL_MASK 0x3fff 105 #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ 106 #define DDESC_RDES1_CHAINED (1 << 14) 107 108 struct dwc_bufmap { 109 bus_dmamap_t map; 110 struct mbuf *mbuf; 111 }; 112 113 /* 114 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 115 * layout, but the bits in the flags field have different meanings. 116 */ 117 struct dwc_hwdesc 118 { 119 uint32_t tdes0; 120 uint32_t tdes1; 121 uint32_t addr; /* pointer to buffer data */ 122 uint32_t addr_next; /* link to next descriptor */ 123 }; 124 125 /* 126 * Driver data and defines. 127 */ 128 #define RX_DESC_COUNT 1024 129 #define RX_DESC_SIZE (sizeof(struct dwc_hwdesc) * RX_DESC_COUNT) 130 #define TX_DESC_COUNT 1024 131 #define TX_DESC_SIZE (sizeof(struct dwc_hwdesc) * TX_DESC_COUNT) 132 133 /* 134 * The hardware imposes alignment restrictions on various objects involved in 135 * DMA transfers. These values are expressed in bytes (not bits). 136 */ 137 #define DWC_DESC_RING_ALIGN 2048 138 139 struct dwc_softc { 140 struct resource *res[2]; 141 bus_space_tag_t bst; 142 bus_space_handle_t bsh; 143 device_t dev; 144 int mii_clk; 145 device_t miibus; 146 struct mii_data * mii_softc; 147 struct ifnet *ifp; 148 int if_flags; 149 struct mtx mtx; 150 void * intr_cookie; 151 struct callout dwc_callout; 152 uint8_t phy_conn_type; 153 uint8_t mactype; 154 boolean_t link_is_up; 155 boolean_t is_attached; 156 boolean_t is_detaching; 157 int tx_watchdog_count; 158 int stats_harvest_count; 159 160 /* RX */ 161 bus_dma_tag_t rxdesc_tag; 162 bus_dmamap_t rxdesc_map; 163 struct dwc_hwdesc *rxdesc_ring; 164 bus_addr_t rxdesc_ring_paddr; 165 bus_dma_tag_t rxbuf_tag; 166 struct dwc_bufmap rxbuf_map[RX_DESC_COUNT]; 167 uint32_t rx_idx; 168 169 /* TX */ 170 bus_dma_tag_t txdesc_tag; 171 bus_dmamap_t txdesc_map; 172 struct dwc_hwdesc *txdesc_ring; 173 bus_addr_t txdesc_ring_paddr; 174 bus_dma_tag_t txbuf_tag; 175 struct dwc_bufmap txbuf_map[RX_DESC_COUNT]; 176 uint32_t tx_idx_head; 177 uint32_t tx_idx_tail; 178 int txcount; 179 }; 180 181 static struct resource_spec dwc_spec[] = { 182 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 183 { SYS_RES_IRQ, 0, RF_ACTIVE }, 184 { -1, 0 } 185 }; 186 187 static void dwc_txfinish_locked(struct dwc_softc *sc); 188 static void dwc_rxfinish_locked(struct dwc_softc *sc); 189 static void dwc_stop_locked(struct dwc_softc *sc); 190 static void dwc_setup_rxfilter(struct dwc_softc *sc); 191 192 static inline uint32_t 193 next_rxidx(struct dwc_softc *sc, uint32_t curidx) 194 { 195 196 return ((curidx + 1) % RX_DESC_COUNT); 197 } 198 199 static inline uint32_t 200 next_txidx(struct dwc_softc *sc, uint32_t curidx) 201 { 202 203 return ((curidx + 1) % TX_DESC_COUNT); 204 } 205 206 static void 207 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 208 { 209 210 if (error != 0) 211 return; 212 *(bus_addr_t *)arg = segs[0].ds_addr; 213 } 214 215 inline static uint32_t 216 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, 217 uint32_t len) 218 { 219 uint32_t flags; 220 uint32_t nidx; 221 222 nidx = next_txidx(sc, idx); 223 224 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 225 if (paddr == 0 || len == 0) { 226 flags = 0; 227 --sc->txcount; 228 } else { 229 flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST 230 | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT; 231 ++sc->txcount; 232 } 233 234 sc->txdesc_ring[idx].addr = (uint32_t)(paddr); 235 sc->txdesc_ring[idx].tdes0 = flags; 236 sc->txdesc_ring[idx].tdes1 = len; 237 238 if (paddr && len) { 239 wmb(); 240 sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN; 241 wmb(); 242 } 243 244 return (nidx); 245 } 246 247 static int 248 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) 249 { 250 struct bus_dma_segment seg; 251 int error, nsegs; 252 struct mbuf * m; 253 254 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 255 return (ENOMEM); 256 *mp = m; 257 258 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 259 m, &seg, &nsegs, 0); 260 if (error != 0) { 261 return (ENOMEM); 262 } 263 264 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 265 266 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 267 BUS_DMASYNC_PREWRITE); 268 269 sc->txbuf_map[idx].mbuf = m; 270 271 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 272 273 return (0); 274 } 275 276 static void 277 dwc_txstart_locked(struct dwc_softc *sc) 278 { 279 struct ifnet *ifp; 280 struct mbuf *m; 281 int enqueued; 282 283 DWC_ASSERT_LOCKED(sc); 284 285 if (!sc->link_is_up) 286 return; 287 288 ifp = sc->ifp; 289 290 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 291 return; 292 } 293 294 enqueued = 0; 295 296 for (;;) { 297 if (sc->txcount == (TX_DESC_COUNT-1)) { 298 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 299 break; 300 } 301 302 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 303 if (m == NULL) 304 break; 305 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 306 IFQ_DRV_PREPEND(&ifp->if_snd, m); 307 break; 308 } 309 BPF_MTAP(ifp, m); 310 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 311 ++enqueued; 312 } 313 314 if (enqueued != 0) { 315 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 316 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 317 } 318 } 319 320 static void 321 dwc_txstart(struct ifnet *ifp) 322 { 323 struct dwc_softc *sc = ifp->if_softc; 324 325 DWC_LOCK(sc); 326 dwc_txstart_locked(sc); 327 DWC_UNLOCK(sc); 328 } 329 330 static void 331 dwc_stop_locked(struct dwc_softc *sc) 332 { 333 struct ifnet *ifp; 334 int reg; 335 336 DWC_ASSERT_LOCKED(sc); 337 338 ifp = sc->ifp; 339 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 340 sc->tx_watchdog_count = 0; 341 sc->stats_harvest_count = 0; 342 343 callout_stop(&sc->dwc_callout); 344 345 /* Stop DMA TX */ 346 reg = READ4(sc, OPERATION_MODE); 347 reg &= ~(MODE_ST); 348 WRITE4(sc, OPERATION_MODE, reg); 349 350 /* Flush TX */ 351 reg = READ4(sc, OPERATION_MODE); 352 reg |= (MODE_FTF); 353 WRITE4(sc, OPERATION_MODE, reg); 354 355 /* Stop transmitters */ 356 reg = READ4(sc, MAC_CONFIGURATION); 357 reg &= ~(CONF_TE | CONF_RE); 358 WRITE4(sc, MAC_CONFIGURATION, reg); 359 360 /* Stop DMA RX */ 361 reg = READ4(sc, OPERATION_MODE); 362 reg &= ~(MODE_SR); 363 WRITE4(sc, OPERATION_MODE, reg); 364 } 365 366 static void dwc_clear_stats(struct dwc_softc *sc) 367 { 368 int reg; 369 370 reg = READ4(sc, MMC_CONTROL); 371 reg |= (MMC_CONTROL_CNTRST); 372 WRITE4(sc, MMC_CONTROL, reg); 373 } 374 375 static void 376 dwc_harvest_stats(struct dwc_softc *sc) 377 { 378 struct ifnet *ifp; 379 380 /* We don't need to harvest too often. */ 381 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 382 return; 383 384 sc->stats_harvest_count = 0; 385 ifp = sc->ifp; 386 387 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); 388 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); 389 if_inc_counter(ifp, IFCOUNTER_IERRORS, 390 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + 391 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + 392 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + 393 READ4(sc, RXLENGTHERROR)); 394 395 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); 396 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); 397 if_inc_counter(ifp, IFCOUNTER_OERRORS, 398 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + 399 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); 400 401 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 402 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); 403 404 dwc_clear_stats(sc); 405 } 406 407 static void 408 dwc_tick(void *arg) 409 { 410 struct dwc_softc *sc; 411 struct ifnet *ifp; 412 int link_was_up; 413 414 sc = arg; 415 416 DWC_ASSERT_LOCKED(sc); 417 418 ifp = sc->ifp; 419 420 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 421 return; 422 423 /* 424 * Typical tx watchdog. If this fires it indicates that we enqueued 425 * packets for output and never got a txdone interrupt for them. Maybe 426 * it's a missed interrupt somehow, just pretend we got one. 427 */ 428 if (sc->tx_watchdog_count > 0) { 429 if (--sc->tx_watchdog_count == 0) { 430 dwc_txfinish_locked(sc); 431 } 432 } 433 434 /* Gather stats from hardware counters. */ 435 dwc_harvest_stats(sc); 436 437 /* Check the media status. */ 438 link_was_up = sc->link_is_up; 439 mii_tick(sc->mii_softc); 440 if (sc->link_is_up && !link_was_up) 441 dwc_txstart_locked(sc); 442 443 /* Schedule another check one second from now. */ 444 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 445 } 446 447 static void 448 dwc_init_locked(struct dwc_softc *sc) 449 { 450 struct ifnet *ifp = sc->ifp; 451 int reg; 452 453 DWC_ASSERT_LOCKED(sc); 454 455 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 456 return; 457 458 ifp->if_drv_flags |= IFF_DRV_RUNNING; 459 460 dwc_setup_rxfilter(sc); 461 462 /* Initializa DMA and enable transmitters */ 463 reg = READ4(sc, OPERATION_MODE); 464 reg |= (MODE_TSF | MODE_OSF | MODE_FUF); 465 reg &= ~(MODE_RSF); 466 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); 467 WRITE4(sc, OPERATION_MODE, reg); 468 469 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 470 471 /* Start DMA */ 472 reg = READ4(sc, OPERATION_MODE); 473 reg |= (MODE_ST | MODE_SR); 474 WRITE4(sc, OPERATION_MODE, reg); 475 476 /* Enable transmitters */ 477 reg = READ4(sc, MAC_CONFIGURATION); 478 reg |= (CONF_JD | CONF_ACS | CONF_BE); 479 reg |= (CONF_TE | CONF_RE); 480 WRITE4(sc, MAC_CONFIGURATION, reg); 481 482 /* 483 * Call mii_mediachg() which will call back into dwc_miibus_statchg() 484 * to set up the remaining config registers based on current media. 485 */ 486 mii_mediachg(sc->mii_softc); 487 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); 488 } 489 490 static void 491 dwc_init(void *if_softc) 492 { 493 struct dwc_softc *sc = if_softc; 494 495 DWC_LOCK(sc); 496 dwc_init_locked(sc); 497 DWC_UNLOCK(sc); 498 } 499 500 inline static uint32_t 501 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) 502 { 503 uint32_t nidx; 504 505 sc->rxdesc_ring[idx].addr = (uint32_t)paddr; 506 nidx = next_rxidx(sc, idx); 507 sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \ 508 (nidx * sizeof(struct dwc_hwdesc)); 509 sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; 510 511 wmb(); 512 sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; 513 wmb(); 514 515 return (nidx); 516 } 517 518 static int 519 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) 520 { 521 struct bus_dma_segment seg; 522 int error, nsegs; 523 524 m_adj(m, ETHER_ALIGN); 525 526 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 527 m, &seg, &nsegs, 0); 528 if (error != 0) { 529 return (error); 530 } 531 532 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 533 534 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 535 BUS_DMASYNC_PREREAD); 536 537 sc->rxbuf_map[idx].mbuf = m; 538 dwc_setup_rxdesc(sc, idx, seg.ds_addr); 539 540 return (0); 541 } 542 543 static struct mbuf * 544 dwc_alloc_mbufcl(struct dwc_softc *sc) 545 { 546 struct mbuf *m; 547 548 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 549 if (m != NULL) 550 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 551 552 return (m); 553 } 554 555 static void 556 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 557 { 558 struct dwc_softc *sc; 559 struct mii_data *mii; 560 561 sc = ifp->if_softc; 562 mii = sc->mii_softc; 563 DWC_LOCK(sc); 564 mii_pollstat(mii); 565 ifmr->ifm_active = mii->mii_media_active; 566 ifmr->ifm_status = mii->mii_media_status; 567 DWC_UNLOCK(sc); 568 } 569 570 static int 571 dwc_media_change_locked(struct dwc_softc *sc) 572 { 573 574 return (mii_mediachg(sc->mii_softc)); 575 } 576 577 static int 578 dwc_media_change(struct ifnet * ifp) 579 { 580 struct dwc_softc *sc; 581 int error; 582 583 sc = ifp->if_softc; 584 585 DWC_LOCK(sc); 586 error = dwc_media_change_locked(sc); 587 DWC_UNLOCK(sc); 588 return (error); 589 } 590 591 static const uint8_t nibbletab[] = { 592 /* 0x0 0000 -> 0000 */ 0x0, 593 /* 0x1 0001 -> 1000 */ 0x8, 594 /* 0x2 0010 -> 0100 */ 0x4, 595 /* 0x3 0011 -> 1100 */ 0xc, 596 /* 0x4 0100 -> 0010 */ 0x2, 597 /* 0x5 0101 -> 1010 */ 0xa, 598 /* 0x6 0110 -> 0110 */ 0x6, 599 /* 0x7 0111 -> 1110 */ 0xe, 600 /* 0x8 1000 -> 0001 */ 0x1, 601 /* 0x9 1001 -> 1001 */ 0x9, 602 /* 0xa 1010 -> 0101 */ 0x5, 603 /* 0xb 1011 -> 1101 */ 0xd, 604 /* 0xc 1100 -> 0011 */ 0x3, 605 /* 0xd 1101 -> 1011 */ 0xb, 606 /* 0xe 1110 -> 0111 */ 0x7, 607 /* 0xf 1111 -> 1111 */ 0xf, }; 608 609 static uint8_t 610 bitreverse(uint8_t x) 611 { 612 613 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; 614 } 615 616 static void 617 dwc_setup_rxfilter(struct dwc_softc *sc) 618 { 619 struct ifmultiaddr *ifma; 620 struct ifnet *ifp; 621 uint8_t *eaddr; 622 uint32_t crc; 623 uint8_t val; 624 int hashbit; 625 int hashreg; 626 int ffval; 627 int reg; 628 int lo; 629 int hi; 630 631 DWC_ASSERT_LOCKED(sc); 632 633 ifp = sc->ifp; 634 635 /* 636 * Set the multicast (group) filter hash. 637 */ 638 if ((ifp->if_flags & IFF_ALLMULTI)) 639 ffval = (FRAME_FILTER_PM); 640 else { 641 ffval = (FRAME_FILTER_HMC); 642 if_maddr_rlock(ifp); 643 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 644 if (ifma->ifma_addr->sa_family != AF_LINK) 645 continue; 646 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 647 ifma->ifma_addr), ETHER_ADDR_LEN); 648 649 /* Take lower 8 bits and reverse it */ 650 val = bitreverse(~crc & 0xff); 651 hashreg = (val >> 5); 652 hashbit = (val & 31); 653 654 reg = READ4(sc, HASH_TABLE_REG(hashreg)); 655 reg |= (1 << hashbit); 656 WRITE4(sc, HASH_TABLE_REG(hashreg), reg); 657 } 658 if_maddr_runlock(ifp); 659 } 660 661 /* 662 * Set the individual address filter hash. 663 */ 664 if (ifp->if_flags & IFF_PROMISC) 665 ffval |= (FRAME_FILTER_PR); 666 667 /* 668 * Set the primary address. 669 */ 670 eaddr = IF_LLADDR(ifp); 671 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 672 (eaddr[3] << 24); 673 hi = eaddr[4] | (eaddr[5] << 8); 674 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); 675 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); 676 WRITE4(sc, MAC_FRAME_FILTER, ffval); 677 } 678 679 static int 680 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 681 { 682 struct dwc_softc *sc; 683 struct mii_data *mii; 684 struct ifreq *ifr; 685 int mask, error; 686 687 sc = ifp->if_softc; 688 ifr = (struct ifreq *)data; 689 690 error = 0; 691 switch (cmd) { 692 case SIOCSIFFLAGS: 693 DWC_LOCK(sc); 694 if (ifp->if_flags & IFF_UP) { 695 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 696 if ((ifp->if_flags ^ sc->if_flags) & 697 (IFF_PROMISC | IFF_ALLMULTI)) 698 dwc_setup_rxfilter(sc); 699 } else { 700 if (!sc->is_detaching) 701 dwc_init_locked(sc); 702 } 703 } else { 704 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 705 dwc_stop_locked(sc); 706 } 707 sc->if_flags = ifp->if_flags; 708 DWC_UNLOCK(sc); 709 break; 710 case SIOCADDMULTI: 711 case SIOCDELMULTI: 712 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 713 DWC_LOCK(sc); 714 dwc_setup_rxfilter(sc); 715 DWC_UNLOCK(sc); 716 } 717 break; 718 case SIOCSIFMEDIA: 719 case SIOCGIFMEDIA: 720 mii = sc->mii_softc; 721 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 722 break; 723 case SIOCSIFCAP: 724 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 725 if (mask & IFCAP_VLAN_MTU) { 726 /* No work to do except acknowledge the change took */ 727 ifp->if_capenable ^= IFCAP_VLAN_MTU; 728 } 729 break; 730 731 default: 732 error = ether_ioctl(ifp, cmd, data); 733 break; 734 } 735 736 return (error); 737 } 738 739 static void 740 dwc_txfinish_locked(struct dwc_softc *sc) 741 { 742 struct dwc_bufmap *bmap; 743 struct dwc_hwdesc *desc; 744 struct ifnet *ifp; 745 746 DWC_ASSERT_LOCKED(sc); 747 748 ifp = sc->ifp; 749 while (sc->tx_idx_tail != sc->tx_idx_head) { 750 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 751 if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) 752 break; 753 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 754 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 755 BUS_DMASYNC_POSTWRITE); 756 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 757 m_freem(bmap->mbuf); 758 bmap->mbuf = NULL; 759 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 760 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 761 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 762 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 763 } 764 765 /* If there are no buffers outstanding, muzzle the watchdog. */ 766 if (sc->tx_idx_tail == sc->tx_idx_head) { 767 sc->tx_watchdog_count = 0; 768 } 769 } 770 771 static void 772 dwc_rxfinish_locked(struct dwc_softc *sc) 773 { 774 struct ifnet *ifp; 775 struct mbuf *m0; 776 struct mbuf *m; 777 int error; 778 int rdes0; 779 int idx; 780 int len; 781 782 ifp = sc->ifp; 783 784 for (;;) { 785 idx = sc->rx_idx; 786 787 rdes0 = sc->rxdesc_ring[idx].tdes0; 788 if ((rdes0 & DDESC_RDES0_OWN) != 0) 789 break; 790 791 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 792 BUS_DMASYNC_POSTREAD); 793 bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); 794 795 len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; 796 if (len != 0) { 797 m = sc->rxbuf_map[idx].mbuf; 798 m->m_pkthdr.rcvif = ifp; 799 m->m_pkthdr.len = len; 800 m->m_len = len; 801 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 802 803 DWC_UNLOCK(sc); 804 (*ifp->if_input)(ifp, m); 805 DWC_LOCK(sc); 806 } else { 807 /* XXX Zero-length packet ? */ 808 } 809 810 if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) { 811 if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { 812 /* 813 * XXX Now what? 814 * We've got a hole in the rx ring. 815 */ 816 } 817 } else 818 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 819 820 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 821 } 822 } 823 824 static void 825 dwc_intr(void *arg) 826 { 827 struct dwc_softc *sc; 828 uint32_t reg; 829 830 sc = arg; 831 832 DWC_LOCK(sc); 833 834 reg = READ4(sc, INTERRUPT_STATUS); 835 if (reg) { 836 mii_mediachg(sc->mii_softc); 837 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); 838 } 839 840 reg = READ4(sc, DMA_STATUS); 841 if (reg & DMA_STATUS_NIS) { 842 if (reg & DMA_STATUS_RI) 843 dwc_rxfinish_locked(sc); 844 845 if (reg & DMA_STATUS_TI) { 846 dwc_txfinish_locked(sc); 847 dwc_txstart_locked(sc); 848 } 849 } 850 851 if (reg & DMA_STATUS_AIS) { 852 if (reg & DMA_STATUS_FBI) { 853 /* Fatal bus error */ 854 device_printf(sc->dev, 855 "Ethernet DMA error, restarting controller.\n"); 856 dwc_stop_locked(sc); 857 dwc_init_locked(sc); 858 } 859 } 860 861 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 862 DWC_UNLOCK(sc); 863 } 864 865 static int 866 setup_dma(struct dwc_softc *sc) 867 { 868 struct mbuf *m; 869 int error; 870 int nidx; 871 int idx; 872 873 /* 874 * Set up TX descriptor ring, descriptors, and dma maps. 875 */ 876 error = bus_dma_tag_create( 877 bus_get_dma_tag(sc->dev), /* Parent tag. */ 878 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 879 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 880 BUS_SPACE_MAXADDR, /* highaddr */ 881 NULL, NULL, /* filter, filterarg */ 882 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 883 TX_DESC_SIZE, /* maxsegsize */ 884 0, /* flags */ 885 NULL, NULL, /* lockfunc, lockarg */ 886 &sc->txdesc_tag); 887 if (error != 0) { 888 device_printf(sc->dev, 889 "could not create TX ring DMA tag.\n"); 890 goto out; 891 } 892 893 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 894 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 895 &sc->txdesc_map); 896 if (error != 0) { 897 device_printf(sc->dev, 898 "could not allocate TX descriptor ring.\n"); 899 goto out; 900 } 901 902 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, 903 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, 904 &sc->txdesc_ring_paddr, 0); 905 if (error != 0) { 906 device_printf(sc->dev, 907 "could not load TX descriptor ring map.\n"); 908 goto out; 909 } 910 911 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 912 sc->txdesc_ring[idx].tdes0 = DDESC_TDES0_TXCHAIN; 913 sc->txdesc_ring[idx].tdes1 = 0; 914 nidx = next_txidx(sc, idx); 915 sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + \ 916 (nidx * sizeof(struct dwc_hwdesc)); 917 } 918 919 error = bus_dma_tag_create( 920 bus_get_dma_tag(sc->dev), /* Parent tag. */ 921 1, 0, /* alignment, boundary */ 922 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 923 BUS_SPACE_MAXADDR, /* highaddr */ 924 NULL, NULL, /* filter, filterarg */ 925 MCLBYTES, 1, /* maxsize, nsegments */ 926 MCLBYTES, /* maxsegsize */ 927 0, /* flags */ 928 NULL, NULL, /* lockfunc, lockarg */ 929 &sc->txbuf_tag); 930 if (error != 0) { 931 device_printf(sc->dev, 932 "could not create TX ring DMA tag.\n"); 933 goto out; 934 } 935 936 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 937 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, 938 &sc->txbuf_map[idx].map); 939 if (error != 0) { 940 device_printf(sc->dev, 941 "could not create TX buffer DMA map.\n"); 942 goto out; 943 } 944 dwc_setup_txdesc(sc, idx, 0, 0); 945 } 946 947 /* 948 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 949 */ 950 error = bus_dma_tag_create( 951 bus_get_dma_tag(sc->dev), /* Parent tag. */ 952 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 953 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 954 BUS_SPACE_MAXADDR, /* highaddr */ 955 NULL, NULL, /* filter, filterarg */ 956 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 957 RX_DESC_SIZE, /* maxsegsize */ 958 0, /* flags */ 959 NULL, NULL, /* lockfunc, lockarg */ 960 &sc->rxdesc_tag); 961 if (error != 0) { 962 device_printf(sc->dev, 963 "could not create RX ring DMA tag.\n"); 964 goto out; 965 } 966 967 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 968 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 969 &sc->rxdesc_map); 970 if (error != 0) { 971 device_printf(sc->dev, 972 "could not allocate RX descriptor ring.\n"); 973 goto out; 974 } 975 976 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, 977 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, 978 &sc->rxdesc_ring_paddr, 0); 979 if (error != 0) { 980 device_printf(sc->dev, 981 "could not load RX descriptor ring map.\n"); 982 goto out; 983 } 984 985 error = bus_dma_tag_create( 986 bus_get_dma_tag(sc->dev), /* Parent tag. */ 987 1, 0, /* alignment, boundary */ 988 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 989 BUS_SPACE_MAXADDR, /* highaddr */ 990 NULL, NULL, /* filter, filterarg */ 991 MCLBYTES, 1, /* maxsize, nsegments */ 992 MCLBYTES, /* maxsegsize */ 993 0, /* flags */ 994 NULL, NULL, /* lockfunc, lockarg */ 995 &sc->rxbuf_tag); 996 if (error != 0) { 997 device_printf(sc->dev, 998 "could not create RX buf DMA tag.\n"); 999 goto out; 1000 } 1001 1002 for (idx = 0; idx < RX_DESC_COUNT; idx++) { 1003 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, 1004 &sc->rxbuf_map[idx].map); 1005 if (error != 0) { 1006 device_printf(sc->dev, 1007 "could not create RX buffer DMA map.\n"); 1008 goto out; 1009 } 1010 if ((m = dwc_alloc_mbufcl(sc)) == NULL) { 1011 device_printf(sc->dev, "Could not alloc mbuf\n"); 1012 error = ENOMEM; 1013 goto out; 1014 } 1015 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { 1016 device_printf(sc->dev, 1017 "could not create new RX buffer.\n"); 1018 goto out; 1019 } 1020 } 1021 1022 out: 1023 if (error != 0) 1024 return (ENXIO); 1025 1026 return (0); 1027 } 1028 1029 static int 1030 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) 1031 { 1032 int rnd; 1033 int lo; 1034 int hi; 1035 1036 /* 1037 * Try to recover a MAC address from the running hardware. If there's 1038 * something non-zero there, assume the bootloader did the right thing 1039 * and just use it. 1040 * 1041 * Otherwise, set the address to a convenient locally assigned address, 1042 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 1043 * assigned bit set, and the broadcast/multicast bit clear. 1044 */ 1045 lo = READ4(sc, MAC_ADDRESS_LOW(0)); 1046 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; 1047 if ((lo != 0xffffffff) || (hi != 0xffff)) { 1048 hwaddr[0] = (lo >> 0) & 0xff; 1049 hwaddr[1] = (lo >> 8) & 0xff; 1050 hwaddr[2] = (lo >> 16) & 0xff; 1051 hwaddr[3] = (lo >> 24) & 0xff; 1052 hwaddr[4] = (hi >> 0) & 0xff; 1053 hwaddr[5] = (hi >> 8) & 0xff; 1054 } else { 1055 rnd = arc4random() & 0x00ffffff; 1056 hwaddr[0] = 'b'; 1057 hwaddr[1] = 's'; 1058 hwaddr[2] = 'd'; 1059 hwaddr[3] = rnd >> 16; 1060 hwaddr[4] = rnd >> 8; 1061 hwaddr[5] = rnd >> 0; 1062 } 1063 1064 return (0); 1065 } 1066 1067 static int 1068 dwc_probe(device_t dev) 1069 { 1070 1071 if (!ofw_bus_status_okay(dev)) 1072 return (ENXIO); 1073 1074 if (!ofw_bus_is_compatible(dev, "snps,dwmac")) 1075 return (ENXIO); 1076 1077 device_set_desc(dev, "Gigabit Ethernet Controller"); 1078 return (BUS_PROBE_DEFAULT); 1079 } 1080 1081 static int 1082 dwc_attach(device_t dev) 1083 { 1084 uint8_t macaddr[ETHER_ADDR_LEN]; 1085 struct dwc_softc *sc; 1086 struct ifnet *ifp; 1087 int error; 1088 int reg; 1089 int i; 1090 1091 sc = device_get_softc(dev); 1092 sc->dev = dev; 1093 sc->mii_clk = MII_CLK_VAL; 1094 sc->rx_idx = 0; 1095 1096 sc->txcount = TX_DESC_COUNT; 1097 1098 if (bus_alloc_resources(dev, dwc_spec, sc->res)) { 1099 device_printf(dev, "could not allocate resources\n"); 1100 return (ENXIO); 1101 } 1102 1103 /* Memory interface */ 1104 sc->bst = rman_get_bustag(sc->res[0]); 1105 sc->bsh = rman_get_bushandle(sc->res[0]); 1106 1107 /* Read MAC before reset */ 1108 if (dwc_get_hwaddr(sc, macaddr)) { 1109 device_printf(sc->dev, "can't get mac\n"); 1110 return (ENXIO); 1111 } 1112 1113 /* Reset */ 1114 reg = READ4(sc, BUS_MODE); 1115 reg |= (BUS_MODE_SWR); 1116 WRITE4(sc, BUS_MODE, reg); 1117 1118 for (i = 0; i < MAC_RESET_TIMEOUT; i++) { 1119 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 1120 break; 1121 DELAY(10); 1122 } 1123 if (i >= MAC_RESET_TIMEOUT) { 1124 device_printf(sc->dev, "Can't reset DWC.\n"); 1125 return (ENXIO); 1126 } 1127 1128 reg = READ4(sc, BUS_MODE); 1129 reg |= (BUS_MODE_EIGHTXPBL); 1130 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); 1131 WRITE4(sc, BUS_MODE, reg); 1132 1133 /* 1134 * DMA must be stop while changing descriptor list addresses. 1135 */ 1136 reg = READ4(sc, OPERATION_MODE); 1137 reg &= ~(MODE_ST | MODE_SR); 1138 WRITE4(sc, OPERATION_MODE, reg); 1139 1140 if (setup_dma(sc)) 1141 return (ENXIO); 1142 1143 /* Setup addresses */ 1144 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 1145 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 1146 1147 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), 1148 MTX_NETWORK_LOCK, MTX_DEF); 1149 1150 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); 1151 1152 /* Setup interrupt handler. */ 1153 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 1154 NULL, dwc_intr, sc, &sc->intr_cookie); 1155 if (error != 0) { 1156 device_printf(dev, "could not setup interrupt handler.\n"); 1157 return (ENXIO); 1158 } 1159 1160 /* Set up the ethernet interface. */ 1161 sc->ifp = ifp = if_alloc(IFT_ETHER); 1162 1163 ifp->if_softc = sc; 1164 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1165 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1166 ifp->if_capabilities = IFCAP_VLAN_MTU; 1167 ifp->if_capenable = ifp->if_capabilities; 1168 ifp->if_start = dwc_txstart; 1169 ifp->if_ioctl = dwc_ioctl; 1170 ifp->if_init = dwc_init; 1171 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1172 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1173 IFQ_SET_READY(&ifp->if_snd); 1174 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1175 1176 /* Attach the mii driver. */ 1177 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, 1178 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 1179 MII_OFFSET_ANY, 0); 1180 1181 if (error != 0) { 1182 device_printf(dev, "PHY attach failed\n"); 1183 return (ENXIO); 1184 } 1185 sc->mii_softc = device_get_softc(sc->miibus); 1186 1187 /* All ready to run, attach the ethernet interface. */ 1188 ether_ifattach(ifp, macaddr); 1189 sc->is_attached = true; 1190 1191 return (0); 1192 } 1193 1194 static int 1195 dwc_miibus_read_reg(device_t dev, int phy, int reg) 1196 { 1197 struct dwc_softc *sc; 1198 uint16_t mii; 1199 size_t cnt; 1200 int rv = 0; 1201 1202 sc = device_get_softc(dev); 1203 1204 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1205 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1206 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1207 | GMII_ADDRESS_GB; /* Busy flag */ 1208 1209 WRITE4(sc, GMII_ADDRESS, mii); 1210 1211 for (cnt = 0; cnt < 1000; cnt++) { 1212 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1213 rv = READ4(sc, GMII_DATA); 1214 break; 1215 } 1216 DELAY(10); 1217 } 1218 1219 return rv; 1220 } 1221 1222 static int 1223 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) 1224 { 1225 struct dwc_softc *sc; 1226 uint16_t mii; 1227 size_t cnt; 1228 1229 sc = device_get_softc(dev); 1230 1231 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) 1232 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) 1233 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) 1234 | GMII_ADDRESS_GB | GMII_ADDRESS_GW; 1235 1236 WRITE4(sc, GMII_DATA, val); 1237 WRITE4(sc, GMII_ADDRESS, mii); 1238 1239 for (cnt = 0; cnt < 1000; cnt++) { 1240 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { 1241 break; 1242 } 1243 DELAY(10); 1244 } 1245 1246 return (0); 1247 } 1248 1249 static void 1250 dwc_miibus_statchg(device_t dev) 1251 { 1252 struct dwc_softc *sc; 1253 struct mii_data *mii; 1254 int reg; 1255 1256 /* 1257 * Called by the MII bus driver when the PHY establishes 1258 * link to set the MAC interface registers. 1259 */ 1260 1261 sc = device_get_softc(dev); 1262 1263 DWC_ASSERT_LOCKED(sc); 1264 1265 mii = sc->mii_softc; 1266 1267 if (mii->mii_media_status & IFM_ACTIVE) 1268 sc->link_is_up = true; 1269 else 1270 sc->link_is_up = false; 1271 1272 reg = READ4(sc, MAC_CONFIGURATION); 1273 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1274 case IFM_1000_T: 1275 case IFM_1000_SX: 1276 reg &= ~(CONF_FES | CONF_PS); 1277 break; 1278 case IFM_100_TX: 1279 reg |= (CONF_FES | CONF_PS); 1280 break; 1281 case IFM_10_T: 1282 reg &= ~(CONF_FES); 1283 reg |= (CONF_PS); 1284 break; 1285 case IFM_NONE: 1286 sc->link_is_up = false; 1287 return; 1288 default: 1289 sc->link_is_up = false; 1290 device_printf(dev, "Unsupported media %u\n", 1291 IFM_SUBTYPE(mii->mii_media_active)); 1292 return; 1293 } 1294 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1295 reg |= (CONF_DM); 1296 else 1297 reg &= ~(CONF_DM); 1298 WRITE4(sc, MAC_CONFIGURATION, reg); 1299 } 1300 1301 static device_method_t dwc_methods[] = { 1302 DEVMETHOD(device_probe, dwc_probe), 1303 DEVMETHOD(device_attach, dwc_attach), 1304 1305 /* MII Interface */ 1306 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), 1307 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), 1308 DEVMETHOD(miibus_statchg, dwc_miibus_statchg), 1309 1310 { 0, 0 } 1311 }; 1312 1313 static driver_t dwc_driver = { 1314 "dwc", 1315 dwc_methods, 1316 sizeof(struct dwc_softc), 1317 }; 1318 1319 static devclass_t dwc_devclass; 1320 1321 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); 1322 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); 1323 1324 MODULE_DEPEND(dwc, ether, 1, 1, 1); 1325 MODULE_DEPEND(dwc, miibus, 1, 1, 1); 1326