xref: /freebsd/sys/dev/dwc/if_dwc.c (revision 4ce386ff25d77954b8cfa11534f632172e848244)
1 /*-
2  * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3  * All rights reserved.
4  *
5  * This software was developed by SRI International and the University of
6  * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7  * ("CTSRD"), as part of the DARPA CRASH research programme.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  */
30 
31 /*
32  * Ethernet media access controller (EMAC)
33  * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
34  *
35  * EMAC is an instance of the Synopsys DesignWare 3504-0
36  * Universal 10/100/1000 Ethernet MAC (DWC_gmac).
37  */
38 
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
41 
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/bus.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/malloc.h>
48 #include <sys/rman.h>
49 #include <sys/timeet.h>
50 #include <sys/timetc.h>
51 #include <sys/endian.h>
52 #include <sys/lock.h>
53 #include <sys/mbuf.h>
54 #include <sys/mutex.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/sysctl.h>
58 
59 #include <dev/fdt/fdt_common.h>
60 #include <dev/ofw/openfirm.h>
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/ofw_bus_subr.h>
63 
64 #include <net/bpf.h>
65 #include <net/if.h>
66 #include <net/ethernet.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
70 #include <net/if_var.h>
71 #include <net/if_vlan_var.h>
72 
73 #include <machine/bus.h>
74 #include <machine/fdt.h>
75 #include <machine/cpu.h>
76 #include <machine/intr.h>
77 
78 #include <dev/mii/mii.h>
79 #include <dev/mii/miivar.h>
80 #include "miibus_if.h"
81 
82 #define	READ4(_sc, _reg) \
83 	bus_read_4((_sc)->res[0], _reg)
84 #define	WRITE4(_sc, _reg, _val) \
85 	bus_write_4((_sc)->res[0], _reg, _val)
86 
87 #define	MAC_RESET_TIMEOUT	100
88 #define	WATCHDOG_TIMEOUT_SECS	5
89 #define	STATS_HARVEST_INTERVAL	2
90 #define	MII_CLK_VAL		2
91 
92 #include <dev/dwc/if_dwc.h>
93 
94 #define	DWC_LOCK(sc)			mtx_lock(&(sc)->mtx)
95 #define	DWC_UNLOCK(sc)			mtx_unlock(&(sc)->mtx)
96 #define	DWC_ASSERT_LOCKED(sc)		mtx_assert(&(sc)->mtx, MA_OWNED);
97 #define	DWC_ASSERT_UNLOCKED(sc)		mtx_assert(&(sc)->mtx, MA_NOTOWNED);
98 
99 #define	DDESC_TDES0_OWN			(1 << 31)
100 #define	DDESC_TDES0_TXINT		(1 << 30)
101 #define	DDESC_TDES0_TXLAST		(1 << 29)
102 #define	DDESC_TDES0_TXFIRST		(1 << 28)
103 #define	DDESC_TDES0_TXCRCDIS		(1 << 27)
104 #define	DDESC_TDES0_TXRINGEND		(1 << 21)
105 #define	DDESC_TDES0_TXCHAIN		(1 << 20)
106 
107 #define	DDESC_RDES0_OWN			(1 << 31)
108 #define	DDESC_RDES0_FL_MASK		0x3fff
109 #define	DDESC_RDES0_FL_SHIFT		16	/* Frame Length */
110 #define	DDESC_RDES1_CHAINED		(1 << 14)
111 
112 struct dwc_bufmap {
113 	bus_dmamap_t	map;
114 	struct mbuf	*mbuf;
115 };
116 
117 /*
118  * A hardware buffer descriptor.  Rx and Tx buffers have the same descriptor
119  * layout, but the bits in the flags field have different meanings.
120  */
121 struct dwc_hwdesc
122 {
123 	uint32_t tdes0;
124 	uint32_t tdes1;
125 	uint32_t addr;		/* pointer to buffer data */
126 	uint32_t addr_next;	/* link to next descriptor */
127 };
128 
129 /*
130  * Driver data and defines.
131  */
132 #define	RX_DESC_COUNT	1024
133 #define	RX_DESC_SIZE	(sizeof(struct dwc_hwdesc) * RX_DESC_COUNT)
134 #define	TX_DESC_COUNT	1024
135 #define	TX_DESC_SIZE	(sizeof(struct dwc_hwdesc) * TX_DESC_COUNT)
136 
137 /*
138  * The hardware imposes alignment restrictions on various objects involved in
139  * DMA transfers.  These values are expressed in bytes (not bits).
140  */
141 #define	DWC_DESC_RING_ALIGN		2048
142 
143 struct dwc_softc {
144 	struct resource		*res[2];
145 	bus_space_tag_t		bst;
146 	bus_space_handle_t	bsh;
147 	device_t		dev;
148 	int			mii_clk;
149 	device_t		miibus;
150 	struct mii_data *	mii_softc;
151 	struct ifnet		*ifp;
152 	int			if_flags;
153 	struct mtx		mtx;
154 	void *			intr_cookie;
155 	struct callout		dwc_callout;
156 	uint8_t			phy_conn_type;
157 	uint8_t			mactype;
158 	boolean_t		link_is_up;
159 	boolean_t		is_attached;
160 	boolean_t		is_detaching;
161 	int			tx_watchdog_count;
162 	int			stats_harvest_count;
163 
164 	/* RX */
165 	bus_dma_tag_t		rxdesc_tag;
166 	bus_dmamap_t		rxdesc_map;
167 	struct dwc_hwdesc	*rxdesc_ring;
168 	bus_addr_t		rxdesc_ring_paddr;
169 	bus_dma_tag_t		rxbuf_tag;
170 	struct dwc_bufmap	rxbuf_map[RX_DESC_COUNT];
171 	uint32_t		rx_idx;
172 
173 	/* TX */
174 	bus_dma_tag_t		txdesc_tag;
175 	bus_dmamap_t		txdesc_map;
176 	struct dwc_hwdesc	*txdesc_ring;
177 	bus_addr_t		txdesc_ring_paddr;
178 	bus_dma_tag_t		txbuf_tag;
179 	struct dwc_bufmap	txbuf_map[RX_DESC_COUNT];
180 	uint32_t		tx_idx_head;
181 	uint32_t		tx_idx_tail;
182 	int			txcount;
183 };
184 
185 static struct resource_spec dwc_spec[] = {
186 	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
187 	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
188 	{ -1, 0 }
189 };
190 
191 static void dwc_txfinish_locked(struct dwc_softc *sc);
192 static void dwc_rxfinish_locked(struct dwc_softc *sc);
193 static void dwc_stop_locked(struct dwc_softc *sc);
194 static void dwc_setup_rxfilter(struct dwc_softc *sc);
195 
196 static inline uint32_t
197 next_rxidx(struct dwc_softc *sc, uint32_t curidx)
198 {
199 
200 	return ((curidx + 1) % RX_DESC_COUNT);
201 }
202 
203 static inline uint32_t
204 next_txidx(struct dwc_softc *sc, uint32_t curidx)
205 {
206 
207 	return ((curidx + 1) % TX_DESC_COUNT);
208 }
209 
210 static void
211 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
212 {
213 
214 	if (error != 0)
215 		return;
216 	*(bus_addr_t *)arg = segs[0].ds_addr;
217 }
218 
219 inline static uint32_t
220 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr,
221     uint32_t len)
222 {
223 	uint32_t flags;
224 	uint32_t nidx;
225 
226 	nidx = next_txidx(sc, idx);
227 
228 	/* Addr/len 0 means we're clearing the descriptor after xmit done. */
229 	if (paddr == 0 || len == 0) {
230 		flags = 0;
231 		--sc->txcount;
232 	} else {
233 		flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST
234 		    | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT;
235 		++sc->txcount;
236 	}
237 
238 	sc->txdesc_ring[idx].addr = (uint32_t)(paddr);
239 	sc->txdesc_ring[idx].tdes0 = flags;
240 	sc->txdesc_ring[idx].tdes1 = len;
241 
242 	if (paddr && len) {
243 		wmb();
244 		sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN;
245 		wmb();
246 	}
247 
248 	return (nidx);
249 }
250 
251 static int
252 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp)
253 {
254 	struct bus_dma_segment seg;
255 	int error, nsegs;
256 	struct mbuf * m;
257 
258 	if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
259 		return (ENOMEM);
260 	*mp = m;
261 
262 	error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
263 	    m, &seg, &nsegs, 0);
264 	if (error != 0) {
265 		return (ENOMEM);
266 	}
267 
268 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
269 
270 	bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
271 	    BUS_DMASYNC_PREWRITE);
272 
273 	sc->txbuf_map[idx].mbuf = m;
274 
275 	dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
276 
277 	return (0);
278 }
279 
280 static void
281 dwc_txstart_locked(struct dwc_softc *sc)
282 {
283 	struct ifnet *ifp;
284 	struct mbuf *m;
285 	int enqueued;
286 
287 	DWC_ASSERT_LOCKED(sc);
288 
289 	if (!sc->link_is_up)
290 		return;
291 
292 	ifp = sc->ifp;
293 
294 	if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
295 		return;
296 	}
297 
298 	enqueued = 0;
299 
300 	for (;;) {
301 		if (sc->txcount == (TX_DESC_COUNT-1)) {
302 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
303 			break;
304 		}
305 
306 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
307 		if (m == NULL)
308 			break;
309 		if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
310 			IFQ_DRV_PREPEND(&ifp->if_snd, m);
311 			break;
312 		}
313 		BPF_MTAP(ifp, m);
314 		sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
315 		++enqueued;
316 	}
317 
318 	if (enqueued != 0) {
319 		WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1);
320 		sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
321 	}
322 }
323 
324 static void
325 dwc_txstart(struct ifnet *ifp)
326 {
327 	struct dwc_softc *sc = ifp->if_softc;
328 
329 	DWC_LOCK(sc);
330 	dwc_txstart_locked(sc);
331 	DWC_UNLOCK(sc);
332 }
333 
334 static void
335 dwc_stop_locked(struct dwc_softc *sc)
336 {
337 	struct ifnet *ifp;
338 	int reg;
339 
340 	DWC_ASSERT_LOCKED(sc);
341 
342 	ifp = sc->ifp;
343 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
344 	sc->tx_watchdog_count = 0;
345 	sc->stats_harvest_count = 0;
346 
347 	callout_stop(&sc->dwc_callout);
348 
349 	/* Stop DMA TX */
350 	reg = READ4(sc, OPERATION_MODE);
351 	reg &= ~(MODE_ST);
352 	WRITE4(sc, OPERATION_MODE, reg);
353 
354 	/* Flush TX */
355 	reg = READ4(sc, OPERATION_MODE);
356 	reg |= (MODE_FTF);
357 	WRITE4(sc, OPERATION_MODE, reg);
358 
359 	/* Stop transmitters */
360 	reg = READ4(sc, MAC_CONFIGURATION);
361 	reg &= ~(CONF_TE | CONF_RE);
362 	WRITE4(sc, MAC_CONFIGURATION, reg);
363 
364 	/* Stop DMA RX */
365 	reg = READ4(sc, OPERATION_MODE);
366 	reg &= ~(MODE_SR);
367 	WRITE4(sc, OPERATION_MODE, reg);
368 }
369 
370 static void dwc_clear_stats(struct dwc_softc *sc)
371 {
372 	int reg;
373 
374 	reg = READ4(sc, MMC_CONTROL);
375 	reg |= (MMC_CONTROL_CNTRST);
376 	WRITE4(sc, MMC_CONTROL, reg);
377 }
378 
379 static void
380 dwc_harvest_stats(struct dwc_softc *sc)
381 {
382 	struct ifnet *ifp;
383 
384 	/* We don't need to harvest too often. */
385 	if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
386 		return;
387 
388 	sc->stats_harvest_count = 0;
389 	ifp = sc->ifp;
390 
391 	if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB));
392 	if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G));
393 	if_inc_counter(ifp, IFCOUNTER_IERRORS,
394 	    READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) +
395 	    READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) +
396 	    READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) +
397 	    READ4(sc, RXLENGTHERROR));
398 
399 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G));
400 	if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G));
401 	if_inc_counter(ifp, IFCOUNTER_OERRORS,
402 	    READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) +
403 	    READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR));
404 
405 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
406 	    READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL));
407 
408 	dwc_clear_stats(sc);
409 }
410 
411 static void
412 dwc_tick(void *arg)
413 {
414 	struct dwc_softc *sc;
415 	struct ifnet *ifp;
416 	int link_was_up;
417 
418 	sc = arg;
419 
420 	DWC_ASSERT_LOCKED(sc);
421 
422 	ifp = sc->ifp;
423 
424 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
425 	    return;
426 
427 	/*
428 	 * Typical tx watchdog.  If this fires it indicates that we enqueued
429 	 * packets for output and never got a txdone interrupt for them.  Maybe
430 	 * it's a missed interrupt somehow, just pretend we got one.
431 	 */
432 	if (sc->tx_watchdog_count > 0) {
433 		if (--sc->tx_watchdog_count == 0) {
434 			dwc_txfinish_locked(sc);
435 		}
436 	}
437 
438 	/* Gather stats from hardware counters. */
439 	dwc_harvest_stats(sc);
440 
441 	/* Check the media status. */
442 	link_was_up = sc->link_is_up;
443 	mii_tick(sc->mii_softc);
444 	if (sc->link_is_up && !link_was_up)
445 		dwc_txstart_locked(sc);
446 
447 	/* Schedule another check one second from now. */
448 	callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
449 }
450 
451 static void
452 dwc_init_locked(struct dwc_softc *sc)
453 {
454 	struct ifnet *ifp = sc->ifp;
455 	int reg;
456 
457 	DWC_ASSERT_LOCKED(sc);
458 
459 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
460 		return;
461 
462 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
463 
464 	dwc_setup_rxfilter(sc);
465 
466 	/* Initializa DMA and enable transmitters */
467 	reg = READ4(sc, OPERATION_MODE);
468 	reg |= (MODE_TSF | MODE_OSF | MODE_FUF);
469 	reg &= ~(MODE_RSF);
470 	reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
471 	WRITE4(sc, OPERATION_MODE, reg);
472 
473 	WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
474 
475 	/* Start DMA */
476 	reg = READ4(sc, OPERATION_MODE);
477 	reg |= (MODE_ST | MODE_SR);
478 	WRITE4(sc, OPERATION_MODE, reg);
479 
480 	/* Enable transmitters */
481 	reg = READ4(sc, MAC_CONFIGURATION);
482 	reg |= (CONF_JD | CONF_ACS | CONF_BE);
483 	reg |= (CONF_TE | CONF_RE);
484 	WRITE4(sc, MAC_CONFIGURATION, reg);
485 
486 	/*
487 	 * Call mii_mediachg() which will call back into dwc_miibus_statchg()
488 	 * to set up the remaining config registers based on current media.
489 	 */
490 	mii_mediachg(sc->mii_softc);
491 	callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
492 }
493 
494 static void
495 dwc_init(void *if_softc)
496 {
497 	struct dwc_softc *sc = if_softc;
498 
499 	DWC_LOCK(sc);
500 	dwc_init_locked(sc);
501 	DWC_UNLOCK(sc);
502 }
503 
504 inline static uint32_t
505 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr)
506 {
507 	uint32_t nidx;
508 
509 	sc->rxdesc_ring[idx].addr = (uint32_t)paddr;
510 	nidx = next_rxidx(sc, idx);
511 	sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr +	\
512 	    (nidx * sizeof(struct dwc_hwdesc));
513 	sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES;
514 
515 	wmb();
516 	sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN;
517 	wmb();
518 
519 	return (nidx);
520 }
521 
522 static int
523 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m)
524 {
525 	struct bus_dma_segment seg;
526 	int error, nsegs;
527 
528 	m_adj(m, ETHER_ALIGN);
529 
530 	error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
531 	    m, &seg, &nsegs, 0);
532 	if (error != 0) {
533 		return (error);
534 	}
535 
536 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
537 
538 	bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
539 	    BUS_DMASYNC_PREREAD);
540 
541 	sc->rxbuf_map[idx].mbuf = m;
542 	dwc_setup_rxdesc(sc, idx, seg.ds_addr);
543 
544 	return (0);
545 }
546 
547 static struct mbuf *
548 dwc_alloc_mbufcl(struct dwc_softc *sc)
549 {
550 	struct mbuf *m;
551 
552 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
553 	m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
554 
555 	return (m);
556 }
557 
558 static void
559 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
560 {
561 	struct dwc_softc *sc;
562 	struct mii_data *mii;
563 
564 	sc = ifp->if_softc;
565 	mii = sc->mii_softc;
566 	DWC_LOCK(sc);
567 	mii_pollstat(mii);
568 	ifmr->ifm_active = mii->mii_media_active;
569 	ifmr->ifm_status = mii->mii_media_status;
570 	DWC_UNLOCK(sc);
571 }
572 
573 static int
574 dwc_media_change_locked(struct dwc_softc *sc)
575 {
576 
577 	return (mii_mediachg(sc->mii_softc));
578 }
579 
580 static int
581 dwc_media_change(struct ifnet * ifp)
582 {
583 	struct dwc_softc *sc;
584 	int error;
585 
586 	sc = ifp->if_softc;
587 
588 	DWC_LOCK(sc);
589 	error = dwc_media_change_locked(sc);
590 	DWC_UNLOCK(sc);
591 	return (error);
592 }
593 
594 static const uint8_t nibbletab[] = {
595 	/* 0x0 0000 -> 0000 */  0x0,
596 	/* 0x1 0001 -> 1000 */  0x8,
597 	/* 0x2 0010 -> 0100 */  0x4,
598 	/* 0x3 0011 -> 1100 */  0xc,
599 	/* 0x4 0100 -> 0010 */  0x2,
600 	/* 0x5 0101 -> 1010 */  0xa,
601 	/* 0x6 0110 -> 0110 */  0x6,
602 	/* 0x7 0111 -> 1110 */  0xe,
603 	/* 0x8 1000 -> 0001 */  0x1,
604 	/* 0x9 1001 -> 1001 */  0x9,
605 	/* 0xa 1010 -> 0101 */  0x5,
606 	/* 0xb 1011 -> 1101 */  0xd,
607 	/* 0xc 1100 -> 0011 */  0x3,
608 	/* 0xd 1101 -> 1011 */  0xb,
609 	/* 0xe 1110 -> 0111 */  0x7,
610 	/* 0xf 1111 -> 1111 */  0xf, };
611 
612 static uint8_t
613 bitreverse(uint8_t x)
614 {
615 
616 	return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4];
617 }
618 
619 static void
620 dwc_setup_rxfilter(struct dwc_softc *sc)
621 {
622 	struct ifmultiaddr *ifma;
623 	struct ifnet *ifp;
624 	uint8_t *eaddr;
625 	uint32_t crc;
626 	uint8_t val;
627 	int hashbit;
628 	int hashreg;
629 	int ffval;
630 	int reg;
631 	int lo;
632 	int hi;
633 
634 	DWC_ASSERT_LOCKED(sc);
635 
636 	ifp = sc->ifp;
637 
638 	/*
639 	 * Set the multicast (group) filter hash.
640 	 */
641 	if ((ifp->if_flags & IFF_ALLMULTI))
642 		ffval = (FRAME_FILTER_PM);
643 	else {
644 		ffval = (FRAME_FILTER_HMC);
645 		if_maddr_rlock(ifp);
646 		TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
647 			if (ifma->ifma_addr->sa_family != AF_LINK)
648 				continue;
649 			crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
650 				ifma->ifma_addr), ETHER_ADDR_LEN);
651 
652 			/* Take lower 8 bits and reverse it */
653 			val = bitreverse(~crc & 0xff);
654 			hashreg = (val >> 5);
655 			hashbit = (val & 31);
656 
657 			reg = READ4(sc, HASH_TABLE_REG(hashreg));
658 			reg |= (1 << hashbit);
659 			WRITE4(sc, HASH_TABLE_REG(hashreg), reg);
660 		}
661 		if_maddr_runlock(ifp);
662 	}
663 
664 	/*
665 	 * Set the individual address filter hash.
666 	 */
667 	if (ifp->if_flags & IFF_PROMISC)
668 		ffval |= (FRAME_FILTER_PR);
669 
670 	/*
671 	 * Set the primary address.
672 	 */
673 	eaddr = IF_LLADDR(ifp);
674 	lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) |
675 	    (eaddr[3] << 24);
676 	hi = eaddr[4] | (eaddr[5] << 8);
677 	WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
678 	WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
679 	WRITE4(sc, MAC_FRAME_FILTER, ffval);
680 }
681 
682 static int
683 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
684 {
685 	struct dwc_softc *sc;
686 	struct mii_data *mii;
687 	struct ifreq *ifr;
688 	int mask, error;
689 
690 	sc = ifp->if_softc;
691 	ifr = (struct ifreq *)data;
692 
693 	error = 0;
694 	switch (cmd) {
695 	case SIOCSIFFLAGS:
696 		DWC_LOCK(sc);
697 		if (ifp->if_flags & IFF_UP) {
698 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
699 				if ((ifp->if_flags ^ sc->if_flags) &
700 				    (IFF_PROMISC | IFF_ALLMULTI))
701 					dwc_setup_rxfilter(sc);
702 			} else {
703 				if (!sc->is_detaching)
704 					dwc_init_locked(sc);
705 			}
706 		} else {
707 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
708 				dwc_stop_locked(sc);
709 		}
710 		sc->if_flags = ifp->if_flags;
711 		DWC_UNLOCK(sc);
712 		break;
713 	case SIOCADDMULTI:
714 	case SIOCDELMULTI:
715 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
716 			DWC_LOCK(sc);
717 			dwc_setup_rxfilter(sc);
718 			DWC_UNLOCK(sc);
719 		}
720 		break;
721 	case SIOCSIFMEDIA:
722 	case SIOCGIFMEDIA:
723 		mii = sc->mii_softc;
724 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
725 		break;
726 	case SIOCSIFCAP:
727 		mask = ifp->if_capenable ^ ifr->ifr_reqcap;
728 		if (mask & IFCAP_VLAN_MTU) {
729 			/* No work to do except acknowledge the change took */
730 			ifp->if_capenable ^= IFCAP_VLAN_MTU;
731 		}
732 		break;
733 
734 	default:
735 		error = ether_ioctl(ifp, cmd, data);
736 		break;
737 	}
738 
739 	return (error);
740 }
741 
742 static void
743 dwc_txfinish_locked(struct dwc_softc *sc)
744 {
745 	struct dwc_bufmap *bmap;
746 	struct dwc_hwdesc *desc;
747 	struct ifnet *ifp;
748 
749 	DWC_ASSERT_LOCKED(sc);
750 
751 	ifp = sc->ifp;
752 
753 	while (sc->tx_idx_tail != sc->tx_idx_head) {
754 		desc = &sc->txdesc_ring[sc->tx_idx_tail];
755 		if ((desc->tdes0 & DDESC_TDES0_OWN) != 0)
756 			break;
757 		bmap = &sc->txbuf_map[sc->tx_idx_tail];
758 		bus_dmamap_sync(sc->txbuf_tag, bmap->map,
759 		    BUS_DMASYNC_POSTWRITE);
760 		bus_dmamap_unload(sc->txbuf_tag, bmap->map);
761 		m_freem(bmap->mbuf);
762 		bmap->mbuf = NULL;
763 		dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
764 		sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
765 	}
766 
767 	/* If there are no buffers outstanding, muzzle the watchdog. */
768 	if (sc->tx_idx_tail == sc->tx_idx_head) {
769 		sc->tx_watchdog_count = 0;
770 	}
771 }
772 
773 static void
774 dwc_rxfinish_locked(struct dwc_softc *sc)
775 {
776 	struct ifnet *ifp;
777 	struct mbuf *m0;
778 	struct mbuf *m;
779 	int error;
780 	int rdes0;
781 	int idx;
782 	int len;
783 
784 	ifp = sc->ifp;
785 
786 	for (;;) {
787 		idx = sc->rx_idx;
788 
789 		rdes0 = sc->rxdesc_ring[idx].tdes0;
790 		if ((rdes0 & DDESC_RDES0_OWN) != 0)
791 			break;
792 
793 		bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
794 		    BUS_DMASYNC_POSTREAD);
795 		bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map);
796 
797 		len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK;
798 		if (len != 0) {
799 			m = sc->rxbuf_map[idx].mbuf;
800 			m->m_pkthdr.rcvif = ifp;
801 			m->m_pkthdr.len = len;
802 			m->m_len = len;
803 			if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
804 
805 			DWC_UNLOCK(sc);
806 			(*ifp->if_input)(ifp, m);
807 			DWC_LOCK(sc);
808 		} else {
809 			/* XXX Zero-length packet ? */
810 		}
811 
812 		if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) {
813 			if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) {
814 				/*
815 				 * XXX Now what?
816 				 * We've got a hole in the rx ring.
817 				 */
818 			}
819 		} else
820 			if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
821 
822 		sc->rx_idx = next_rxidx(sc, sc->rx_idx);
823 	}
824 }
825 
826 static void
827 dwc_intr(void *arg)
828 {
829 	struct dwc_softc *sc;
830 	uint32_t reg;
831 
832 	sc = arg;
833 
834 	DWC_LOCK(sc);
835 
836 	reg = READ4(sc, INTERRUPT_STATUS);
837 	if (reg) {
838 		mii_mediachg(sc->mii_softc);
839 		READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
840 	}
841 
842 	reg = READ4(sc, DMA_STATUS);
843 	if (reg & DMA_STATUS_NIS) {
844 		if (reg & DMA_STATUS_RI)
845 			dwc_rxfinish_locked(sc);
846 
847 		if (reg & DMA_STATUS_TI)
848 			dwc_txfinish_locked(sc);
849 	}
850 
851 	if (reg & DMA_STATUS_AIS) {
852 		if (reg & DMA_STATUS_FBI) {
853 			/* Fatal bus error */
854 			device_printf(sc->dev,
855 			    "Ethernet DMA error, restarting controller.\n");
856 			dwc_stop_locked(sc);
857 			dwc_init_locked(sc);
858 		}
859 	}
860 
861 	WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
862 	DWC_UNLOCK(sc);
863 }
864 
865 static int
866 setup_dma(struct dwc_softc *sc)
867 {
868 	struct mbuf *m;
869 	int error;
870 	int nidx;
871 	int idx;
872 
873 	/*
874 	 * Set up TX descriptor ring, descriptors, and dma maps.
875 	 */
876 	error = bus_dma_tag_create(
877 	    bus_get_dma_tag(sc->dev),	/* Parent tag. */
878 	    DWC_DESC_RING_ALIGN, 0,	/* alignment, boundary */
879 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
880 	    BUS_SPACE_MAXADDR,		/* highaddr */
881 	    NULL, NULL,			/* filter, filterarg */
882 	    TX_DESC_SIZE, 1, 		/* maxsize, nsegments */
883 	    TX_DESC_SIZE,		/* maxsegsize */
884 	    0,				/* flags */
885 	    NULL, NULL,			/* lockfunc, lockarg */
886 	    &sc->txdesc_tag);
887 	if (error != 0) {
888 		device_printf(sc->dev,
889 		    "could not create TX ring DMA tag.\n");
890 		goto out;
891 	}
892 
893 	error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
894 	    BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
895 	    &sc->txdesc_map);
896 	if (error != 0) {
897 		device_printf(sc->dev,
898 		    "could not allocate TX descriptor ring.\n");
899 		goto out;
900 	}
901 
902 	error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map,
903 	    sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr,
904 	    &sc->txdesc_ring_paddr, 0);
905 	if (error != 0) {
906 		device_printf(sc->dev,
907 		    "could not load TX descriptor ring map.\n");
908 		goto out;
909 	}
910 
911 	for (idx = 0; idx < TX_DESC_COUNT; idx++) {
912 		sc->txdesc_ring[idx].tdes0 = DDESC_TDES0_TXCHAIN;
913 		sc->txdesc_ring[idx].tdes1 = 0;
914 		nidx = next_txidx(sc, idx);
915 		sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + \
916 		    (nidx * sizeof(struct dwc_hwdesc));
917 	}
918 
919 	error = bus_dma_tag_create(
920 	    bus_get_dma_tag(sc->dev),	/* Parent tag. */
921 	    1, 0,			/* alignment, boundary */
922 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
923 	    BUS_SPACE_MAXADDR,		/* highaddr */
924 	    NULL, NULL,			/* filter, filterarg */
925 	    MCLBYTES, 1, 		/* maxsize, nsegments */
926 	    MCLBYTES,			/* maxsegsize */
927 	    0,				/* flags */
928 	    NULL, NULL,			/* lockfunc, lockarg */
929 	    &sc->txbuf_tag);
930 	if (error != 0) {
931 		device_printf(sc->dev,
932 		    "could not create TX ring DMA tag.\n");
933 		goto out;
934 	}
935 
936 	for (idx = 0; idx < TX_DESC_COUNT; idx++) {
937 		error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT,
938 		    &sc->txbuf_map[idx].map);
939 		if (error != 0) {
940 			device_printf(sc->dev,
941 			    "could not create TX buffer DMA map.\n");
942 			goto out;
943 		}
944 		dwc_setup_txdesc(sc, idx, 0, 0);
945 	}
946 
947 	/*
948 	 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
949 	 */
950 	error = bus_dma_tag_create(
951 	    bus_get_dma_tag(sc->dev),	/* Parent tag. */
952 	    DWC_DESC_RING_ALIGN, 0,	/* alignment, boundary */
953 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
954 	    BUS_SPACE_MAXADDR,		/* highaddr */
955 	    NULL, NULL,			/* filter, filterarg */
956 	    RX_DESC_SIZE, 1, 		/* maxsize, nsegments */
957 	    RX_DESC_SIZE,		/* maxsegsize */
958 	    0,				/* flags */
959 	    NULL, NULL,			/* lockfunc, lockarg */
960 	    &sc->rxdesc_tag);
961 	if (error != 0) {
962 		device_printf(sc->dev,
963 		    "could not create RX ring DMA tag.\n");
964 		goto out;
965 	}
966 
967 	error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
968 	    BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
969 	    &sc->rxdesc_map);
970 	if (error != 0) {
971 		device_printf(sc->dev,
972 		    "could not allocate RX descriptor ring.\n");
973 		goto out;
974 	}
975 
976 	error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map,
977 	    sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr,
978 	    &sc->rxdesc_ring_paddr, 0);
979 	if (error != 0) {
980 		device_printf(sc->dev,
981 		    "could not load RX descriptor ring map.\n");
982 		goto out;
983 	}
984 
985 	error = bus_dma_tag_create(
986 	    bus_get_dma_tag(sc->dev),	/* Parent tag. */
987 	    1, 0,			/* alignment, boundary */
988 	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
989 	    BUS_SPACE_MAXADDR,		/* highaddr */
990 	    NULL, NULL,			/* filter, filterarg */
991 	    MCLBYTES, 1, 		/* maxsize, nsegments */
992 	    MCLBYTES,			/* maxsegsize */
993 	    0,				/* flags */
994 	    NULL, NULL,			/* lockfunc, lockarg */
995 	    &sc->rxbuf_tag);
996 	if (error != 0) {
997 		device_printf(sc->dev,
998 		    "could not create RX buf DMA tag.\n");
999 		goto out;
1000 	}
1001 
1002 	for (idx = 0; idx < RX_DESC_COUNT; idx++) {
1003 		error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT,
1004 		    &sc->rxbuf_map[idx].map);
1005 		if (error != 0) {
1006 			device_printf(sc->dev,
1007 			    "could not create RX buffer DMA map.\n");
1008 			goto out;
1009 		}
1010 		if ((m = dwc_alloc_mbufcl(sc)) == NULL) {
1011 			device_printf(sc->dev, "Could not alloc mbuf\n");
1012 			error = ENOMEM;
1013 			goto out;
1014 		}
1015 		if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) {
1016 			device_printf(sc->dev,
1017 			    "could not create new RX buffer.\n");
1018 			goto out;
1019 		}
1020 	}
1021 
1022 out:
1023 	if (error != 0)
1024 		return (ENXIO);
1025 
1026 	return (0);
1027 }
1028 
1029 static int
1030 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr)
1031 {
1032 	int rnd;
1033 	int lo;
1034 	int hi;
1035 
1036 	/*
1037 	 * Try to recover a MAC address from the running hardware. If there's
1038 	 * something non-zero there, assume the bootloader did the right thing
1039 	 * and just use it.
1040 	 *
1041 	 * Otherwise, set the address to a convenient locally assigned address,
1042 	 * 'bsd' + random 24 low-order bits.  'b' is 0x62, which has the locally
1043 	 * assigned bit set, and the broadcast/multicast bit clear.
1044 	 */
1045 	lo = READ4(sc, MAC_ADDRESS_LOW(0));
1046 	hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff;
1047 	if ((lo != 0xffffffff) || (hi != 0xffff)) {
1048 		hwaddr[0] = (lo >>  0) & 0xff;
1049 		hwaddr[1] = (lo >>  8) & 0xff;
1050 		hwaddr[2] = (lo >> 16) & 0xff;
1051 		hwaddr[3] = (lo >> 24) & 0xff;
1052 		hwaddr[4] = (hi >>  0) & 0xff;
1053 		hwaddr[5] = (hi >>  8) & 0xff;
1054 	} else {
1055 		rnd = arc4random() & 0x00ffffff;
1056 		hwaddr[0] = 'b';
1057 		hwaddr[1] = 's';
1058 		hwaddr[2] = 'd';
1059 		hwaddr[3] = rnd >> 16;
1060 		hwaddr[4] = rnd >>  8;
1061 		hwaddr[5] = rnd >>  0;
1062 	}
1063 
1064 	return (0);
1065 }
1066 
1067 static int
1068 dwc_probe(device_t dev)
1069 {
1070 
1071 	if (!ofw_bus_status_okay(dev))
1072 		return (ENXIO);
1073 
1074 	if (!ofw_bus_is_compatible(dev, "snps,dwmac"))
1075 		return (ENXIO);
1076 
1077 	device_set_desc(dev, "Gigabit Ethernet Controller");
1078 	return (BUS_PROBE_DEFAULT);
1079 }
1080 
1081 static int
1082 dwc_attach(device_t dev)
1083 {
1084 	uint8_t macaddr[ETHER_ADDR_LEN];
1085 	struct dwc_softc *sc;
1086 	struct ifnet *ifp;
1087 	int error;
1088 	int reg;
1089 	int i;
1090 
1091 	sc = device_get_softc(dev);
1092 	sc->dev = dev;
1093 	sc->mii_clk = MII_CLK_VAL;
1094 	sc->rx_idx = 0;
1095 
1096 	sc->txcount = TX_DESC_COUNT;
1097 
1098 	if (bus_alloc_resources(dev, dwc_spec, sc->res)) {
1099 		device_printf(dev, "could not allocate resources\n");
1100 		return (ENXIO);
1101 	}
1102 
1103 	/* Memory interface */
1104 	sc->bst = rman_get_bustag(sc->res[0]);
1105 	sc->bsh = rman_get_bushandle(sc->res[0]);
1106 
1107 	/* Read MAC before reset */
1108 	if (dwc_get_hwaddr(sc, macaddr)) {
1109 		device_printf(sc->dev, "can't get mac\n");
1110 		return (ENXIO);
1111 	}
1112 
1113 	/* Reset */
1114 	reg = READ4(sc, BUS_MODE);
1115 	reg |= (BUS_MODE_SWR);
1116 	WRITE4(sc, BUS_MODE, reg);
1117 
1118 	for (i = 0; i < MAC_RESET_TIMEOUT; i++) {
1119 		if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)
1120 			break;
1121 		DELAY(10);
1122 	}
1123 	if (i >= MAC_RESET_TIMEOUT) {
1124 		device_printf(sc->dev, "Can't reset DWC.\n");
1125 		return (ENXIO);
1126 	}
1127 
1128 	reg = READ4(sc, BUS_MODE);
1129 	reg |= (BUS_MODE_EIGHTXPBL);
1130 	reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT);
1131 	WRITE4(sc, BUS_MODE, reg);
1132 
1133 	/*
1134 	 * DMA must be stop while changing descriptor list addresses.
1135 	 */
1136 	reg = READ4(sc, OPERATION_MODE);
1137 	reg &= ~(MODE_ST | MODE_SR);
1138 	WRITE4(sc, OPERATION_MODE, reg);
1139 
1140 	if (setup_dma(sc))
1141 	        return (ENXIO);
1142 
1143 	/* Setup addresses */
1144 	WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);
1145 	WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);
1146 
1147 	mtx_init(&sc->mtx, device_get_nameunit(sc->dev),
1148 	    MTX_NETWORK_LOCK, MTX_DEF);
1149 
1150 	callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0);
1151 
1152 	/* Setup interrupt handler. */
1153 	error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
1154 	    NULL, dwc_intr, sc, &sc->intr_cookie);
1155 	if (error != 0) {
1156 		device_printf(dev, "could not setup interrupt handler.\n");
1157 		return (ENXIO);
1158 	}
1159 
1160 	/* Set up the ethernet interface. */
1161 	sc->ifp = ifp = if_alloc(IFT_ETHER);
1162 
1163 	ifp->if_softc = sc;
1164 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1165 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1166 	ifp->if_capabilities = IFCAP_VLAN_MTU;
1167 	ifp->if_capenable = ifp->if_capabilities;
1168 	ifp->if_start = dwc_txstart;
1169 	ifp->if_ioctl = dwc_ioctl;
1170 	ifp->if_init = dwc_init;
1171 	IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1172 	ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1173 	IFQ_SET_READY(&ifp->if_snd);
1174 	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1175 
1176 	/* Attach the mii driver. */
1177 	error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change,
1178 	    dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY,
1179 	    MII_OFFSET_ANY, 0);
1180 
1181 	if (error != 0) {
1182 		device_printf(dev, "PHY attach failed\n");
1183 		return (ENXIO);
1184 	}
1185 	sc->mii_softc = device_get_softc(sc->miibus);
1186 
1187 	/* All ready to run, attach the ethernet interface. */
1188 	ether_ifattach(ifp, macaddr);
1189 	sc->is_attached = true;
1190 
1191 	return (0);
1192 }
1193 
1194 static int
1195 dwc_miibus_read_reg(device_t dev, int phy, int reg)
1196 {
1197 	struct dwc_softc *sc;
1198 	uint16_t mii;
1199 	size_t cnt;
1200 	int rv = 0;
1201 
1202 	sc = device_get_softc(dev);
1203 
1204 	mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1205 	    | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1206 	    | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1207 	    | GMII_ADDRESS_GB; /* Busy flag */
1208 
1209 	WRITE4(sc, GMII_ADDRESS, mii);
1210 
1211 	for (cnt = 0; cnt < 1000; cnt++) {
1212 		if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1213 			rv = READ4(sc, GMII_DATA);
1214 			break;
1215 		}
1216 		DELAY(10);
1217 	}
1218 
1219 	return rv;
1220 }
1221 
1222 static int
1223 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val)
1224 {
1225 	struct dwc_softc *sc;
1226 	uint16_t mii;
1227 	size_t cnt;
1228 
1229 	sc = device_get_softc(dev);
1230 
1231 	mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1232 	    | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1233 	    | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1234 	    | GMII_ADDRESS_GB | GMII_ADDRESS_GW;
1235 
1236 	WRITE4(sc, GMII_DATA, val);
1237 	WRITE4(sc, GMII_ADDRESS, mii);
1238 
1239 	for (cnt = 0; cnt < 1000; cnt++) {
1240 		if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1241 			break;
1242                 }
1243 		DELAY(10);
1244 	}
1245 
1246 	return (0);
1247 }
1248 
1249 static void
1250 dwc_miibus_statchg(device_t dev)
1251 {
1252 	struct dwc_softc *sc;
1253 	struct mii_data *mii;
1254 	int reg;
1255 
1256 	/*
1257 	 * Called by the MII bus driver when the PHY establishes
1258 	 * link to set the MAC interface registers.
1259 	 */
1260 
1261 	sc = device_get_softc(dev);
1262 
1263 	DWC_ASSERT_LOCKED(sc);
1264 
1265 	mii = sc->mii_softc;
1266 
1267 	if (mii->mii_media_status & IFM_ACTIVE)
1268 		sc->link_is_up = true;
1269 	else
1270 		sc->link_is_up = false;
1271 
1272 	reg = READ4(sc, MAC_CONFIGURATION);
1273 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
1274 	case IFM_1000_T:
1275 	case IFM_1000_SX:
1276 		reg &= ~(CONF_FES | CONF_PS);
1277 		break;
1278 	case IFM_100_TX:
1279 		reg |= (CONF_FES | CONF_PS);
1280 		break;
1281 	case IFM_10_T:
1282 		reg &= ~(CONF_FES);
1283 		reg |= (CONF_PS);
1284 		break;
1285 	case IFM_NONE:
1286 		sc->link_is_up = false;
1287 		return;
1288 	default:
1289 		sc->link_is_up = false;
1290 		device_printf(dev, "Unsupported media %u\n",
1291 		    IFM_SUBTYPE(mii->mii_media_active));
1292 		return;
1293 	}
1294 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1295 		reg |= (CONF_DM);
1296 	else
1297 		reg &= ~(CONF_DM);
1298 	WRITE4(sc, MAC_CONFIGURATION, reg);
1299 }
1300 
1301 static device_method_t dwc_methods[] = {
1302 	DEVMETHOD(device_probe,		dwc_probe),
1303 	DEVMETHOD(device_attach,	dwc_attach),
1304 
1305 	/* MII Interface */
1306 	DEVMETHOD(miibus_readreg,	dwc_miibus_read_reg),
1307 	DEVMETHOD(miibus_writereg,	dwc_miibus_write_reg),
1308 	DEVMETHOD(miibus_statchg,	dwc_miibus_statchg),
1309 
1310 	{ 0, 0 }
1311 };
1312 
1313 static driver_t dwc_driver = {
1314 	"dwc",
1315 	dwc_methods,
1316 	sizeof(struct dwc_softc),
1317 };
1318 
1319 static devclass_t dwc_devclass;
1320 
1321 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0);
1322 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0);
1323 
1324 MODULE_DEPEND(dwc, ether, 1, 1, 1);
1325 MODULE_DEPEND(dwc, miibus, 1, 1, 1);
1326