1 /*- 2 * Copyright (c) 2026 Ruslan Bukin <br@bsdpad.com> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #ifndef _DEV_DWC_DWC4_REG_H_ 27 #define _DEV_DWC_DWC4_REG_H_ 28 29 #define ETH_MACCR 0x0000 30 #define MACCR_IPC (1 << 27) /* Checksum Offload */ 31 #define MACCR_ACS (1 << 20) /* Automatic Pad or CRC Stripping */ 32 #define MACCR_BE (1 << 18) /* Packet Burst Enable */ 33 #define MACCR_JD (1 << 17) /* Jabber Disable */ 34 #define MACCR_PS (1 << 15) /* Port Select */ 35 #define MACCR_FES (1 << 14) /* MAC Speed */ 36 #define MACCR_DM (1 << 13) /* Duplex Mode */ 37 #define MACCR_TE (1 << 1) /* Transmitter Enable */ 38 #define MACCR_RE (1 << 0) /* Receiver Enable */ 39 #define ETH_MACECR 0x0004 40 #define ETH_MACPFR 0x0008 41 #define MACPFR_RA (1 << 31) /* Receive All */ 42 #define MACPFR_PM (1 << 4) /* Pass All Multicast */ 43 #define MACPFR_HMC (1 << 2) /* Hash Multicast */ 44 #define MACPFR_PR (1 << 0) /* Promiscuous Mode */ 45 #define ETH_MACWJBTR 0x000C 46 #define ETH_MACHT0R 0x0010 47 #define ETH_MACHT1R 0x0014 48 #define ETH_MACVTCR 0x0050 49 #define ETH_MACVTDR 0x0054 50 #define ETH_MACVHTR 0x0058 51 #define ETH_MACVIR 0x0060 52 #define ETH_MACiVIR 0x0064 53 #define ETH_MACQ0TXFCR 0x0070 54 #define ETH_MACRXFCR 0x0090 55 #define ETH_MACRXQCR 0x0094 56 57 #define ETH_MACRXQC0R(x) (0x00A0 + 0x4 * (x)) 58 #define MACRXQC0R_RXQ0EN_S 0 /* Receive Queue 0 Enable */ 59 #define MACRXQC0R_RXQ0EN_AV (0x1 << MACRXQC0R_RXQ0EN_S) 60 #define MACRXQC0R_RXQ0EN_GEN (0x2 << MACRXQC0R_RXQ0EN_S) 61 #define MACRXQC0R_RXQ0EN_M (0x3 << MACRXQC0R_RXQ0EN_S) 62 #define ETH_MACRXQC1R 0x00A4 63 #define ETH_MACRXQC2R 0x00A8 64 65 #define ETH_MACISR 0x00B0 66 #define ETH_MACIER 0x00B4 67 #define ETH_MACRXTXSR 0x00B8 68 #define ETH_MACPCSR 0x00C0 69 #define ETH_MACRWKPFR 0x00C4 70 #define ETH_MACLCSR 0x00D0 71 #define ETH_MACLTCR 0x00D4 72 #define ETH_MACLETR 0x00D8 73 #define ETH_MAC1USTCR 0x00DC 74 #define ETH_MACPHYCSR 0x00F8 75 #define ETH_MACVR 0x0110 76 #define ETH_MACDR 0x0114 77 #define ETH_MACHWF0R 0x011C 78 #define ETH_MACHWF1R 0x0120 79 #define ETH_MACHWF2R 0x0124 80 #define ETH_MACHWF3R 0x0128 81 #define ETH_MACMDIOAR 0x0200 82 #define MACMDIOAR_CR_S 8 /* CSR Clock Range */ 83 #define MACMDIOAR_CR_M (0xf << MACMDIOAR_CR_S) 84 #define MACMDIOAR_GOC_S 2 /* GMII Operation Command */ 85 #define MACMDIOAR_GOC_M (0x3 << MACMDIOAR_GOC_S) 86 #define MACMDIOAR_WRITE (0x1 << MACMDIOAR_GOC_S) 87 #define MACMDIOAR_POST_RD_INC (0x2 << MACMDIOAR_GOC_S) 88 #define MACMDIOAR_READ (0x3 << MACMDIOAR_GOC_S) 89 #define MACMDIOAR_GB (1 << 0) /* GMII Busy */ 90 #define MACMDIOAR_PA_S 21 /* Physical Layer Address */ 91 #define MACMDIOAR_PA_M (0x1f << MACMDIOAR_PA_S) 92 #define MACMDIOAR_RDA_S 16 /* Register/Device Address */ 93 #define MACMDIOAR_RDA_M (0x1f << MACMDIOAR_RDA_S) 94 #define ETH_MACMDIODR 0x0204 95 #define ETH_MACARPAR 0x0210 96 #define ETH_MACCSRSWCR 0x0230 97 #define ETH_MACFPECSR 0x0234 98 #define ETH_MACPRSTIMR 0x0240 99 #define ETH_MACPRSTIMUR 0x0244 100 #define ETH_MACA0HR 0x0300 101 #define ETH_MACA0LR 0x0304 102 #define ETH_MACA1HR 0x0308 103 #define ETH_MACA1LR 0x030C 104 #define ETH_MACA2HR 0x0310 105 #define ETH_MACA2LR 0x0314 106 #define ETH_MACA3HR 0x0318 107 #define ETH_MACA3LR 0x031C 108 #define ETH_MMC_CONTROL 0x0700 109 #define MMC_CONTROL_CNTRST (1 << 0) /* Counters Reset */ 110 #define ETH_MMC_RX_INTERRUPT 0x0704 111 #define ETH_MMC_TX_INTERRUPT 0x0708 112 #define ETH_MMC_RX_INTERRUPT_MASK 0x070C 113 #define ETH_MMC_TX_INTERRUPT_MASK 0x0710 114 #define ETH_TX_OCTET_COUNT_GOOD_BAD 0x0714 115 #define ETH_TX_PACKET_COUNT_GOOD_BAD 0x0718 116 #define ETH_TX_BROADCAST_PACKETS_GOOD 0x071C 117 #define ETH_TX_MULTICAST_PACKETS_GOOD 0x0720 118 #define ETH_TX_64OCTETS_PACKETS_GOOD_BAD 0x0724 119 #define ETH_TX_64TO127OCTETS_PACKETS_GOOD_BAD 0x0728 120 #define ETH_TX_128TO255OCTETS_PACKETS_GOOD_BAD 0x072C 121 #define ETH_TX_256TO511OCTETS_PACKETS_GOOD_BAD 0x0730 122 #define ETH_TX_512TO1023OCTETS_PACKETS_GOOD_BAD 0x0734 123 #define ETH_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD 0x0738 124 #define ETH_TX_UNICAST_PACKETS_GOOD_BAD 0x073C 125 #define ETH_TX_MULTICAST_PACKETS_GOOD_BAD 0x0740 126 #define ETH_TX_BROADCAST_PACKETS_GOOD_BAD 0x0744 127 #define ETH_TX_UNDERFLOW_ERROR_PACKETS 0x0748 128 #define ETH_TX_SINGLE_COLLISION_GOOD_PACKETS 0x074C 129 #define ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS 0x0750 130 #define ETH_TX_DEFERRED_PACKETS 0x0754 131 #define ETH_TX_LATE_COLLISION_PACKETS 0x0758 132 #define ETH_TX_EXCESSIVE_COLLISION_PACKETS 0x075C 133 #define ETH_TX_CARRIER_ERROR_PACKETS 0x0760 134 #define ETH_TX_OCTET_COUNT_GOOD 0x0764 135 #define ETH_TX_PACKET_COUNT_GOOD 0x0768 136 #define ETH_TX_EXCESSIVE_DEFERRAL_ERROR 0x076C 137 #define ETH_TX_PAUSE_PACKETS 0x0770 138 #define ETH_TX_VLAN_PACKETS_GOOD 0x0774 139 #define ETH_TX_OSIZE_PACKETS_GOOD 0x0778 140 #define ETH_RX_PACKETS_COUNT_GOOD_BAD 0x0780 141 #define ETH_RX_OCTET_COUNT_GOOD_BAD 0x0784 142 #define ETH_RX_OCTET_COUNT_GOOD 0x0788 143 #define ETH_RX_BROADCAST_PACKETS_GOOD 0x078C 144 #define ETH_RX_MULTICAST_PACKETS_GOOD 0x0790 145 #define ETH_RX_CRC_ERROR_PACKETS 0x0794 146 #define ETH_RX_ALIGNMENT_ERROR_PACKETS 0x0798 147 #define ETH_RX_RUNT_ERROR_PACKETS 0x079C 148 #define ETH_RX_JABBER_ERROR_PACKETS 0x07A0 149 #define ETH_RX_UNDERSIZE_PACKETS_GOOD 0x07A4 150 #define ETH_RX_OVERSIZE_PACKETS_GOOD 0x07A8 151 #define ETH_RX_64OCTETS_PACKETS_GOOD_BAD 0x07AC 152 #define ETH_RX_65TO127OCTETS_PACKETS_GOOD_BAD 0x07B0 153 #define ETH_RX_128TO255OCTETS_PACKETS_GOOD_BAD 0x07B4 154 #define ETH_RX_256TO511OCTETS_PACKETS_GOOD_BAD 0x07B8 155 #define ETH_RX_512TO1023OCTETS_PACKETS_GOOD_BAD 0x07BC 156 #define ETH_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD 0x07C0 157 #define ETH_RX_UNICAST_PACKETS_GOOD 0x07C4 158 #define ETH_RX_LENGTH_ERROR_PACKETS 0x07C8 159 #define ETH_RX_OUT_OF_RANGE_PACKETS 0x07CC 160 #define ETH_RX_PAUSE_PACKETS 0x07D0 161 #define ETH_RX_FIFO_OVERFLOW_PACKETS 0x07D4 162 #define ETH_RX_VLAN_PACKETS_GOOD_BAD 0x07D8 163 #define ETH_RX_WATCHDOG_ERROR_PACKETS 0x07DC 164 #define ETH_RX_RECEIVE_ERROR 0x07E0 165 #define ETH_RX_CONTROL_PACKETS_GOOD 0x07E4 166 #define ETH_TX_LPI_USEC_CNTR 0x07EC 167 #define ETH_TX_LPI_TRAN_CNTR 0x07F0 168 #define ETH_RX_LPI_USEC_CNTR 0x07F4 169 #define ETH_RX_LPI_TRAN_CNTR 0x07F8 170 #define ETH_MMC_FPE_TX_ISR 0x08A0 171 #define ETH_MMC_FPE_TX_IMR 0x08A4 172 #define ETH_MMC_FPE_TX_FCR 0x08A8 173 #define ETH_MMC_TX_HRCR 0x08AC 174 #define ETH_MMC_FPE_RX_ISR 0x08C0 175 #define ETH_MMC_FPE_RX_IMR 0x08C4 176 #define ETH_RX_PACKET_ASM_ERR 0x08C8 177 #define ETH_RX_PACKET_SMD_ERR 0x08CC 178 #define ETH_RX_PACKET_ASM_OKR 0x08D0 179 #define ETH_RX_FPE_FRAG_CR 0x08D4 180 #define ETH_MACL3L4C0R 0x0900 181 #define ETH_MACL4A0R 0x0904 182 #define ETH_MACL3A00R 0x0910 183 #define ETH_MACL3A10R 0x0914 184 #define ETH_MACL3A20R 0x0918 185 #define ETH_MACL3A30R 0x091C 186 #define ETH_MACL3L4C1R 0x0930 187 #define ETH_MACL4A1R 0x0934 188 #define ETH_MACL3A01R 0x0940 189 #define ETH_MACL3A11R 0x0944 190 #define ETH_MACL3A21R 0x0948 191 #define ETH_MACL3A31R 0x094C 192 #define ETH_MAC_IACR 0x0A70 193 #define ETH_MAC_TMRQR 0x0A74 194 #define ETH_MACTSCR 0x0B00 195 #define ETH_MACSSIR 0x0B04 196 #define ETH_MACSTSR 0x0B08 197 #define ETH_MACSTNR 0x0B0C 198 #define ETH_MACSTSUR 0x0B10 199 #define ETH_MACSTNUR 0x0B14 200 #define ETH_MACTSAR 0x0B18 201 #define ETH_MACTSSR 0x0B20 202 #define ETH_MACRXDTI 0x0B24 203 #define ETH_MACTXDTI 0x0B28 204 #define ETH_MACTXTSSNR 0x0B30 205 #define ETH_MACTXTSSSR 0x0B34 206 #define ETH_MACACR 0x0B40 207 #define ETH_MACATSNR 0x0B48 208 #define ETH_MACATSSR 0x0B4C 209 #define ETH_MACTSIACR 0x0B50 210 #define ETH_MACTSEACR 0x0B54 211 #define ETH_MACTSICNR 0x0B58 212 #define ETH_MACTSECNR 0x0B5C 213 #define ETH_MACTSILR 0x0B68 214 #define ETH_MACTSELR 0x0B6C 215 #define ETH_MACPPSCR 0x0B70 216 #define ETH_MACPPSTTS0R 0x0B80 217 #define ETH_MACPPSTTN0R 0x0B84 218 #define ETH_MACPPSI0R 0x0B88 219 #define ETH_MACPPSW0R 0x0B8C 220 #define ETH_MACPPSTTS1R 0x0B90 221 #define ETH_MACPPSTTN1R 0x0B94 222 #define ETH_MACPPSI1R 0x0B98 223 #define ETH_MACPPSW1R 0x0B9C 224 #define ETH_MACPOCR 0x0BC0 225 #define ETH_MACSPI0R 0x0BC4 226 #define ETH_MACSPI1R 0x0BC8 227 #define ETH_MACSPI2R 0x0BCC 228 #define ETH_MACLMIR 0x0BD0 229 230 int dwc4_miibus_read_reg(device_t dev, int phy, int reg); 231 int dwc4_miibus_write_reg(device_t dev, int phy, int reg, int val); 232 void dwc4_miibus_statchg(device_t dev); 233 void dwc4_core_setup(struct dwc_softc *sc); 234 void dwc4_enable_mac(struct dwc_softc *sc, bool enable); 235 void dwc4_enable_csum_offload(struct dwc_softc *sc); 236 void dwc4_setup_rxfilter(struct dwc_softc *sc); 237 void dwc4_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr); 238 void dwc4_harvest_stats(struct dwc_softc *sc); 239 void dwc4_intr(struct dwc_softc *softc); 240 void dwc4_intr_disable(struct dwc_softc *sc); 241 242 #endif /* !_DEV_DWC_DWC4_REG_H_ */ 243