1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * 4 * This software was developed by SRI International and the University of 5 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 6 * ("CTSRD"), as part of the DARPA CRASH research programme. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Register names were taken almost as is from the documentation. 32 */ 33 34 #ifndef __DWC1000_REG_H__ 35 #define __DWC1000_REG_H__ 36 37 #define MAC_CONFIGURATION 0x0 38 #define CONF_JD (1 << 22) /* jabber timer disable */ 39 #define CONF_BE (1 << 21) /* Frame Burst Enable */ 40 #define CONF_PS (1 << 15) /* GMII/MII */ 41 #define CONF_FES (1 << 14) /* MII speed select */ 42 #define CONF_DM (1 << 11) /* Full Duplex Enable */ 43 #define CONF_IPC (1 << 10) /* IPC checksum offload */ 44 #define CONF_ACS (1 << 7) 45 #define CONF_TE (1 << 3) 46 #define CONF_RE (1 << 2) 47 #define MAC_FRAME_FILTER 0x4 48 #define FRAME_FILTER_RA (1U << 31) /* Receive All */ 49 #define FRAME_FILTER_HPF (1 << 10) /* Hash or Perfect Filter */ 50 #define FRAME_FILTER_PM (1 << 4) /* Pass multicast */ 51 #define FRAME_FILTER_HMC (1 << 2) 52 #define FRAME_FILTER_HUC (1 << 1) 53 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */ 54 #define GMAC_MAC_HTHIGH 0x08 55 #define GMAC_MAC_HTLOW 0x0c 56 #define GMII_ADDRESS 0x10 57 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */ 58 #define GMII_ADDRESS_PA_SHIFT 11 59 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */ 60 #define GMII_ADDRESS_GR_SHIFT 6 61 #define GMII_ADDRESS_CR_MASK 0xf 62 #define GMII_ADDRESS_CR_SHIFT 2 /* Clock */ 63 #define GMII_ADDRESS_GW (1 << 1) /* Write operation */ 64 #define GMII_ADDRESS_GB (1 << 0) /* Busy */ 65 #define GMII_DATA 0x14 66 #define FLOW_CONTROL 0x18 67 #define FLOW_CONTROL_PT_SHIFT 16 68 #define FLOW_CONTROL_UP (1 << 3) /* Unicast pause enable */ 69 #define FLOW_CONTROL_RX (1 << 2) /* RX Flow control enable */ 70 #define FLOW_CONTROL_TX (1 << 1) /* TX Flow control enable */ 71 #define GMAC_VLAN_TAG 0x1C 72 #define VERSION 0x20 73 #define GMAC_DEBUG 0x24 74 #define LPI_CONTROL_STATUS 0x30 75 #define LPI_TIMERS_CONTROL 0x34 76 #define INTERRUPT_STATUS 0x38 77 #define INTERRUPT_MASK 0x3C 78 #define MAC_ADDRESS_HIGH(n) ((n > 15 ? 0x800 : 0x40) + 0x8 * n) 79 #define MAC_ADDRESS_LOW(n) ((n > 15 ? 0x804 : 0x44) + 0x8 * n) 80 81 #define SGMII_RGMII_SMII_CTRL_STATUS 0xD8 82 #define MMC_CONTROL 0x100 83 #define MMC_CONTROL_CNTRST (1 << 0) 84 #define MMC_RECEIVE_INTERRUPT 0x104 85 #define MMC_TRANSMIT_INTERRUPT 0x108 86 #define MMC_RECEIVE_INTERRUPT_MASK 0x10C 87 #define MMC_TRANSMIT_INTERRUPT_MASK 0x110 88 #define TXOCTETCOUNT_GB 0x114 89 #define TXFRAMECOUNT_GB 0x118 90 #define TXBROADCASTFRAMES_G 0x11C 91 #define TXMULTICASTFRAMES_G 0x120 92 #define TX64OCTETS_GB 0x124 93 #define TX65TO127OCTETS_GB 0x128 94 #define TX128TO255OCTETS_GB 0x12C 95 #define TX256TO511OCTETS_GB 0x130 96 #define TX512TO1023OCTETS_GB 0x134 97 #define TX1024TOMAXOCTETS_GB 0x138 98 #define TXUNICASTFRAMES_GB 0x13C 99 #define TXMULTICASTFRAMES_GB 0x140 100 #define TXBROADCASTFRAMES_GB 0x144 101 #define TXUNDERFLOWERROR 0x148 102 #define TXSINGLECOL_G 0x14C 103 #define TXMULTICOL_G 0x150 104 #define TXDEFERRED 0x154 105 #define TXLATECOL 0x158 106 #define TXEXESSCOL 0x15C 107 #define TXCARRIERERR 0x160 108 #define TXOCTETCNT 0x164 109 #define TXFRAMECOUNT_G 0x168 110 #define TXEXCESSDEF 0x16C 111 #define TXPAUSEFRAMES 0x170 112 #define TXVLANFRAMES_G 0x174 113 #define TXOVERSIZE_G 0x178 114 #define RXFRAMECOUNT_GB 0x180 115 #define RXOCTETCOUNT_GB 0x184 116 #define RXOCTETCOUNT_G 0x188 117 #define RXBROADCASTFRAMES_G 0x18C 118 #define RXMULTICASTFRAMES_G 0x190 119 #define RXCRCERROR 0x194 120 #define RXALIGNMENTERROR 0x198 121 #define RXRUNTERROR 0x19C 122 #define RXJABBERERROR 0x1A0 123 #define RXUNDERSIZE_G 0x1A4 124 #define RXOVERSIZE_G 0x1A8 125 #define RX64OCTETS_GB 0x1AC 126 #define RX65TO127OCTETS_GB 0x1B0 127 #define RX128TO255OCTETS_GB 0x1B4 128 #define RX256TO511OCTETS_GB 0x1B8 129 #define RX512TO1023OCTETS_GB 0x1BC 130 #define RX1024TOMAXOCTETS_GB 0x1C0 131 #define RXUNICASTFRAMES_G 0x1C4 132 #define RXLENGTHERROR 0x1C8 133 #define RXOUTOFRANGETYPE 0x1CC 134 #define RXPAUSEFRAMES 0x1D0 135 #define RXFIFOOVERFLOW 0x1D4 136 #define RXVLANFRAMES_GB 0x1D8 137 #define RXWATCHDOGERROR 0x1DC 138 #define RXRCVERROR 0x1E0 139 #define RXCTRLFRAMES_G 0x1E4 140 #define MMC_IPC_RECEIVE_INT_MASK 0x200 141 #define MMC_IPC_RECEIVE_INT 0x208 142 #define RXIPV4_GD_FRMS 0x210 143 #define RXIPV4_HDRERR_FRMS 0x214 144 #define RXIPV4_NOPAY_FRMS 0x218 145 #define RXIPV4_FRAG_FRMS 0x21C 146 #define RXIPV4_UDSBL_FRMS 0x220 147 #define RXIPV6_GD_FRMS 0x224 148 #define RXIPV6_HDRERR_FRMS 0x228 149 #define RXIPV6_NOPAY_FRMS 0x22C 150 #define RXUDP_GD_FRMS 0x230 151 #define RXUDP_ERR_FRMS 0x234 152 #define RXTCP_GD_FRMS 0x238 153 #define RXTCP_ERR_FRMS 0x23C 154 #define RXICMP_GD_FRMS 0x240 155 #define RXICMP_ERR_FRMS 0x244 156 #define RXIPV4_GD_OCTETS 0x250 157 #define RXIPV4_HDRERR_OCTETS 0x254 158 #define RXIPV4_NOPAY_OCTETS 0x258 159 #define RXIPV4_FRAG_OCTETS 0x25C 160 #define RXIPV4_UDSBL_OCTETS 0x260 161 #define RXIPV6_GD_OCTETS 0x264 162 #define RXIPV6_HDRERR_OCTETS 0x268 163 #define RXIPV6_NOPAY_OCTETS 0x26C 164 #define RXUDP_GD_OCTETS 0x270 165 #define RXUDP_ERR_OCTETS 0x274 166 #define RXTCP_GD_OCTETS 0x278 167 #define RXTCPERROCTETS 0x27C 168 #define RXICMP_GD_OCTETS 0x280 169 #define RXICMP_ERR_OCTETS 0x284 170 #define L3_L4_CONTROL0 0x400 171 #define LAYER4_ADDRESS0 0x404 172 #define LAYER3_ADDR0_REG0 0x410 173 #define LAYER3_ADDR1_REG0 0x414 174 #define LAYER3_ADDR2_REG0 0x418 175 #define LAYER3_ADDR3_REG0 0x41C 176 #define L3_L4_CONTROL1 0x430 177 #define LAYER4_ADDRESS1 0x434 178 #define LAYER3_ADDR0_REG1 0x440 179 #define LAYER3_ADDR1_REG1 0x444 180 #define LAYER3_ADDR2_REG1 0x448 181 #define LAYER3_ADDR3_REG1 0x44C 182 #define L3_L4_CONTROL2 0x460 183 #define LAYER4_ADDRESS2 0x464 184 #define LAYER3_ADDR0_REG2 0x470 185 #define LAYER3_ADDR1_REG2 0x474 186 #define LAYER3_ADDR2_REG2 0x478 187 #define LAYER3_ADDR3_REG2 0x47C 188 #define L3_L4_CONTROL3 0x490 189 #define LAYER4_ADDRESS3 0x494 190 #define LAYER3_ADDR0_REG3 0x4A0 191 #define LAYER3_ADDR1_REG3 0x4A4 192 #define LAYER3_ADDR2_REG3 0x4A8 193 #define LAYER3_ADDR3_REG3 0x4AC 194 #define HASH_TABLE_REG(n) 0x500 + (0x4 * n) 195 #define VLAN_INCL_REG 0x584 196 #define VLAN_HASH_TABLE_REG 0x588 197 #define TIMESTAMP_CONTROL 0x700 198 #define SUB_SECOND_INCREMENT 0x704 199 #define SYSTEM_TIME_SECONDS 0x708 200 #define SYSTEM_TIME_NANOSECONDS 0x70C 201 #define SYSTEM_TIME_SECONDS_UPDATE 0x710 202 #define SYSTEM_TIME_NANOSECONDS_UPDATE 0x714 203 #define TIMESTAMP_ADDEND 0x718 204 #define TARGET_TIME_SECONDS 0x71C 205 #define TARGET_TIME_NANOSECONDS 0x720 206 #define SYSTEM_TIME_HIGHER_WORD_SECONDS 0x724 207 #define TIMESTAMP_STATUS 0x728 208 #define PPS_CONTROL 0x72C 209 #define AUXILIARY_TIMESTAMP_NANOSECONDS 0x730 210 #define AUXILIARY_TIMESTAMP_SECONDS 0x734 211 #define PPS0_INTERVAL 0x760 212 #define PPS0_WIDTH 0x764 213 214 /* DMA */ 215 #define BUS_MODE 0x1000 216 #define BUS_MODE_MIXEDBURST (1 << 26) 217 #define BUS_MODE_AAL (1 << 25) 218 #define BUS_MODE_EIGHTXPBL (1 << 24) /* Multiplies PBL by 8 */ 219 #define BUS_MODE_USP (1 << 23) 220 #define BUS_MODE_RPBL_SHIFT 17 /* Single block transfer size */ 221 #define BUS_MODE_FIXEDBURST (1 << 16) 222 #define BUS_MODE_PRIORXTX_SHIFT 14 223 #define BUS_MODE_PRIORXTX_41 3 224 #define BUS_MODE_PRIORXTX_31 2 225 #define BUS_MODE_PRIORXTX_21 1 226 #define BUS_MODE_PRIORXTX_11 0 227 #define BUS_MODE_PBL_SHIFT 8 /* Single block transfer size */ 228 #define BUS_MODE_SWR (1 << 0) /* Reset */ 229 #define TRANSMIT_POLL_DEMAND 0x1004 230 #define RECEIVE_POLL_DEMAND 0x1008 231 #define RX_DESCR_LIST_ADDR 0x100C 232 #define TX_DESCR_LIST_ADDR 0x1010 233 #define DMA_STATUS 0x1014 234 #define DMA_STATUS_NIS (1 << 16) 235 #define DMA_STATUS_AIS (1 << 15) 236 #define DMA_STATUS_FBI (1 << 13) 237 #define DMA_STATUS_RI (1 << 6) 238 #define DMA_STATUS_TI (1 << 0) 239 #define DMA_STATUS_INTR_MASK 0x1ffff 240 #define OPERATION_MODE 0x1018 241 #define MODE_RSF (1 << 25) /* RX Full Frame */ 242 #define MODE_TSF (1 << 21) /* TX Full Frame */ 243 #define MODE_FTF (1 << 20) /* Flush TX FIFO */ 244 #define MODE_ST (1 << 13) /* Start DMA TX */ 245 #define MODE_FUF (1 << 6) /* TX frames < 64bytes */ 246 #define MODE_RTC_LEV32 0x1 247 #define MODE_RTC_SHIFT 3 248 #define MODE_OSF (1 << 2) /* Process Second frame */ 249 #define MODE_SR (1 << 1) /* Start DMA RX */ 250 #define INTERRUPT_ENABLE 0x101C 251 #define INT_EN_NIE (1 << 16) /* Normal/Summary */ 252 #define INT_EN_AIE (1 << 15) /* Abnormal/Summary */ 253 #define INT_EN_ERE (1 << 14) /* Early receive */ 254 #define INT_EN_FBE (1 << 13) /* Fatal bus error */ 255 #define INT_EN_ETE (1 << 10) /* Early transmit */ 256 #define INT_EN_RWE (1 << 9) /* Receive watchdog */ 257 #define INT_EN_RSE (1 << 8) /* Receive stopped */ 258 #define INT_EN_RUE (1 << 7) /* Recv buf unavailable */ 259 #define INT_EN_RIE (1 << 6) /* Receive interrupt */ 260 #define INT_EN_UNE (1 << 5) /* Tx underflow */ 261 #define INT_EN_OVE (1 << 4) /* Receive overflow */ 262 #define INT_EN_TJE (1 << 3) /* Transmit jabber */ 263 #define INT_EN_TUE (1 << 2) /* Tx. buf unavailable */ 264 #define INT_EN_TSE (1 << 1) /* Transmit stopped */ 265 #define INT_EN_TIE (1 << 0) /* Transmit interrupt */ 266 #define INT_EN_DEFAULT (INT_EN_TIE|INT_EN_RIE| \ 267 INT_EN_NIE|INT_EN_AIE| \ 268 INT_EN_FBE|INT_EN_UNE) 269 270 #define MISSED_FRAMEBUF_OVERFLOW_CNTR 0x1020 271 #define RECEIVE_INT_WATCHDOG_TMR 0x1024 272 #define AXI_BUS_MODE 0x1028 273 #define AHB_OR_AXI_STATUS 0x102C 274 #define CURRENT_HOST_TRANSMIT_DESCR 0x1048 275 #define CURRENT_HOST_RECEIVE_DESCR 0x104C 276 #define CURRENT_HOST_TRANSMIT_BUF_ADDR 0x1050 277 #define CURRENT_HOST_RECEIVE_BUF_ADDR 0x1054 278 279 #define HW_FEATURE 0x1058 280 #define HW_FEATURE_EXT_DESCRIPTOR (1 << 24) 281 282 #define DWC_GMAC_NORMAL_DESC 0x1 283 #define DWC_GMAC_EXT_DESC 0x2 284 285 #define GMAC_MII_CLK_60_100M_DIV42 0x0 286 #define GMAC_MII_CLK_100_150M_DIV62 0x1 287 #define GMAC_MII_CLK_25_35M_DIV16 0x2 288 #define GMAC_MII_CLK_35_60M_DIV26 0x3 289 #define GMAC_MII_CLK_150_250M_DIV102 0x4 290 #define GMAC_MII_CLK_250_300M_DIV124 0x5 291 #define GMAC_MII_CLK_DIV4 0x8 292 #define GMAC_MII_CLK_DIV6 0x9 293 #define GMAC_MII_CLK_DIV8 0xa 294 #define GMAC_MII_CLK_DIV10 0xb 295 #define GMAC_MII_CLK_DIV12 0xc 296 #define GMAC_MII_CLK_DIV14 0xd 297 #define GMAC_MII_CLK_DIV16 0xe 298 #define GMAC_MII_CLK_DIV18 0xf 299 300 #endif /* __DWC1000_REG_H__ */ 301