1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * 4 * This software was developed by SRI International and the University of 5 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 6 * ("CTSRD"), as part of the DARPA CRASH research programme. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef __DWC1000_DMA_H__ 31 #define __DWC1000_DMA_H__ 32 33 /* TX descriptors - TDESC0 is almost unified */ 34 #define TDESC0_OWN (1U << 31) 35 #define TDESC0_IHE (1U << 16) /* IP Header Error */ 36 #define TDESC0_ES (1U << 15) /* Error Summary */ 37 #define TDESC0_JT (1U << 14) /* Jabber Timeout */ 38 #define TDESC0_FF (1U << 13) /* Frame Flushed */ 39 #define TDESC0_PCE (1U << 12) /* Payload Checksum Error */ 40 #define TDESC0_LOC (1U << 11) /* Loss of Carrier */ 41 #define TDESC0_NC (1U << 10) /* No Carrier */ 42 #define TDESC0_LC (1U << 9) /* Late Collision */ 43 #define TDESC0_EC (1U << 8) /* Excessive Collision */ 44 #define TDESC0_VF (1U << 7) /* VLAN Frame */ 45 #define TDESC0_CC_MASK 0xf 46 #define TDESC0_CC_SHIFT 3 /* Collision Count */ 47 #define TDESC0_ED (1U << 2) /* Excessive Deferral */ 48 #define TDESC0_UF (1U << 1) /* Underflow Error */ 49 #define TDESC0_DB (1U << 0) /* Deferred Bit */ 50 /* TX descriptors - TDESC0 extended format only */ 51 #define ETDESC0_IC (1U << 30) /* Interrupt on Completion */ 52 #define ETDESC0_LS (1U << 29) /* Last Segment */ 53 #define ETDESC0_FS (1U << 28) /* First Segment */ 54 #define ETDESC0_DC (1U << 27) /* Disable CRC */ 55 #define ETDESC0_DP (1U << 26) /* Disable Padding */ 56 #define ETDESC0_CIC_NONE (0U << 22) /* Checksum Insertion Control */ 57 #define ETDESC0_CIC_HDR (1U << 22) 58 #define ETDESC0_CIC_SEG (2U << 22) 59 #define ETDESC0_CIC_FULL (3U << 22) 60 #define ETDESC0_TER (1U << 21) /* Transmit End of Ring */ 61 #define ETDESC0_TCH (1U << 20) /* Second Address Chained */ 62 63 /* TX descriptors - TDESC1 normal format */ 64 #define NTDESC1_IC (1U << 31) /* Interrupt on Completion */ 65 #define NTDESC1_LS (1U << 30) /* Last Segment */ 66 #define NTDESC1_FS (1U << 29) /* First Segment */ 67 #define NTDESC1_CIC_NONE (0U << 27) /* Checksum Insertion Control */ 68 #define NTDESC1_CIC_HDR (1U << 27) 69 #define NTDESC1_CIC_SEG (2U << 27) 70 #define NTDESC1_CIC_FULL (3U << 27) 71 #define NTDESC1_DC (1U << 26) /* Disable CRC */ 72 #define NTDESC1_TER (1U << 25) /* Transmit End of Ring */ 73 #define NTDESC1_TCH (1U << 24) /* Second Address Chained */ 74 /* TX descriptors - TDESC1 extended format */ 75 #define ETDESC1_DP (1U << 23) /* Disable Padding */ 76 #define ETDESC1_TBS2_MASK 0x7ff 77 #define ETDESC1_TBS2_SHIFT 11 /* Receive Buffer 2 Size */ 78 #define ETDESC1_TBS1_MASK 0x7ff 79 #define ETDESC1_TBS1_SHIFT 0 /* Receive Buffer 1 Size */ 80 81 /* RX descriptor - RDESC0 is unified */ 82 #define RDESC0_OWN (1U << 31) 83 #define RDESC0_AFM (1U << 30) /* Dest. Address Filter Fail */ 84 #define RDESC0_FL_MASK 0x3fff 85 #define RDESC0_FL_SHIFT 16 /* Frame Length */ 86 #define RDESC0_ES (1U << 15) /* Error Summary */ 87 #define RDESC0_DE (1U << 14) /* Descriptor Error */ 88 #define RDESC0_SAF (1U << 13) /* Source Address Filter Fail */ 89 #define RDESC0_LE (1U << 12) /* Length Error */ 90 #define RDESC0_OE (1U << 11) /* Overflow Error */ 91 #define RDESC0_VLAN (1U << 10) /* VLAN Tag */ 92 #define RDESC0_FS (1U << 9) /* First Descriptor */ 93 #define RDESC0_LS (1U << 8) /* Last Descriptor */ 94 #define RDESC0_ICE (1U << 7) /* IPC Checksum Error */ 95 #define RDESC0_LC (1U << 6) /* Late Collision */ 96 #define RDESC0_FT (1U << 5) /* Frame Type */ 97 #define RDESC0_RWT (1U << 4) /* Receive Watchdog Timeout */ 98 #define RDESC0_RE (1U << 3) /* Receive Error */ 99 #define RDESC0_DBE (1U << 2) /* Dribble Bit Error */ 100 #define RDESC0_CE (1U << 1) /* CRC Error */ 101 #define RDESC0_PCE (1U << 0) /* Payload Checksum Error */ 102 #define RDESC0_RXMA (1U << 0) /* Rx MAC Address */ 103 104 /* RX descriptors - RDESC1 normal format */ 105 #define NRDESC1_DIC (1U << 31) /* Disable Intr on Completion */ 106 #define NRDESC1_RER (1U << 25) /* Receive End of Ring */ 107 #define NRDESC1_RCH (1U << 24) /* Second Address Chained */ 108 #define NRDESC1_RBS2_MASK 0x7ff 109 #define NRDESC1_RBS2_SHIFT 11 /* Receive Buffer 2 Size */ 110 #define NRDESC1_RBS1_MASK 0x7ff 111 #define NRDESC1_RBS1_SHIFT 0 /* Receive Buffer 1 Size */ 112 113 /* RX descriptors - RDESC1 enhanced format */ 114 #define ERDESC1_DIC (1U << 31) /* Disable Intr on Completion */ 115 #define ERDESC1_RBS2_MASK 0x7ffff 116 #define ERDESC1_RBS2_SHIFT 16 /* Receive Buffer 2 Size */ 117 #define ERDESC1_RER (1U << 15) /* Receive End of Ring */ 118 #define ERDESC1_RCH (1U << 14) /* Second Address Chained */ 119 #define ERDESC1_RBS1_MASK 0x7ffff 120 #define ERDESC1_RBS1_SHIFT 0 /* Receive Buffer 1 Size */ 121 122 /* 123 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 124 * layout, but the bits in the fields have different meanings. 125 */ 126 struct dwc_hwdesc 127 { 128 uint32_t desc0; 129 uint32_t desc1; 130 uint32_t addr1; /* ptr to first buffer data */ 131 uint32_t addr2; /* ptr to next descriptor / second buffer data*/ 132 }; 133 134 /* 135 * The hardware imposes alignment restrictions on various objects involved in 136 * DMA transfers. These values are expressed in bytes (not bits). 137 */ 138 #define DWC_DESC_RING_ALIGN 2048 139 140 int dma1000_init(struct dwc_softc *sc); 141 void dma1000_free(struct dwc_softc *sc); 142 void dma1000_start(struct dwc_softc *sc); 143 void dma1000_stop(struct dwc_softc *sc); 144 int dma1000_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp); 145 void dma1000_txfinish_locked(struct dwc_softc *sc); 146 void dma1000_rxfinish_locked(struct dwc_softc *sc); 147 void dma1000_txstart(struct dwc_softc *sc); 148 149 #endif /* __DWC1000_DMA_H__ */ 150