1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * 4 * This software was developed by SRI International and the University of 5 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 6 * ("CTSRD"), as part of the DARPA CRASH research programme. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/malloc.h> 37 #include <sys/mbuf.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/socket.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 #include <net/if_types.h> 49 #include <net/if_var.h> 50 51 #include <machine/bus.h> 52 53 #include <dev/extres/clk/clk.h> 54 #include <dev/extres/hwreset/hwreset.h> 55 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 59 #include <dev/dwc/if_dwcvar.h> 60 #include <dev/dwc/dwc1000_reg.h> 61 #include <dev/dwc/dwc1000_dma.h> 62 63 #define WATCHDOG_TIMEOUT_SECS 5 64 #define DMA_RESET_TIMEOUT 100 65 66 /* TX descriptors - TDESC0 is almost unified */ 67 #define TDESC0_OWN (1U << 31) 68 #define TDESC0_IHE (1U << 16) /* IP Header Error */ 69 #define TDESC0_ES (1U << 15) /* Error Summary */ 70 #define TDESC0_JT (1U << 14) /* Jabber Timeout */ 71 #define TDESC0_FF (1U << 13) /* Frame Flushed */ 72 #define TDESC0_PCE (1U << 12) /* Payload Checksum Error */ 73 #define TDESC0_LOC (1U << 11) /* Loss of Carrier */ 74 #define TDESC0_NC (1U << 10) /* No Carrier */ 75 #define TDESC0_LC (1U << 9) /* Late Collision */ 76 #define TDESC0_EC (1U << 8) /* Excessive Collision */ 77 #define TDESC0_VF (1U << 7) /* VLAN Frame */ 78 #define TDESC0_CC_MASK 0xf 79 #define TDESC0_CC_SHIFT 3 /* Collision Count */ 80 #define TDESC0_ED (1U << 2) /* Excessive Deferral */ 81 #define TDESC0_UF (1U << 1) /* Underflow Error */ 82 #define TDESC0_DB (1U << 0) /* Deferred Bit */ 83 /* TX descriptors - TDESC0 extended format only */ 84 #define ETDESC0_IC (1U << 30) /* Interrupt on Completion */ 85 #define ETDESC0_LS (1U << 29) /* Last Segment */ 86 #define ETDESC0_FS (1U << 28) /* First Segment */ 87 #define ETDESC0_DC (1U << 27) /* Disable CRC */ 88 #define ETDESC0_DP (1U << 26) /* Disable Padding */ 89 #define ETDESC0_CIC_NONE (0U << 22) /* Checksum Insertion Control */ 90 #define ETDESC0_CIC_HDR (1U << 22) 91 #define ETDESC0_CIC_SEG (2U << 22) 92 #define ETDESC0_CIC_FULL (3U << 22) 93 #define ETDESC0_TER (1U << 21) /* Transmit End of Ring */ 94 #define ETDESC0_TCH (1U << 20) /* Second Address Chained */ 95 96 /* TX descriptors - TDESC1 normal format */ 97 #define NTDESC1_IC (1U << 31) /* Interrupt on Completion */ 98 #define NTDESC1_LS (1U << 30) /* Last Segment */ 99 #define NTDESC1_FS (1U << 29) /* First Segment */ 100 #define NTDESC1_CIC_NONE (0U << 27) /* Checksum Insertion Control */ 101 #define NTDESC1_CIC_HDR (1U << 27) 102 #define NTDESC1_CIC_SEG (2U << 27) 103 #define NTDESC1_CIC_FULL (3U << 27) 104 #define NTDESC1_DC (1U << 26) /* Disable CRC */ 105 #define NTDESC1_TER (1U << 25) /* Transmit End of Ring */ 106 #define NTDESC1_TCH (1U << 24) /* Second Address Chained */ 107 /* TX descriptors - TDESC1 extended format */ 108 #define ETDESC1_DP (1U << 23) /* Disable Padding */ 109 #define ETDESC1_TBS2_MASK 0x7ff 110 #define ETDESC1_TBS2_SHIFT 11 /* Receive Buffer 2 Size */ 111 #define ETDESC1_TBS1_MASK 0x7ff 112 #define ETDESC1_TBS1_SHIFT 0 /* Receive Buffer 1 Size */ 113 114 /* RX descriptor - RDESC0 is unified */ 115 #define RDESC0_OWN (1U << 31) 116 #define RDESC0_AFM (1U << 30) /* Dest. Address Filter Fail */ 117 #define RDESC0_FL_MASK 0x3fff 118 #define RDESC0_FL_SHIFT 16 /* Frame Length */ 119 #define RDESC0_ES (1U << 15) /* Error Summary */ 120 #define RDESC0_DE (1U << 14) /* Descriptor Error */ 121 #define RDESC0_SAF (1U << 13) /* Source Address Filter Fail */ 122 #define RDESC0_LE (1U << 12) /* Length Error */ 123 #define RDESC0_OE (1U << 11) /* Overflow Error */ 124 #define RDESC0_VLAN (1U << 10) /* VLAN Tag */ 125 #define RDESC0_FS (1U << 9) /* First Descriptor */ 126 #define RDESC0_LS (1U << 8) /* Last Descriptor */ 127 #define RDESC0_ICE (1U << 7) /* IPC Checksum Error */ 128 #define RDESC0_LC (1U << 6) /* Late Collision */ 129 #define RDESC0_FT (1U << 5) /* Frame Type */ 130 #define RDESC0_RWT (1U << 4) /* Receive Watchdog Timeout */ 131 #define RDESC0_RE (1U << 3) /* Receive Error */ 132 #define RDESC0_DBE (1U << 2) /* Dribble Bit Error */ 133 #define RDESC0_CE (1U << 1) /* CRC Error */ 134 #define RDESC0_PCE (1U << 0) /* Payload Checksum Error */ 135 #define RDESC0_RXMA (1U << 0) /* Rx MAC Address */ 136 137 /* RX descriptors - RDESC1 normal format */ 138 #define NRDESC1_DIC (1U << 31) /* Disable Intr on Completion */ 139 #define NRDESC1_RER (1U << 25) /* Receive End of Ring */ 140 #define NRDESC1_RCH (1U << 24) /* Second Address Chained */ 141 #define NRDESC1_RBS2_MASK 0x7ff 142 #define NRDESC1_RBS2_SHIFT 11 /* Receive Buffer 2 Size */ 143 #define NRDESC1_RBS1_MASK 0x7ff 144 #define NRDESC1_RBS1_SHIFT 0 /* Receive Buffer 1 Size */ 145 146 /* RX descriptors - RDESC1 enhanced format */ 147 #define ERDESC1_DIC (1U << 31) /* Disable Intr on Completion */ 148 #define ERDESC1_RBS2_MASK 0x7ffff 149 #define ERDESC1_RBS2_SHIFT 16 /* Receive Buffer 2 Size */ 150 #define ERDESC1_RER (1U << 15) /* Receive End of Ring */ 151 #define ERDESC1_RCH (1U << 14) /* Second Address Chained */ 152 #define ERDESC1_RBS1_MASK 0x7ffff 153 #define ERDESC1_RBS1_SHIFT 0 /* Receive Buffer 1 Size */ 154 155 /* 156 * The hardware imposes alignment restrictions on various objects involved in 157 * DMA transfers. These values are expressed in bytes (not bits). 158 */ 159 #define DWC_DESC_RING_ALIGN 2048 160 161 static inline uint32_t 162 next_txidx(struct dwc_softc *sc, uint32_t curidx) 163 { 164 165 return ((curidx + 1) % TX_DESC_COUNT); 166 } 167 168 static inline uint32_t 169 next_rxidx(struct dwc_softc *sc, uint32_t curidx) 170 { 171 172 return ((curidx + 1) % RX_DESC_COUNT); 173 } 174 175 static void 176 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 177 { 178 179 if (error != 0) 180 return; 181 *(bus_addr_t *)arg = segs[0].ds_addr; 182 } 183 184 inline static void 185 txdesc_clear(struct dwc_softc *sc, int idx) 186 { 187 188 sc->tx_desccount--; 189 sc->txdesc_ring[idx].addr1 = (uint32_t)(0); 190 sc->txdesc_ring[idx].desc0 = 0; 191 sc->txdesc_ring[idx].desc1 = 0; 192 } 193 194 inline static void 195 txdesc_setup(struct dwc_softc *sc, int idx, bus_addr_t paddr, 196 uint32_t len, uint32_t flags, bool first, bool last) 197 { 198 uint32_t desc0, desc1; 199 200 if (!sc->dma_ext_desc) { 201 desc0 = 0; 202 desc1 = NTDESC1_TCH | len | flags; 203 if (first) 204 desc1 |= NTDESC1_FS; 205 if (last) 206 desc1 |= NTDESC1_LS | NTDESC1_IC; 207 } else { 208 desc0 = ETDESC0_TCH | flags; 209 if (first) 210 desc0 |= ETDESC0_FS; 211 if (last) 212 desc0 |= ETDESC0_LS | ETDESC0_IC; 213 desc1 = len; 214 } 215 ++sc->tx_desccount; 216 sc->txdesc_ring[idx].addr1 = (uint32_t)(paddr); 217 sc->txdesc_ring[idx].desc0 = desc0; 218 sc->txdesc_ring[idx].desc1 = desc1; 219 wmb(); 220 sc->txdesc_ring[idx].desc0 |= TDESC0_OWN; 221 } 222 223 inline static uint32_t 224 rxdesc_setup(struct dwc_softc *sc, int idx, bus_addr_t paddr) 225 { 226 uint32_t nidx; 227 228 sc->rxdesc_ring[idx].addr1 = (uint32_t)paddr; 229 nidx = next_rxidx(sc, idx); 230 sc->rxdesc_ring[idx].addr2 = sc->rxdesc_ring_paddr + 231 (nidx * sizeof(struct dwc_hwdesc)); 232 if (!sc->dma_ext_desc) 233 sc->rxdesc_ring[idx].desc1 = NRDESC1_RCH | 234 MIN(MCLBYTES, NRDESC1_RBS1_MASK); 235 else 236 sc->rxdesc_ring[idx].desc1 = ERDESC1_RCH | 237 MIN(MCLBYTES, ERDESC1_RBS1_MASK); 238 239 wmb(); 240 sc->rxdesc_ring[idx].desc0 = RDESC0_OWN; 241 return (nidx); 242 } 243 244 int 245 dma1000_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) 246 { 247 struct bus_dma_segment segs[TX_MAP_MAX_SEGS]; 248 int error, nsegs; 249 struct mbuf * m; 250 uint32_t flags = 0; 251 int i; 252 int last; 253 254 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 255 *mp, segs, &nsegs, 0); 256 if (error == EFBIG) { 257 /* 258 * The map may be partially mapped from the first call. 259 * Make sure to reset it. 260 */ 261 bus_dmamap_unload(sc->txbuf_tag, sc->txbuf_map[idx].map); 262 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 263 return (ENOMEM); 264 *mp = m; 265 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 266 *mp, segs, &nsegs, 0); 267 } 268 if (error != 0) 269 return (ENOMEM); 270 271 if (sc->tx_desccount + nsegs > TX_DESC_COUNT) { 272 bus_dmamap_unload(sc->txbuf_tag, sc->txbuf_map[idx].map); 273 return (ENOMEM); 274 } 275 276 m = *mp; 277 278 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) { 279 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) { 280 if (!sc->dma_ext_desc) 281 flags = NTDESC1_CIC_FULL; 282 else 283 flags = ETDESC0_CIC_FULL; 284 } else { 285 if (!sc->dma_ext_desc) 286 flags = NTDESC1_CIC_HDR; 287 else 288 flags = ETDESC0_CIC_HDR; 289 } 290 } 291 292 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 293 BUS_DMASYNC_PREWRITE); 294 295 sc->txbuf_map[idx].mbuf = m; 296 297 for (i = 0; i < nsegs; i++) { 298 txdesc_setup(sc, sc->tx_desc_head, 299 segs[i].ds_addr, segs[i].ds_len, 300 (i == 0) ? flags : 0, /* only first desc needs flags */ 301 (i == 0), 302 (i == nsegs - 1)); 303 last = sc->tx_desc_head; 304 sc->tx_desc_head = next_txidx(sc, sc->tx_desc_head); 305 } 306 307 sc->txbuf_map[idx].last_desc_idx = last; 308 309 return (0); 310 } 311 312 static int 313 dma1000_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) 314 { 315 struct bus_dma_segment seg; 316 int error, nsegs; 317 318 m_adj(m, ETHER_ALIGN); 319 320 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 321 m, &seg, &nsegs, 0); 322 if (error != 0) 323 return (error); 324 325 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 326 327 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 328 BUS_DMASYNC_PREREAD); 329 330 sc->rxbuf_map[idx].mbuf = m; 331 rxdesc_setup(sc, idx, seg.ds_addr); 332 333 return (0); 334 } 335 336 static struct mbuf * 337 dwc_alloc_mbufcl(struct dwc_softc *sc) 338 { 339 struct mbuf *m; 340 341 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 342 if (m != NULL) 343 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 344 345 return (m); 346 } 347 348 static struct mbuf * 349 dwc_rxfinish_one(struct dwc_softc *sc, struct dwc_hwdesc *desc, 350 struct dwc_bufmap *map) 351 { 352 if_t ifp; 353 struct mbuf *m, *m0; 354 int len; 355 uint32_t rdesc0; 356 357 m = map->mbuf; 358 ifp = sc->ifp; 359 rdesc0 = desc ->desc0; 360 361 if ((rdesc0 & (RDESC0_FS | RDESC0_LS)) != 362 (RDESC0_FS | RDESC0_LS)) { 363 /* 364 * Something very wrong happens. The whole packet should be 365 * recevied in one descriptr. Report problem. 366 */ 367 device_printf(sc->dev, 368 "%s: RX descriptor without FIRST and LAST bit set: 0x%08X", 369 __func__, rdesc0); 370 return (NULL); 371 } 372 373 len = (rdesc0 >> RDESC0_FL_SHIFT) & RDESC0_FL_MASK; 374 if (len < 64) { 375 /* 376 * Lenght is invalid, recycle old mbuf 377 * Probably impossible case 378 */ 379 return (NULL); 380 } 381 382 /* Allocate new buffer */ 383 m0 = dwc_alloc_mbufcl(sc); 384 if (m0 == NULL) { 385 /* no new mbuf available, recycle old */ 386 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 387 return (NULL); 388 } 389 /* Do dmasync for newly received packet */ 390 bus_dmamap_sync(sc->rxbuf_tag, map->map, BUS_DMASYNC_POSTREAD); 391 bus_dmamap_unload(sc->rxbuf_tag, map->map); 392 393 /* Received packet is valid, process it */ 394 m->m_pkthdr.rcvif = ifp; 395 m->m_pkthdr.len = len; 396 m->m_len = len; 397 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 398 399 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 400 (rdesc0 & RDESC0_FT) != 0) { 401 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 402 if ((rdesc0 & RDESC0_ICE) == 0) 403 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 404 if ((rdesc0 & RDESC0_PCE) == 0) { 405 m->m_pkthdr.csum_flags |= 406 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 407 m->m_pkthdr.csum_data = 0xffff; 408 } 409 } 410 411 /* Remove trailing FCS */ 412 m_adj(m, -ETHER_CRC_LEN); 413 414 DWC_UNLOCK(sc); 415 if_input(ifp, m); 416 DWC_LOCK(sc); 417 return (m0); 418 } 419 420 void 421 dma1000_txfinish_locked(struct dwc_softc *sc) 422 { 423 struct dwc_bufmap *bmap; 424 struct dwc_hwdesc *desc; 425 if_t ifp; 426 int idx, last_idx; 427 bool map_finished; 428 429 DWC_ASSERT_LOCKED(sc); 430 431 ifp = sc->ifp; 432 /* check if all descriptors of the map are done */ 433 while (sc->tx_map_tail != sc->tx_map_head) { 434 map_finished = true; 435 bmap = &sc->txbuf_map[sc->tx_map_tail]; 436 idx = sc->tx_desc_tail; 437 last_idx = next_txidx(sc, bmap->last_desc_idx); 438 while (idx != last_idx) { 439 desc = &sc->txdesc_ring[idx]; 440 if ((desc->desc0 & TDESC0_OWN) != 0) { 441 map_finished = false; 442 break; 443 } 444 idx = next_txidx(sc, idx); 445 } 446 447 if (!map_finished) 448 break; 449 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 450 BUS_DMASYNC_POSTWRITE); 451 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 452 m_freem(bmap->mbuf); 453 bmap->mbuf = NULL; 454 sc->tx_mapcount--; 455 while (sc->tx_desc_tail != last_idx) { 456 txdesc_clear(sc, sc->tx_desc_tail); 457 sc->tx_desc_tail = next_txidx(sc, sc->tx_desc_tail); 458 } 459 sc->tx_map_tail = next_txidx(sc, sc->tx_map_tail); 460 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 461 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 462 } 463 464 /* If there are no buffers outstanding, muzzle the watchdog. */ 465 if (sc->tx_desc_tail == sc->tx_desc_head) { 466 sc->tx_watchdog_count = 0; 467 } 468 } 469 470 void 471 dma1000_txstart(struct dwc_softc *sc) 472 { 473 int enqueued; 474 struct mbuf *m; 475 476 enqueued = 0; 477 478 for (;;) { 479 if (sc->tx_desccount > (TX_DESC_COUNT - TX_MAP_MAX_SEGS + 1)) { 480 if_setdrvflagbits(sc->ifp, IFF_DRV_OACTIVE, 0); 481 break; 482 } 483 484 if (sc->tx_mapcount == (TX_MAP_COUNT - 1)) { 485 if_setdrvflagbits(sc->ifp, IFF_DRV_OACTIVE, 0); 486 break; 487 } 488 489 m = if_dequeue(sc->ifp); 490 if (m == NULL) 491 break; 492 if (dma1000_setup_txbuf(sc, sc->tx_map_head, &m) != 0) { 493 if_sendq_prepend(sc->ifp, m); 494 if_setdrvflagbits(sc->ifp, IFF_DRV_OACTIVE, 0); 495 break; 496 } 497 bpf_mtap_if(sc->ifp, m); 498 sc->tx_map_head = next_txidx(sc, sc->tx_map_head); 499 sc->tx_mapcount++; 500 ++enqueued; 501 } 502 503 if (enqueued != 0) { 504 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 505 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 506 } 507 } 508 509 void 510 dma1000_rxfinish_locked(struct dwc_softc *sc) 511 { 512 struct mbuf *m; 513 int error, idx; 514 struct dwc_hwdesc *desc; 515 516 DWC_ASSERT_LOCKED(sc); 517 for (;;) { 518 idx = sc->rx_idx; 519 desc = sc->rxdesc_ring + idx; 520 if ((desc->desc0 & RDESC0_OWN) != 0) 521 break; 522 523 m = dwc_rxfinish_one(sc, desc, sc->rxbuf_map + idx); 524 if (m == NULL) { 525 wmb(); 526 desc->desc0 = RDESC0_OWN; 527 } else { 528 /* We cannot create hole in RX ring */ 529 error = dma1000_setup_rxbuf(sc, idx, m); 530 if (error != 0) 531 panic("dma1000_setup_rxbuf failed: error %d\n", 532 error); 533 534 } 535 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 536 } 537 } 538 539 /* 540 * Start the DMA controller 541 */ 542 void 543 dma1000_start(struct dwc_softc *sc) 544 { 545 uint32_t reg; 546 547 DWC_ASSERT_LOCKED(sc); 548 549 /* Initializa DMA and enable transmitters */ 550 reg = READ4(sc, OPERATION_MODE); 551 reg |= (MODE_TSF | MODE_OSF | MODE_FUF); 552 reg &= ~(MODE_RSF); 553 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); 554 WRITE4(sc, OPERATION_MODE, reg); 555 556 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 557 558 /* Start DMA */ 559 reg = READ4(sc, OPERATION_MODE); 560 reg |= (MODE_ST | MODE_SR); 561 WRITE4(sc, OPERATION_MODE, reg); 562 } 563 564 /* 565 * Stop the DMA controller 566 */ 567 void 568 dma1000_stop(struct dwc_softc *sc) 569 { 570 uint32_t reg; 571 572 DWC_ASSERT_LOCKED(sc); 573 574 /* Stop DMA TX */ 575 reg = READ4(sc, OPERATION_MODE); 576 reg &= ~(MODE_ST); 577 WRITE4(sc, OPERATION_MODE, reg); 578 579 /* Flush TX */ 580 reg = READ4(sc, OPERATION_MODE); 581 reg |= (MODE_FTF); 582 WRITE4(sc, OPERATION_MODE, reg); 583 584 /* Stop DMA RX */ 585 reg = READ4(sc, OPERATION_MODE); 586 reg &= ~(MODE_SR); 587 WRITE4(sc, OPERATION_MODE, reg); 588 } 589 590 int 591 dma1000_reset(struct dwc_softc *sc) 592 { 593 uint32_t reg; 594 int i; 595 596 reg = READ4(sc, BUS_MODE); 597 reg |= (BUS_MODE_SWR); 598 WRITE4(sc, BUS_MODE, reg); 599 600 for (i = 0; i < DMA_RESET_TIMEOUT; i++) { 601 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) 602 break; 603 DELAY(10); 604 } 605 if (i >= DMA_RESET_TIMEOUT) { 606 return (ENXIO); 607 } 608 609 return (0); 610 } 611 612 /* 613 * Create the bus_dma resources 614 */ 615 int 616 dma1000_init(struct dwc_softc *sc) 617 { 618 struct mbuf *m; 619 uint32_t reg; 620 int error; 621 int nidx; 622 int idx; 623 624 reg = BUS_MODE_USP; 625 if (!sc->nopblx8) 626 reg |= BUS_MODE_EIGHTXPBL; 627 reg |= (sc->txpbl << BUS_MODE_PBL_SHIFT); 628 reg |= (sc->rxpbl << BUS_MODE_RPBL_SHIFT); 629 if (sc->fixed_burst) 630 reg |= BUS_MODE_FIXEDBURST; 631 if (sc->mixed_burst) 632 reg |= BUS_MODE_MIXEDBURST; 633 if (sc->aal) 634 reg |= BUS_MODE_AAL; 635 636 WRITE4(sc, BUS_MODE, reg); 637 638 reg = READ4(sc, HW_FEATURE); 639 if (reg & HW_FEATURE_EXT_DESCRIPTOR) 640 sc->dma_ext_desc = true; 641 642 /* 643 * DMA must be stop while changing descriptor list addresses. 644 */ 645 reg = READ4(sc, OPERATION_MODE); 646 reg &= ~(MODE_ST | MODE_SR); 647 WRITE4(sc, OPERATION_MODE, reg); 648 649 /* 650 * Set up TX descriptor ring, descriptors, and dma maps. 651 */ 652 error = bus_dma_tag_create( 653 bus_get_dma_tag(sc->dev), /* Parent tag. */ 654 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 655 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 656 BUS_SPACE_MAXADDR, /* highaddr */ 657 NULL, NULL, /* filter, filterarg */ 658 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 659 TX_DESC_SIZE, /* maxsegsize */ 660 0, /* flags */ 661 NULL, NULL, /* lockfunc, lockarg */ 662 &sc->txdesc_tag); 663 if (error != 0) { 664 device_printf(sc->dev, 665 "could not create TX ring DMA tag.\n"); 666 goto out; 667 } 668 669 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 670 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 671 &sc->txdesc_map); 672 if (error != 0) { 673 device_printf(sc->dev, 674 "could not allocate TX descriptor ring.\n"); 675 goto out; 676 } 677 678 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, 679 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, 680 &sc->txdesc_ring_paddr, 0); 681 if (error != 0) { 682 device_printf(sc->dev, 683 "could not load TX descriptor ring map.\n"); 684 goto out; 685 } 686 687 for (idx = 0; idx < TX_DESC_COUNT; idx++) { 688 nidx = next_txidx(sc, idx); 689 sc->txdesc_ring[idx].addr2 = sc->txdesc_ring_paddr + 690 (nidx * sizeof(struct dwc_hwdesc)); 691 } 692 693 error = bus_dma_tag_create( 694 bus_get_dma_tag(sc->dev), /* Parent tag. */ 695 1, 0, /* alignment, boundary */ 696 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 697 BUS_SPACE_MAXADDR, /* highaddr */ 698 NULL, NULL, /* filter, filterarg */ 699 MCLBYTES*TX_MAP_MAX_SEGS, /* maxsize */ 700 TX_MAP_MAX_SEGS, /* nsegments */ 701 MCLBYTES, /* maxsegsize */ 702 0, /* flags */ 703 NULL, NULL, /* lockfunc, lockarg */ 704 &sc->txbuf_tag); 705 if (error != 0) { 706 device_printf(sc->dev, 707 "could not create TX ring DMA tag.\n"); 708 goto out; 709 } 710 711 for (idx = 0; idx < TX_MAP_COUNT; idx++) { 712 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, 713 &sc->txbuf_map[idx].map); 714 if (error != 0) { 715 device_printf(sc->dev, 716 "could not create TX buffer DMA map.\n"); 717 goto out; 718 } 719 } 720 721 for (idx = 0; idx < TX_DESC_COUNT; idx++) 722 txdesc_clear(sc, idx); 723 724 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); 725 726 /* 727 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 728 */ 729 error = bus_dma_tag_create( 730 bus_get_dma_tag(sc->dev), /* Parent tag. */ 731 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 732 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 733 BUS_SPACE_MAXADDR, /* highaddr */ 734 NULL, NULL, /* filter, filterarg */ 735 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 736 RX_DESC_SIZE, /* maxsegsize */ 737 0, /* flags */ 738 NULL, NULL, /* lockfunc, lockarg */ 739 &sc->rxdesc_tag); 740 if (error != 0) { 741 device_printf(sc->dev, 742 "could not create RX ring DMA tag.\n"); 743 goto out; 744 } 745 746 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 747 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 748 &sc->rxdesc_map); 749 if (error != 0) { 750 device_printf(sc->dev, 751 "could not allocate RX descriptor ring.\n"); 752 goto out; 753 } 754 755 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, 756 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, 757 &sc->rxdesc_ring_paddr, 0); 758 if (error != 0) { 759 device_printf(sc->dev, 760 "could not load RX descriptor ring map.\n"); 761 goto out; 762 } 763 764 error = bus_dma_tag_create( 765 bus_get_dma_tag(sc->dev), /* Parent tag. */ 766 1, 0, /* alignment, boundary */ 767 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 768 BUS_SPACE_MAXADDR, /* highaddr */ 769 NULL, NULL, /* filter, filterarg */ 770 MCLBYTES, 1, /* maxsize, nsegments */ 771 MCLBYTES, /* maxsegsize */ 772 0, /* flags */ 773 NULL, NULL, /* lockfunc, lockarg */ 774 &sc->rxbuf_tag); 775 if (error != 0) { 776 device_printf(sc->dev, 777 "could not create RX buf DMA tag.\n"); 778 goto out; 779 } 780 781 for (idx = 0; idx < RX_DESC_COUNT; idx++) { 782 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, 783 &sc->rxbuf_map[idx].map); 784 if (error != 0) { 785 device_printf(sc->dev, 786 "could not create RX buffer DMA map.\n"); 787 goto out; 788 } 789 if ((m = dwc_alloc_mbufcl(sc)) == NULL) { 790 device_printf(sc->dev, "Could not alloc mbuf\n"); 791 error = ENOMEM; 792 goto out; 793 } 794 if ((error = dma1000_setup_rxbuf(sc, idx, m)) != 0) { 795 device_printf(sc->dev, 796 "could not create new RX buffer.\n"); 797 goto out; 798 } 799 } 800 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); 801 802 out: 803 if (error != 0) 804 return (ENXIO); 805 806 return (0); 807 } 808 809 /* 810 * Free the bus_dma resources 811 */ 812 void 813 dma1000_free(struct dwc_softc *sc) 814 { 815 bus_dmamap_t map; 816 int idx; 817 818 /* Clean up RX DMA resources and free mbufs. */ 819 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 820 if ((map = sc->rxbuf_map[idx].map) != NULL) { 821 bus_dmamap_unload(sc->rxbuf_tag, map); 822 bus_dmamap_destroy(sc->rxbuf_tag, map); 823 m_freem(sc->rxbuf_map[idx].mbuf); 824 } 825 } 826 if (sc->rxbuf_tag != NULL) 827 bus_dma_tag_destroy(sc->rxbuf_tag); 828 if (sc->rxdesc_map != NULL) { 829 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 830 bus_dmamem_free(sc->rxdesc_tag, sc->rxdesc_ring, 831 sc->rxdesc_map); 832 } 833 if (sc->rxdesc_tag != NULL) 834 bus_dma_tag_destroy(sc->rxdesc_tag); 835 836 /* Clean up TX DMA resources. */ 837 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 838 if ((map = sc->txbuf_map[idx].map) != NULL) { 839 /* TX maps are already unloaded. */ 840 bus_dmamap_destroy(sc->txbuf_tag, map); 841 } 842 } 843 if (sc->txbuf_tag != NULL) 844 bus_dma_tag_destroy(sc->txbuf_tag); 845 if (sc->txdesc_map != NULL) { 846 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 847 bus_dmamem_free(sc->txdesc_tag, sc->txdesc_ring, 848 sc->txdesc_map); 849 } 850 if (sc->txdesc_tag != NULL) 851 bus_dma_tag_destroy(sc->txdesc_tag); 852 } 853 854 /* 855 * Interrupt function 856 */ 857 858 int 859 dma1000_intr(struct dwc_softc *sc) 860 { 861 uint32_t reg; 862 int rv; 863 864 DWC_ASSERT_LOCKED(sc); 865 866 rv = 0; 867 reg = READ4(sc, DMA_STATUS); 868 if (reg & DMA_STATUS_NIS) { 869 if (reg & DMA_STATUS_RI) 870 dma1000_rxfinish_locked(sc); 871 872 if (reg & DMA_STATUS_TI) { 873 dma1000_txfinish_locked(sc); 874 dma1000_txstart(sc); 875 } 876 } 877 878 if (reg & DMA_STATUS_AIS) { 879 if (reg & DMA_STATUS_FBI) { 880 /* Fatal bus error */ 881 rv = EIO; 882 } 883 } 884 885 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); 886 return (rv); 887 } 888