xref: /freebsd/sys/dev/drm2/ttm/ttm_placement.h (revision 592ffb217505586a6c69e91549a3c14132875f16)
1*592ffb21SWarner Losh /**************************************************************************
2*592ffb21SWarner Losh  *
3*592ffb21SWarner Losh  * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA
4*592ffb21SWarner Losh  * All Rights Reserved.
5*592ffb21SWarner Losh  *
6*592ffb21SWarner Losh  * Permission is hereby granted, free of charge, to any person obtaining a
7*592ffb21SWarner Losh  * copy of this software and associated documentation files (the
8*592ffb21SWarner Losh  * "Software"), to deal in the Software without restriction, including
9*592ffb21SWarner Losh  * without limitation the rights to use, copy, modify, merge, publish,
10*592ffb21SWarner Losh  * distribute, sub license, and/or sell copies of the Software, and to
11*592ffb21SWarner Losh  * permit persons to whom the Software is furnished to do so, subject to
12*592ffb21SWarner Losh  * the following conditions:
13*592ffb21SWarner Losh  *
14*592ffb21SWarner Losh  * The above copyright notice and this permission notice (including the
15*592ffb21SWarner Losh  * next paragraph) shall be included in all copies or substantial portions
16*592ffb21SWarner Losh  * of the Software.
17*592ffb21SWarner Losh  *
18*592ffb21SWarner Losh  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19*592ffb21SWarner Losh  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20*592ffb21SWarner Losh  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21*592ffb21SWarner Losh  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22*592ffb21SWarner Losh  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23*592ffb21SWarner Losh  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24*592ffb21SWarner Losh  * USE OR OTHER DEALINGS IN THE SOFTWARE.
25*592ffb21SWarner Losh  *
26*592ffb21SWarner Losh  **************************************************************************/
27*592ffb21SWarner Losh /*
28*592ffb21SWarner Losh  * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
29*592ffb21SWarner Losh  */
30*592ffb21SWarner Losh /* $FreeBSD$ */
31*592ffb21SWarner Losh 
32*592ffb21SWarner Losh #ifndef _TTM_PLACEMENT_H_
33*592ffb21SWarner Losh #define _TTM_PLACEMENT_H_
34*592ffb21SWarner Losh /*
35*592ffb21SWarner Losh  * Memory regions for data placement.
36*592ffb21SWarner Losh  */
37*592ffb21SWarner Losh 
38*592ffb21SWarner Losh #define TTM_PL_SYSTEM           0
39*592ffb21SWarner Losh #define TTM_PL_TT               1
40*592ffb21SWarner Losh #define TTM_PL_VRAM             2
41*592ffb21SWarner Losh #define TTM_PL_PRIV0            3
42*592ffb21SWarner Losh #define TTM_PL_PRIV1            4
43*592ffb21SWarner Losh #define TTM_PL_PRIV2            5
44*592ffb21SWarner Losh #define TTM_PL_PRIV3            6
45*592ffb21SWarner Losh #define TTM_PL_PRIV4            7
46*592ffb21SWarner Losh #define TTM_PL_PRIV5            8
47*592ffb21SWarner Losh #define TTM_PL_SWAPPED          15
48*592ffb21SWarner Losh 
49*592ffb21SWarner Losh #define TTM_PL_FLAG_SYSTEM      (1 << TTM_PL_SYSTEM)
50*592ffb21SWarner Losh #define TTM_PL_FLAG_TT          (1 << TTM_PL_TT)
51*592ffb21SWarner Losh #define TTM_PL_FLAG_VRAM        (1 << TTM_PL_VRAM)
52*592ffb21SWarner Losh #define TTM_PL_FLAG_PRIV0       (1 << TTM_PL_PRIV0)
53*592ffb21SWarner Losh #define TTM_PL_FLAG_PRIV1       (1 << TTM_PL_PRIV1)
54*592ffb21SWarner Losh #define TTM_PL_FLAG_PRIV2       (1 << TTM_PL_PRIV2)
55*592ffb21SWarner Losh #define TTM_PL_FLAG_PRIV3       (1 << TTM_PL_PRIV3)
56*592ffb21SWarner Losh #define TTM_PL_FLAG_PRIV4       (1 << TTM_PL_PRIV4)
57*592ffb21SWarner Losh #define TTM_PL_FLAG_PRIV5       (1 << TTM_PL_PRIV5)
58*592ffb21SWarner Losh #define TTM_PL_FLAG_SWAPPED     (1 << TTM_PL_SWAPPED)
59*592ffb21SWarner Losh #define TTM_PL_MASK_MEM         0x0000FFFF
60*592ffb21SWarner Losh 
61*592ffb21SWarner Losh /*
62*592ffb21SWarner Losh  * Other flags that affects data placement.
63*592ffb21SWarner Losh  * TTM_PL_FLAG_CACHED indicates cache-coherent mappings
64*592ffb21SWarner Losh  * if available.
65*592ffb21SWarner Losh  * TTM_PL_FLAG_SHARED means that another application may
66*592ffb21SWarner Losh  * reference the buffer.
67*592ffb21SWarner Losh  * TTM_PL_FLAG_NO_EVICT means that the buffer may never
68*592ffb21SWarner Losh  * be evicted to make room for other buffers.
69*592ffb21SWarner Losh  */
70*592ffb21SWarner Losh 
71*592ffb21SWarner Losh #define TTM_PL_FLAG_CACHED      (1 << 16)
72*592ffb21SWarner Losh #define TTM_PL_FLAG_UNCACHED    (1 << 17)
73*592ffb21SWarner Losh #define TTM_PL_FLAG_WC          (1 << 18)
74*592ffb21SWarner Losh #define TTM_PL_FLAG_SHARED      (1 << 20)
75*592ffb21SWarner Losh #define TTM_PL_FLAG_NO_EVICT    (1 << 21)
76*592ffb21SWarner Losh 
77*592ffb21SWarner Losh #define TTM_PL_MASK_CACHING     (TTM_PL_FLAG_CACHED | \
78*592ffb21SWarner Losh 				 TTM_PL_FLAG_UNCACHED | \
79*592ffb21SWarner Losh 				 TTM_PL_FLAG_WC)
80*592ffb21SWarner Losh 
81*592ffb21SWarner Losh #define TTM_PL_MASK_MEMTYPE     (TTM_PL_MASK_MEM | TTM_PL_MASK_CACHING)
82*592ffb21SWarner Losh 
83*592ffb21SWarner Losh /*
84*592ffb21SWarner Losh  * Access flags to be used for CPU- and GPU- mappings.
85*592ffb21SWarner Losh  * The idea is that the TTM synchronization mechanism will
86*592ffb21SWarner Losh  * allow concurrent READ access and exclusive write access.
87*592ffb21SWarner Losh  * Currently GPU- and CPU accesses are exclusive.
88*592ffb21SWarner Losh  */
89*592ffb21SWarner Losh 
90*592ffb21SWarner Losh #define TTM_ACCESS_READ         (1 << 0)
91*592ffb21SWarner Losh #define TTM_ACCESS_WRITE        (1 << 1)
92*592ffb21SWarner Losh 
93*592ffb21SWarner Losh #endif
94