xref: /freebsd/sys/dev/drm2/drm_mode.h (revision 4ce386ff25d77954b8cfa11534f632172e848244)
1 /*
2  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
3  * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
4  * Copyright (c) 2008 Red Hat Inc.
5  * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
6  * Copyright (c) 2007-2008 Intel Corporation
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24  * IN THE SOFTWARE.
25  *
26  * $FreeBSD$
27  */
28 
29 #ifndef _DRM_MODE_H
30 #define _DRM_MODE_H
31 
32 #define DRM_DISPLAY_INFO_LEN	32
33 #define DRM_CONNECTOR_NAME_LEN	32
34 #define DRM_DISPLAY_MODE_LEN	32
35 #define DRM_PROP_NAME_LEN	32
36 
37 #define DRM_MODE_TYPE_BUILTIN	(1<<0)
38 #define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
39 #define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
40 #define DRM_MODE_TYPE_PREFERRED	(1<<3)
41 #define DRM_MODE_TYPE_DEFAULT	(1<<4)
42 #define DRM_MODE_TYPE_USERDEF	(1<<5)
43 #define DRM_MODE_TYPE_DRIVER	(1<<6)
44 
45 /* Video mode flags */
46 /* bit compatible with the xorg definitions. */
47 #define DRM_MODE_FLAG_PHSYNC	(1<<0)
48 #define DRM_MODE_FLAG_NHSYNC	(1<<1)
49 #define DRM_MODE_FLAG_PVSYNC	(1<<2)
50 #define DRM_MODE_FLAG_NVSYNC	(1<<3)
51 #define DRM_MODE_FLAG_INTERLACE	(1<<4)
52 #define DRM_MODE_FLAG_DBLSCAN	(1<<5)
53 #define DRM_MODE_FLAG_CSYNC	(1<<6)
54 #define DRM_MODE_FLAG_PCSYNC	(1<<7)
55 #define DRM_MODE_FLAG_NCSYNC	(1<<8)
56 #define DRM_MODE_FLAG_HSKEW	(1<<9) /* hskew provided */
57 #define DRM_MODE_FLAG_BCAST	(1<<10)
58 #define DRM_MODE_FLAG_PIXMUX	(1<<11)
59 #define DRM_MODE_FLAG_DBLCLK	(1<<12)
60 #define DRM_MODE_FLAG_CLKDIV2	(1<<13)
61 
62 /* DPMS flags */
63 /* bit compatible with the xorg definitions. */
64 #define DRM_MODE_DPMS_ON	0
65 #define DRM_MODE_DPMS_STANDBY	1
66 #define DRM_MODE_DPMS_SUSPEND	2
67 #define DRM_MODE_DPMS_OFF	3
68 
69 /* Scaling mode options */
70 #define DRM_MODE_SCALE_NONE		0 /* Unmodified timing (display or
71 					     software can still scale) */
72 #define DRM_MODE_SCALE_FULLSCREEN	1 /* Full screen, ignore aspect */
73 #define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
74 #define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */
75 
76 /* Dithering mode options */
77 #define DRM_MODE_DITHERING_OFF	0
78 #define DRM_MODE_DITHERING_ON	1
79 #define DRM_MODE_DITHERING_AUTO 2
80 
81 /* Dirty info options */
82 #define DRM_MODE_DIRTY_OFF      0
83 #define DRM_MODE_DIRTY_ON       1
84 #define DRM_MODE_DIRTY_ANNOTATE 2
85 
86 struct drm_mode_modeinfo {
87 	uint32_t clock;
88 	uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew;
89 	uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan;
90 
91 	uint32_t vrefresh;
92 
93 	uint32_t flags;
94 	uint32_t type;
95 	char name[DRM_DISPLAY_MODE_LEN];
96 };
97 
98 struct drm_mode_card_res {
99 	uint64_t fb_id_ptr;
100 	uint64_t crtc_id_ptr;
101 	uint64_t connector_id_ptr;
102 	uint64_t encoder_id_ptr;
103 	uint32_t count_fbs;
104 	uint32_t count_crtcs;
105 	uint32_t count_connectors;
106 	uint32_t count_encoders;
107 	uint32_t min_width, max_width;
108 	uint32_t min_height, max_height;
109 };
110 
111 struct drm_mode_crtc {
112 	uint64_t set_connectors_ptr;
113 	uint32_t count_connectors;
114 
115 	uint32_t crtc_id; /**< Id */
116 	uint32_t fb_id; /**< Id of framebuffer */
117 
118 	uint32_t x, y; /**< Position on the frameuffer */
119 
120 	uint32_t gamma_size;
121 	uint32_t mode_valid;
122 	struct drm_mode_modeinfo mode;
123 };
124 
125 #define DRM_MODE_PRESENT_TOP_FIELD	(1<<0)
126 #define DRM_MODE_PRESENT_BOTTOM_FIELD	(1<<1)
127 
128 /* Planes blend with or override other bits on the CRTC */
129 struct drm_mode_set_plane {
130 	uint32_t plane_id;
131 	uint32_t crtc_id;
132 	uint32_t fb_id; /* fb object contains surface format type */
133 	uint32_t flags; /* see above flags */
134 
135 	/* Signed dest location allows it to be partially off screen */
136 	int32_t crtc_x, crtc_y;
137 	uint32_t crtc_w, crtc_h;
138 
139 	/* Source values are 16.16 fixed point */
140 	uint32_t src_x, src_y;
141 	uint32_t src_h, src_w;
142 };
143 
144 struct drm_mode_get_plane {
145 	uint32_t plane_id;
146 
147 	uint32_t crtc_id;
148 	uint32_t fb_id;
149 
150 	uint32_t possible_crtcs;
151 	uint32_t gamma_size;
152 
153 	uint32_t count_format_types;
154 	uint64_t format_type_ptr;
155 };
156 
157 struct drm_mode_get_plane_res {
158 	uint64_t plane_id_ptr;
159 	uint32_t count_planes;
160 };
161 
162 #define DRM_MODE_ENCODER_NONE	0
163 #define DRM_MODE_ENCODER_DAC	1
164 #define DRM_MODE_ENCODER_TMDS	2
165 #define DRM_MODE_ENCODER_LVDS	3
166 #define DRM_MODE_ENCODER_TVDAC	4
167 
168 struct drm_mode_get_encoder {
169 	uint32_t encoder_id;
170 	uint32_t encoder_type;
171 
172 	uint32_t crtc_id; /**< Id of crtc */
173 
174 	uint32_t possible_crtcs;
175 	uint32_t possible_clones;
176 };
177 
178 /* This is for connectors with multiple signal types. */
179 /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
180 #define DRM_MODE_SUBCONNECTOR_Automatic	0
181 #define DRM_MODE_SUBCONNECTOR_Unknown	0
182 #define DRM_MODE_SUBCONNECTOR_DVID	3
183 #define DRM_MODE_SUBCONNECTOR_DVIA	4
184 #define DRM_MODE_SUBCONNECTOR_Composite	5
185 #define DRM_MODE_SUBCONNECTOR_SVIDEO	6
186 #define DRM_MODE_SUBCONNECTOR_Component	8
187 #define DRM_MODE_SUBCONNECTOR_SCART	9
188 
189 #define DRM_MODE_CONNECTOR_Unknown	0
190 #define DRM_MODE_CONNECTOR_VGA		1
191 #define DRM_MODE_CONNECTOR_DVII		2
192 #define DRM_MODE_CONNECTOR_DVID		3
193 #define DRM_MODE_CONNECTOR_DVIA		4
194 #define DRM_MODE_CONNECTOR_Composite	5
195 #define DRM_MODE_CONNECTOR_SVIDEO	6
196 #define DRM_MODE_CONNECTOR_LVDS		7
197 #define DRM_MODE_CONNECTOR_Component	8
198 #define DRM_MODE_CONNECTOR_9PinDIN	9
199 #define DRM_MODE_CONNECTOR_DisplayPort	10
200 #define DRM_MODE_CONNECTOR_HDMIA	11
201 #define DRM_MODE_CONNECTOR_HDMIB	12
202 #define DRM_MODE_CONNECTOR_TV		13
203 #define DRM_MODE_CONNECTOR_eDP		14
204 
205 struct drm_mode_get_connector {
206 
207 	uint64_t encoders_ptr;
208 	uint64_t modes_ptr;
209 	uint64_t props_ptr;
210 	uint64_t prop_values_ptr;
211 
212 	uint32_t count_modes;
213 	uint32_t count_props;
214 	uint32_t count_encoders;
215 
216 	uint32_t encoder_id; /**< Current Encoder */
217 	uint32_t connector_id; /**< Id */
218 	uint32_t connector_type;
219 	uint32_t connector_type_id;
220 
221 	uint32_t connection;
222 	uint32_t mm_width, mm_height; /**< HxW in millimeters */
223 	uint32_t subpixel;
224 };
225 
226 #define DRM_MODE_PROP_PENDING	(1<<0)
227 #define DRM_MODE_PROP_RANGE	(1<<1)
228 #define DRM_MODE_PROP_IMMUTABLE	(1<<2)
229 #define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
230 #define DRM_MODE_PROP_BLOB	(1<<4)
231 #define DRM_MODE_PROP_BITMASK	(1<<5) /* bitmask of enumerated types */
232 
233 struct drm_mode_property_enum {
234 	uint64_t value;
235 	char name[DRM_PROP_NAME_LEN];
236 };
237 
238 struct drm_mode_get_property {
239 	uint64_t values_ptr; /* values and blob lengths */
240 	uint64_t enum_blob_ptr; /* enum and blob id ptrs */
241 
242 	uint32_t prop_id;
243 	uint32_t flags;
244 	char name[DRM_PROP_NAME_LEN];
245 
246 	uint32_t count_values;
247 	uint32_t count_enum_blobs;
248 };
249 
250 struct drm_mode_connector_set_property {
251 	uint64_t value;
252 	uint32_t prop_id;
253 	uint32_t connector_id;
254 };
255 
256 struct drm_mode_obj_get_properties {
257 	uint64_t props_ptr;
258 	uint64_t prop_values_ptr;
259 	uint32_t count_props;
260 	uint32_t obj_id;
261 	uint32_t obj_type;
262 };
263 
264 struct drm_mode_obj_set_property {
265 	uint64_t value;
266 	uint32_t prop_id;
267 	uint32_t obj_id;
268 	uint32_t obj_type;
269 };
270 
271 struct drm_mode_get_blob {
272 	uint32_t blob_id;
273 	uint32_t length;
274 	uint64_t data;
275 };
276 
277 struct drm_mode_fb_cmd {
278 	uint32_t fb_id;
279 	uint32_t width, height;
280 	uint32_t pitch;
281 	uint32_t bpp;
282 	uint32_t depth;
283 	/* driver specific handle */
284 	uint32_t handle;
285 };
286 
287 #define DRM_MODE_FB_INTERLACED	(1<<0 /* for interlaced framebuffers */
288 
289 struct drm_mode_fb_cmd2 {
290 	uint32_t fb_id;
291 	uint32_t width, height;
292 	uint32_t pixel_format; /* fourcc code from drm_fourcc.h */
293 	uint32_t flags; /* see above flags */
294 
295 	/*
296 	 * In case of planar formats, this ioctl allows up to 4
297 	 * buffer objects with offets and pitches per plane.
298 	 * The pitch and offset order is dictated by the fourcc,
299 	 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
300 	 *
301 	 *   YUV 4:2:0 image with a plane of 8 bit Y samples
302 	 *   followed by an interleaved U/V plane containing
303 	 *   8 bit 2x2 subsampled colour difference samples.
304 	 *
305 	 * So it would consist of Y as offset[0] and UV as
306 	 * offeset[1].  Note that offset[0] will generally
307 	 * be 0.
308 	 */
309 	uint32_t handles[4];
310 	uint32_t pitches[4]; /* pitch for each plane */
311 	uint32_t offsets[4]; /* offset of each plane */
312 };
313 
314 #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
315 #define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
316 #define DRM_MODE_FB_DIRTY_FLAGS         0x03
317 
318 #define DRM_MODE_FB_DIRTY_MAX_CLIPS     256
319 
320 /*
321  * Mark a region of a framebuffer as dirty.
322  *
323  * Some hardware does not automatically update display contents
324  * as a hardware or software draw to a framebuffer. This ioctl
325  * allows userspace to tell the kernel and the hardware what
326  * regions of the framebuffer have changed.
327  *
328  * The kernel or hardware is free to update more then just the
329  * region specified by the clip rects. The kernel or hardware
330  * may also delay and/or coalesce several calls to dirty into a
331  * single update.
332  *
333  * Userspace may annotate the updates, the annotates are a
334  * promise made by the caller that the change is either a copy
335  * of pixels or a fill of a single color in the region specified.
336  *
337  * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
338  * the number of updated regions are half of num_clips given,
339  * where the clip rects are paired in src and dst. The width and
340  * height of each one of the pairs must match.
341  *
342  * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
343  * promises that the region specified of the clip rects is filled
344  * completely with a single color as given in the color argument.
345  */
346 
347 struct drm_mode_fb_dirty_cmd {
348 	uint32_t fb_id;
349 	uint32_t flags;
350 	uint32_t color;
351 	uint32_t num_clips;
352 	uint64_t clips_ptr;
353 };
354 
355 struct drm_mode_mode_cmd {
356 	uint32_t connector_id;
357 	struct drm_mode_modeinfo mode;
358 };
359 
360 #define DRM_MODE_CURSOR_BO	(1<<0)
361 #define DRM_MODE_CURSOR_MOVE	(1<<1)
362 
363 /*
364  * depending on the value in flags diffrent members are used.
365  *
366  * CURSOR_BO uses
367  *    crtc
368  *    width
369  *    height
370  *    handle - if 0 turns the cursor of
371  *
372  * CURSOR_MOVE uses
373  *    crtc
374  *    x
375  *    y
376  */
377 struct drm_mode_cursor {
378 	uint32_t flags;
379 	uint32_t crtc_id;
380 	int32_t x;
381 	int32_t y;
382 	uint32_t width;
383 	uint32_t height;
384 	/* driver specific handle */
385 	uint32_t handle;
386 };
387 
388 struct drm_mode_crtc_lut {
389 	uint32_t crtc_id;
390 	uint32_t gamma_size;
391 
392 	/* pointers to arrays */
393 	uint64_t red;
394 	uint64_t green;
395 	uint64_t blue;
396 };
397 
398 #define DRM_MODE_PAGE_FLIP_EVENT 0x01
399 #define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
400 
401 /*
402  * Request a page flip on the specified crtc.
403  *
404  * This ioctl will ask KMS to schedule a page flip for the specified
405  * crtc.  Once any pending rendering targeting the specified fb (as of
406  * ioctl time) has completed, the crtc will be reprogrammed to display
407  * that fb after the next vertical refresh.  The ioctl returns
408  * immediately, but subsequent rendering to the current fb will block
409  * in the execbuffer ioctl until the page flip happens.  If a page
410  * flip is already pending as the ioctl is called, EBUSY will be
411  * returned.
412  *
413  * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
414  * request that drm sends back a vblank event (see drm.h: struct
415  * drm_event_vblank) when the page flip is done.  The user_data field
416  * passed in with this ioctl will be returned as the user_data field
417  * in the vblank event struct.
418  *
419  * The reserved field must be zero until we figure out something
420  * clever to use it for.
421  */
422 
423 struct drm_mode_crtc_page_flip {
424 	uint32_t crtc_id;
425 	uint32_t fb_id;
426 	uint32_t flags;
427 	uint32_t reserved;
428 	uint64_t user_data;
429 };
430 
431 /* create a dumb scanout buffer */
432 struct drm_mode_create_dumb {
433 	uint32_t height;
434 	uint32_t width;
435 	uint32_t bpp;
436 	uint32_t flags;
437 	/* handle, pitch, size will be returned */
438 	uint32_t handle;
439 	uint32_t pitch;
440 	uint64_t size;
441 };
442 
443 /* set up for mmap of a dumb scanout buffer */
444 struct drm_mode_map_dumb {
445 	/** Handle for the object being mapped. */
446 	uint32_t handle;
447 	uint32_t pad;
448 	/**
449 	 * Fake offset to use for subsequent mmap call
450 	 *
451 	 * This is a fixed-size type for 32/64 compatibility.
452 	 */
453 	uint64_t offset;
454 };
455 
456 struct drm_mode_destroy_dumb {
457 	uint32_t handle;
458 };
459 
460 #endif
461