1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 /* 27 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 28 * DP and DPCD versions are independent. Differences from 1.0 are not noted, 29 * 1.0 devices basically don't exist in the wild. 30 * 31 * Abbreviations, in chronological order: 32 * 33 * eDP: Embedded DisplayPort version 1 34 * DPI: DisplayPort Interoperability Guideline v1.1a 35 * 1.2: DisplayPort 1.2 36 * 37 * 1.2 formally includes both eDP and DPI definitions. 38 */ 39 40 #define AUX_NATIVE_WRITE 0x8 41 #define AUX_NATIVE_READ 0x9 42 #define AUX_I2C_WRITE 0x0 43 #define AUX_I2C_READ 0x1 44 #define AUX_I2C_STATUS 0x2 45 #define AUX_I2C_MOT 0x4 46 47 #define AUX_NATIVE_REPLY_ACK (0x0 << 4) 48 #define AUX_NATIVE_REPLY_NACK (0x1 << 4) 49 #define AUX_NATIVE_REPLY_DEFER (0x2 << 4) 50 #define AUX_NATIVE_REPLY_MASK (0x3 << 4) 51 52 #define AUX_I2C_REPLY_ACK (0x0 << 6) 53 #define AUX_I2C_REPLY_NACK (0x1 << 6) 54 #define AUX_I2C_REPLY_DEFER (0x2 << 6) 55 #define AUX_I2C_REPLY_MASK (0x3 << 6) 56 57 /* AUX CH addresses */ 58 /* DPCD */ 59 #define DP_DPCD_REV 0x000 60 61 #define DP_MAX_LINK_RATE 0x001 62 63 #define DP_MAX_LANE_COUNT 0x002 64 # define DP_MAX_LANE_COUNT_MASK 0x1f 65 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 66 # define DP_ENHANCED_FRAME_CAP (1 << 7) 67 68 #define DP_MAX_DOWNSPREAD 0x003 69 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 70 71 #define DP_NORP 0x004 72 73 #define DP_DOWNSTREAMPORT_PRESENT 0x005 74 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 75 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 76 /* 00b = DisplayPort */ 77 /* 01b = Analog */ 78 /* 10b = TMDS or HDMI */ 79 /* 11b = Other */ 80 # define DP_FORMAT_CONVERSION (1 << 3) 81 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 82 83 #define DP_MAIN_LINK_CHANNEL_CODING 0x006 84 85 #define DP_DOWN_STREAM_PORT_COUNT 0x007 86 # define DP_PORT_COUNT_MASK 0x0f 87 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 88 # define DP_OUI_SUPPORT (1 << 7) 89 90 #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 91 # define DP_I2C_SPEED_1K 0x01 92 # define DP_I2C_SPEED_5K 0x02 93 # define DP_I2C_SPEED_10K 0x04 94 # define DP_I2C_SPEED_100K 0x08 95 # define DP_I2C_SPEED_400K 0x10 96 # define DP_I2C_SPEED_1M 0x20 97 98 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 99 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 100 101 /* Multiple stream transport */ 102 #define DP_MSTM_CAP 0x021 /* 1.2 */ 103 # define DP_MST_CAP (1 << 0) 104 105 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 106 # define DP_PSR_IS_SUPPORTED 1 107 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 108 # define DP_PSR_NO_TRAIN_ON_EXIT 1 109 # define DP_PSR_SETUP_TIME_330 (0 << 1) 110 # define DP_PSR_SETUP_TIME_275 (1 << 1) 111 # define DP_PSR_SETUP_TIME_220 (2 << 1) 112 # define DP_PSR_SETUP_TIME_165 (3 << 1) 113 # define DP_PSR_SETUP_TIME_110 (4 << 1) 114 # define DP_PSR_SETUP_TIME_55 (5 << 1) 115 # define DP_PSR_SETUP_TIME_0 (6 << 1) 116 # define DP_PSR_SETUP_TIME_MASK (7 << 1) 117 # define DP_PSR_SETUP_TIME_SHIFT 1 118 119 /* 120 * 0x80-0x8f describe downstream port capabilities, but there are two layouts 121 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 122 * each port's descriptor is one byte wide. If it was set, each port's is 123 * four bytes wide, starting with the one byte from the base info. As of 124 * DP interop v1.1a only VGA defines additional detail. 125 */ 126 127 /* offset 0 */ 128 #define DP_DOWNSTREAM_PORT_0 0x80 129 # define DP_DS_PORT_TYPE_MASK (7 << 0) 130 # define DP_DS_PORT_TYPE_DP 0 131 # define DP_DS_PORT_TYPE_VGA 1 132 # define DP_DS_PORT_TYPE_DVI 2 133 # define DP_DS_PORT_TYPE_HDMI 3 134 # define DP_DS_PORT_TYPE_NON_EDID 4 135 # define DP_DS_PORT_HPD (1 << 3) 136 /* offset 1 for VGA is maximum megapixels per second / 8 */ 137 /* offset 2 */ 138 # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) 139 # define DP_DS_VGA_8BPC 0 140 # define DP_DS_VGA_10BPC 1 141 # define DP_DS_VGA_12BPC 2 142 # define DP_DS_VGA_16BPC 3 143 144 /* link configuration */ 145 #define DP_LINK_BW_SET 0x100 146 # define DP_LINK_BW_1_62 0x06 147 # define DP_LINK_BW_2_7 0x0a 148 # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 149 150 #define DP_LANE_COUNT_SET 0x101 151 # define DP_LANE_COUNT_MASK 0x0f 152 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 153 154 #define DP_TRAINING_PATTERN_SET 0x102 155 # define DP_TRAINING_PATTERN_DISABLE 0 156 # define DP_TRAINING_PATTERN_1 1 157 # define DP_TRAINING_PATTERN_2 2 158 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 159 # define DP_TRAINING_PATTERN_MASK 0x3 160 161 # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) 162 # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) 163 # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) 164 # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) 165 # define DP_LINK_QUAL_PATTERN_MASK (3 << 2) 166 167 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 168 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 169 170 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 171 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 172 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 173 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 174 175 #define DP_TRAINING_LANE0_SET 0x103 176 #define DP_TRAINING_LANE1_SET 0x104 177 #define DP_TRAINING_LANE2_SET 0x105 178 #define DP_TRAINING_LANE3_SET 0x106 179 180 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 181 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 182 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 183 # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) 184 # define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) 185 # define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) 186 # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) 187 188 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 189 # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) 190 # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) 191 # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) 192 # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) 193 194 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 195 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 196 197 #define DP_DOWNSPREAD_CTRL 0x107 198 # define DP_SPREAD_AMP_0_5 (1 << 4) 199 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 200 201 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 202 # define DP_SET_ANSI_8B10B (1 << 0) 203 204 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 205 /* bitmask as for DP_I2C_SPEED_CAP */ 206 207 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 208 209 #define DP_MSTM_CTRL 0x111 /* 1.2 */ 210 # define DP_MST_EN (1 << 0) 211 # define DP_UP_REQ_EN (1 << 1) 212 # define DP_UPSTREAM_IS_SRC (1 << 2) 213 214 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 215 # define DP_PSR_ENABLE (1 << 0) 216 # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 217 # define DP_PSR_CRC_VERIFICATION (1 << 2) 218 # define DP_PSR_FRAME_CAPTURE (1 << 3) 219 220 #define DP_SINK_COUNT 0x200 221 /* prior to 1.2 bit 7 was reserved mbz */ 222 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 223 # define DP_SINK_CP_READY (1 << 6) 224 225 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 226 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 227 # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 228 # define DP_CP_IRQ (1 << 2) 229 # define DP_SINK_SPECIFIC_IRQ (1 << 6) 230 231 #define DP_LANE0_1_STATUS 0x202 232 #define DP_LANE2_3_STATUS 0x203 233 # define DP_LANE_CR_DONE (1 << 0) 234 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 235 # define DP_LANE_SYMBOL_LOCKED (1 << 2) 236 237 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 238 DP_LANE_CHANNEL_EQ_DONE | \ 239 DP_LANE_SYMBOL_LOCKED) 240 241 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 242 243 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 244 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 245 #define DP_LINK_STATUS_UPDATED (1 << 7) 246 247 #define DP_SINK_STATUS 0x205 248 249 #define DP_RECEIVE_PORT_0_STATUS (1 << 0) 250 #define DP_RECEIVE_PORT_1_STATUS (1 << 1) 251 252 #define DP_ADJUST_REQUEST_LANE0_1 0x206 253 #define DP_ADJUST_REQUEST_LANE2_3 0x207 254 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 255 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 256 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 257 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 258 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 259 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 260 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 261 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 262 263 #define DP_TEST_REQUEST 0x218 264 # define DP_TEST_LINK_TRAINING (1 << 0) 265 # define DP_TEST_LINK_PATTERN (1 << 1) 266 # define DP_TEST_LINK_EDID_READ (1 << 2) 267 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 268 269 #define DP_TEST_LINK_RATE 0x219 270 # define DP_LINK_RATE_162 (0x6) 271 # define DP_LINK_RATE_27 (0xa) 272 273 #define DP_TEST_LANE_COUNT 0x220 274 275 #define DP_TEST_PATTERN 0x221 276 277 #define DP_TEST_RESPONSE 0x260 278 # define DP_TEST_ACK (1 << 0) 279 # define DP_TEST_NAK (1 << 1) 280 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 281 282 #define DP_SOURCE_OUI 0x300 283 #define DP_SINK_OUI 0x400 284 #define DP_BRANCH_OUI 0x500 285 286 #define DP_SET_POWER 0x600 287 # define DP_SET_POWER_D0 0x1 288 # define DP_SET_POWER_D3 0x2 289 290 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 291 # define DP_PSR_LINK_CRC_ERROR (1 << 0) 292 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 293 294 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 295 # define DP_PSR_CAPS_CHANGE (1 << 0) 296 297 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 298 # define DP_PSR_SINK_INACTIVE 0 299 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 300 # define DP_PSR_SINK_ACTIVE_RFB 2 301 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 302 # define DP_PSR_SINK_ACTIVE_RESYNC 4 303 # define DP_PSR_SINK_INTERNAL_ERROR 7 304 # define DP_PSR_SINK_STATE_MASK 0x07 305 306 #define MODE_I2C_START 1 307 #define MODE_I2C_WRITE 2 308 #define MODE_I2C_READ 4 309 #define MODE_I2C_STOP 8 310 311 struct iic_dp_aux_data { 312 bool running; 313 u16 address; 314 void *priv; 315 int (*aux_ch)(device_t adapter, int mode, uint8_t write_byte, 316 uint8_t *read_byte); 317 device_t port; 318 }; 319 320 int iic_dp_aux_add_bus(device_t dev, const char *name, 321 int (*ch)(device_t idev, int mode, uint8_t write_byte, uint8_t *read_byte), 322 void *priv, device_t *bus, device_t *adapter); 323 324 325 #define DP_LINK_STATUS_SIZE 6 326 bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], 327 int lane_count); 328 bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], 329 int lane_count); 330 u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], 331 int lane); 332 u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], 333 int lane); 334 335 #define DP_RECEIVER_CAP_SIZE 0xf 336 void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); 337 void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); 338 339 u8 drm_dp_link_rate_to_bw_code(int link_rate); 340 int drm_dp_bw_code_to_link_rate(u8 link_bw); 341 342 static inline int 343 drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) 344 { 345 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 346 } 347 348 static inline u8 349 drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE]) 350 { 351 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 352 } 353 354 #endif /* _DRM_DP_HELPER_H_ */ 355