1 /* 2 * Copyright © 2009 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #include <sys/cdefs.h> 24 __FBSDID("$FreeBSD$"); 25 26 #include <dev/drm2/drmP.h> 27 #include <dev/drm2/drm_dp_helper.h> 28 29 /** 30 * DOC: dp helpers 31 * 32 * These functions contain some common logic and helpers at various abstraction 33 * levels to deal with Display Port sink devices and related things like DP aux 34 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 35 * blocks, ... 36 */ 37 38 static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r) 39 { 40 return link_status[r - DP_LANE0_1_STATUS]; 41 } 42 43 static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], 44 int lane) 45 { 46 int i = DP_LANE0_1_STATUS + (lane >> 1); 47 int s = (lane & 1) * 4; 48 u8 l = dp_link_status(link_status, i); 49 return (l >> s) & 0xf; 50 } 51 52 bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], 53 int lane_count) 54 { 55 u8 lane_align; 56 u8 lane_status; 57 int lane; 58 59 lane_align = dp_link_status(link_status, 60 DP_LANE_ALIGN_STATUS_UPDATED); 61 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 62 return false; 63 for (lane = 0; lane < lane_count; lane++) { 64 lane_status = dp_get_lane_status(link_status, lane); 65 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 66 return false; 67 } 68 return true; 69 } 70 71 bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], 72 int lane_count) 73 { 74 int lane; 75 u8 lane_status; 76 77 for (lane = 0; lane < lane_count; lane++) { 78 lane_status = dp_get_lane_status(link_status, lane); 79 if ((lane_status & DP_LANE_CR_DONE) == 0) 80 return false; 81 } 82 return true; 83 } 84 85 u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], 86 int lane) 87 { 88 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 89 int s = ((lane & 1) ? 90 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 91 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 92 u8 l = dp_link_status(link_status, i); 93 94 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 95 } 96 97 u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], 98 int lane) 99 { 100 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 101 int s = ((lane & 1) ? 102 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 103 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 104 u8 l = dp_link_status(link_status, i); 105 106 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 107 } 108 109 void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) { 110 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) 111 DRM_UDELAY(100); 112 else 113 DRM_MDELAY(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); 114 } 115 116 void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) { 117 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) 118 DRM_UDELAY(400); 119 else 120 DRM_MDELAY(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); 121 } 122 123 u8 drm_dp_link_rate_to_bw_code(int link_rate) 124 { 125 switch (link_rate) { 126 case 162000: 127 default: 128 return DP_LINK_BW_1_62; 129 case 270000: 130 return DP_LINK_BW_2_7; 131 case 540000: 132 return DP_LINK_BW_5_4; 133 } 134 } 135 136 int drm_dp_bw_code_to_link_rate(u8 link_bw) 137 { 138 switch (link_bw) { 139 case DP_LINK_BW_1_62: 140 default: 141 return 162000; 142 case DP_LINK_BW_2_7: 143 return 270000; 144 case DP_LINK_BW_5_4: 145 return 540000; 146 } 147 } 148