1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2022 Bjoern A. Zeeb 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/kernel.h> 30 #include <sys/bus.h> 31 #include <sys/rman.h> 32 #include <sys/endian.h> 33 #include <sys/socket.h> 34 35 #include <machine/bus.h> 36 #include <machine/resource.h> 37 38 #include <net/if.h> 39 #include <net/if_var.h> 40 #include <net/if_media.h> 41 42 #include <dev/mii/mii.h> 43 #include <dev/mii/miivar.h> 44 45 #include "memac_mdio.h" 46 #include "miibus_if.h" 47 48 /* #define MEMAC_MDIO_DEBUG */ 49 50 /* -------------------------------------------------------------------------- */ 51 52 int 53 memacphy_miibus_readreg(device_t dev, int phy, int reg) 54 { 55 56 return (MIIBUS_READREG(device_get_parent(dev), phy, reg)); 57 } 58 59 int 60 memacphy_miibus_writereg(device_t dev, int phy, int reg, int data) 61 { 62 63 return (MIIBUS_WRITEREG(device_get_parent(dev), phy, reg, data)); 64 } 65 66 void 67 memacphy_miibus_statchg(struct memacphy_softc_common *sc) 68 { 69 70 if (sc->dpnidev != NULL) 71 MIIBUS_STATCHG(sc->dpnidev); 72 } 73 74 int 75 memacphy_set_ni_dev(struct memacphy_softc_common *sc, device_t nidev) 76 { 77 78 if (nidev == NULL) 79 return (EINVAL); 80 81 #if defined(MEMAC_MDIO_DEBUG) 82 if (bootverbose) 83 device_printf(sc->dev, "setting nidev %p (%s)\n", 84 nidev, device_get_nameunit(nidev)); 85 #endif 86 87 if (sc->dpnidev != NULL) 88 return (EBUSY); 89 90 sc->dpnidev = nidev; 91 return (0); 92 } 93 94 int 95 memacphy_get_phy_loc(struct memacphy_softc_common *sc, int *phy_loc) 96 { 97 int error; 98 99 if (phy_loc == NULL) 100 return (EINVAL); 101 102 if (sc->phy == -1) { 103 *phy_loc = MII_PHY_ANY; 104 error = ENODEV; 105 } else { 106 *phy_loc = sc->phy; 107 error = 0; 108 } 109 110 #if defined(MEMAC_MDIO_DEBUG) 111 if (bootverbose) 112 device_printf(sc->dev, "returning phy_loc %d, error %d\n", 113 *phy_loc, error); 114 #endif 115 116 return (error); 117 } 118 119 /* -------------------------------------------------------------------------- */ 120 121 /* 122 * MDIO Ethernet Management Interface Registers (internal PCS MDIO PHY) 123 * 0x0030 MDIO Configuration Register (MDIO_CFG) 124 * 0x0034 MDIO Control Register (MDIO_CTL) 125 * 0x0038 MDIO Data Register (MDIO_DATA) 126 * 0x003c MDIO Register Address Register (MDIO_ADDR) 127 * 128 * External MDIO interfaces 129 * 0x0030 External MDIO Configuration Register (EMDIO_CFG) 130 * 0x0034 External MDIO Control Register (EMDIO_CTL) 131 * 0x0038 External MDIO Data Register (EMDIO_DATA) 132 * 0x003c External MDIO Register Address Register (EMDIO_ADDR) 133 */ 134 #define MDIO_CFG 0x00030 135 #define MDIO_CFG_MDIO_RD_ER (1 << 1) 136 #define MDIO_CFG_ENC45 (1 << 6) 137 #define MDIO_CFG_BUSY (1 << 31) 138 #define MDIO_CTL 0x00034 139 #define MDIO_CTL_READ (1 << 15) 140 #define MDIO_CTL_PORT_ADDR(_x) (((_x) & 0x1f) << 5) 141 #define MDIO_CTL_DEV_ADDR(_x) ((_x) & 0x1f) 142 #define MDIO_DATA 0x00038 143 #define MDIO_ADDR 0x0003c 144 145 static uint32_t 146 memac_read_4(struct memac_mdio_softc_common *sc, uint32_t reg) 147 { 148 uint32_t v, r; 149 150 v = bus_read_4(sc->mem_res, reg); 151 if (sc->is_little_endian) 152 r = le32toh(v); 153 else 154 r = be32toh(v); 155 156 return (r); 157 } 158 159 static void 160 memac_write_4(struct memac_mdio_softc_common *sc, uint32_t reg, uint32_t val) 161 { 162 uint32_t v; 163 164 if (sc->is_little_endian) 165 v = htole32(val); 166 else 167 v = htobe32(val); 168 bus_write_4(sc->mem_res, reg, v); 169 } 170 171 static uint32_t 172 memac_miibus_wait_no_busy(struct memac_mdio_softc_common *sc) 173 { 174 uint32_t count, val; 175 176 for (count = 1000; count > 0; count--) { 177 val = memac_read_4(sc, MDIO_CFG); 178 if ((val & MDIO_CFG_BUSY) == 0) 179 break; 180 DELAY(1); 181 } 182 183 if (count == 0) 184 return (0xffff); 185 186 return (0); 187 } 188 189 int 190 memac_miibus_readreg(struct memac_mdio_softc_common *sc, int phy, int reg) 191 { 192 uint32_t cfg, ctl, val; 193 194 /* Set proper Clause 45 mode. */ 195 cfg = memac_read_4(sc, MDIO_CFG); 196 /* XXX 45 support? */ 197 cfg &= ~MDIO_CFG_ENC45; /* Use Clause 22 */ 198 memac_write_4(sc, MDIO_CFG, cfg); 199 200 val = memac_miibus_wait_no_busy(sc); 201 if (val != 0) 202 return (0xffff); 203 204 /* To whom do we want to talk to.. */ 205 ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(reg); 206 /* XXX do we need two writes for this to work reliably? */ 207 memac_write_4(sc, MDIO_CTL, ctl | MDIO_CTL_READ); 208 209 val = memac_miibus_wait_no_busy(sc); 210 if (val != 0) 211 return (0xffff); 212 213 cfg = memac_read_4(sc, MDIO_CFG); 214 if (cfg & MDIO_CFG_MDIO_RD_ER) 215 return (0xffff); 216 217 val = memac_read_4(sc, MDIO_DATA); 218 val &= 0xffff; 219 220 #if defined(MEMAC_MDIO_DEBUG) 221 device_printf(sc->dev, "phy read %d:%d = %#06x\n", phy, reg, val); 222 #endif 223 224 return (val); 225 } 226 227 int 228 memac_miibus_writereg(struct memac_mdio_softc_common *sc, int phy, int reg, int data) 229 { 230 uint32_t cfg, ctl, val; 231 232 #if defined(MEMAC_MDIO_DEBUG) 233 device_printf(sc->dev, "phy write %d:%d\n", phy, reg); 234 #endif 235 236 /* Set proper Clause 45 mode. */ 237 cfg = memac_read_4(sc, MDIO_CFG); 238 /* XXX 45 support? */ 239 cfg &= ~MDIO_CFG_ENC45; /* Use Clause 22 */ 240 memac_write_4(sc, MDIO_CFG, cfg); 241 242 val = memac_miibus_wait_no_busy(sc); 243 if (val != 0) 244 return (0xffff); 245 246 /* To whom do we want to talk to.. */ 247 ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(reg); 248 memac_write_4(sc, MDIO_CTL, ctl); 249 250 memac_write_4(sc, MDIO_DATA, data & 0xffff); 251 252 val = memac_miibus_wait_no_busy(sc); 253 if (val != 0) 254 return (0xffff); 255 256 return (0); 257 } 258 259 ssize_t 260 memac_mdio_get_property(device_t dev, device_t child, const char *propname, 261 void *propvalue, size_t size, device_property_type_t type) 262 { 263 264 return (bus_generic_get_property(dev, child, propname, propvalue, size, type)); 265 } 266 267 int 268 memac_mdio_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 269 { 270 271 return (BUS_READ_IVAR(device_get_parent(dev), dev, index, result)); 272 } 273 274 275 int 276 memac_mdio_generic_attach(struct memac_mdio_softc_common *sc) 277 { 278 int rid; 279 280 rid = 0; 281 sc->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 282 &rid, RF_ACTIVE | RF_SHAREABLE); 283 if (sc->mem_res == NULL) { 284 device_printf(sc->dev, "%s: cannot allocate mem resource\n", 285 __func__); 286 return (ENXIO); 287 } 288 289 sc->is_little_endian = device_has_property(sc->dev, "little-endian"); 290 291 return (0); 292 } 293 294 int 295 memac_mdio_generic_detach(struct memac_mdio_softc_common *sc) 296 { 297 298 if (sc->mem_res != NULL) 299 bus_release_resource(sc->dev, SYS_RES_MEMORY, 300 rman_get_rid(sc->mem_res), sc->mem_res); 301 302 return (0); 303 } 304