1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2023 Dmitry Salychev 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _DPAA2_SWP_H 29 #define _DPAA2_SWP_H 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include "dpaa2_types.h" 36 #include "dpaa2_bp.h" 37 38 /* 39 * DPAA2 QBMan software portal. 40 */ 41 42 /* All QBMan commands and result structures use this "valid bit" encoding. */ 43 #define DPAA2_SWP_VALID_BIT ((uint32_t) 0x80) 44 45 #define DPAA2_SWP_TIMEOUT 100000 /* in us */ 46 #define DPAA2_SWP_CMD_PARAMS_N 8u 47 #define DPAA2_SWP_RSP_PARAMS_N 8u 48 49 /* 50 * Maximum number of buffers that can be acquired/released through a single 51 * QBMan command. 52 */ 53 #define DPAA2_SWP_BUFS_PER_CMD 7u 54 55 /* 56 * Number of times to retry DPIO portal operations while waiting for portal to 57 * finish executing current command and become available. 58 * 59 * We want to avoid being stuck in a while loop in case hardware becomes 60 * unresponsive, but not give up too easily if the portal really is busy for 61 * valid reasons. 62 */ 63 #define DPAA2_SWP_BUSY_RETRIES 1000 64 65 /* Versions of the QBMan software portals. */ 66 #define DPAA2_SWP_REV_4000 0x04000000 67 #define DPAA2_SWP_REV_4100 0x04010000 68 #define DPAA2_SWP_REV_4101 0x04010001 69 #define DPAA2_SWP_REV_5000 0x05000000 70 71 #define DPAA2_SWP_REV_MASK 0xFFFF0000 72 73 /* Registers in the cache-inhibited area of the software portal. */ 74 #define DPAA2_SWP_CINH_CR 0x600 /* Management Command reg.*/ 75 #define DPAA2_SWP_CINH_EQCR_PI 0x800 /* Enqueue Ring, Producer Index */ 76 #define DPAA2_SWP_CINH_EQCR_CI 0x840 /* Enqueue Ring, Consumer Index */ 77 #define DPAA2_SWP_CINH_CR_RT 0x900 /* CR Read Trigger */ 78 #define DPAA2_SWP_CINH_VDQCR_RT 0x940 /* VDQCR Read Trigger */ 79 #define DPAA2_SWP_CINH_EQCR_AM_RT 0x980 80 #define DPAA2_SWP_CINH_RCR_AM_RT 0x9C0 81 #define DPAA2_SWP_CINH_DQPI 0xA00 /* DQRR Producer Index reg. */ 82 #define DPAA2_SWP_CINH_DQRR_ITR 0xA80 /* DQRR interrupt timeout reg. */ 83 #define DPAA2_SWP_CINH_DCAP 0xAC0 /* DQRR Consumption Ack. reg. */ 84 #define DPAA2_SWP_CINH_SDQCR 0xB00 /* Static Dequeue Command reg. */ 85 #define DPAA2_SWP_CINH_EQCR_AM_RT2 0xB40 86 #define DPAA2_SWP_CINH_RCR_PI 0xC00 /* Release Ring, Producer Index */ 87 #define DPAA2_SWP_CINH_RAR 0xCC0 /* Release Array Allocation reg. */ 88 #define DPAA2_SWP_CINH_CFG 0xD00 89 #define DPAA2_SWP_CINH_ISR 0xE00 90 #define DPAA2_SWP_CINH_IER 0xE40 91 #define DPAA2_SWP_CINH_ISDR 0xE80 92 #define DPAA2_SWP_CINH_IIR 0xEC0 93 #define DPAA2_SWP_CINH_ITPR 0xF40 94 95 /* Registers in the cache-enabled area of the software portal. */ 96 #define DPAA2_SWP_CENA_EQCR(n) (0x000 + ((uint32_t)(n) << 6)) 97 #define DPAA2_SWP_CENA_DQRR(n) (0x200 + ((uint32_t)(n) << 6)) 98 #define DPAA2_SWP_CENA_RCR(n) (0x400 + ((uint32_t)(n) << 6)) 99 #define DPAA2_SWP_CENA_CR (0x600) /* Management Command reg. */ 100 #define DPAA2_SWP_CENA_RR(vb) (0x700 + ((uint32_t)(vb) >> 1)) 101 #define DPAA2_SWP_CENA_VDQCR (0x780) 102 #define DPAA2_SWP_CENA_EQCR_CI (0x840) 103 104 /* Registers in the cache-enabled area of the software portal (memory-backed). */ 105 #define DPAA2_SWP_CENA_DQRR_MEM(n) (0x0800 + ((uint32_t)(n) << 6)) 106 #define DPAA2_SWP_CENA_RCR_MEM(n) (0x1400 + ((uint32_t)(n) << 6)) 107 #define DPAA2_SWP_CENA_CR_MEM (0x1600) /* Management Command reg. */ 108 #define DPAA2_SWP_CENA_RR_MEM (0x1680) /* Management Response reg. */ 109 #define DPAA2_SWP_CENA_VDQCR_MEM (0x1780) 110 #define DPAA2_SWP_CENA_EQCR_CI_MEMBACK (0x1840) 111 112 /* Shifts in the portal's configuration register. */ 113 #define DPAA2_SWP_CFG_DQRR_MF_SHIFT 20 114 #define DPAA2_SWP_CFG_EST_SHIFT 16 115 #define DPAA2_SWP_CFG_CPBS_SHIFT 15 116 #define DPAA2_SWP_CFG_WN_SHIFT 14 117 #define DPAA2_SWP_CFG_RPM_SHIFT 12 118 #define DPAA2_SWP_CFG_DCM_SHIFT 10 119 #define DPAA2_SWP_CFG_EPM_SHIFT 8 120 #define DPAA2_SWP_CFG_VPM_SHIFT 7 121 #define DPAA2_SWP_CFG_CPM_SHIFT 6 122 #define DPAA2_SWP_CFG_SD_SHIFT 5 123 #define DPAA2_SWP_CFG_SP_SHIFT 4 124 #define DPAA2_SWP_CFG_SE_SHIFT 3 125 #define DPAA2_SWP_CFG_DP_SHIFT 2 126 #define DPAA2_SWP_CFG_DE_SHIFT 1 127 #define DPAA2_SWP_CFG_EP_SHIFT 0 128 129 /* Static Dequeue Command Register attribute codes */ 130 #define DPAA2_SDQCR_FC_SHIFT 29 /* Dequeue Command Frame Count */ 131 #define DPAA2_SDQCR_FC_MASK 0x1 132 #define DPAA2_SDQCR_DCT_SHIFT 24 /* Dequeue Command Type */ 133 #define DPAA2_SDQCR_DCT_MASK 0x3 134 #define DPAA2_SDQCR_TOK_SHIFT 16 /* Dequeue Command Token */ 135 #define DPAA2_SDQCR_TOK_MASK 0xff 136 #define DPAA2_SDQCR_SRC_SHIFT 0 /* Dequeue Source */ 137 #define DPAA2_SDQCR_SRC_MASK 0xffff 138 139 /* 140 * Read trigger bit is used to trigger QMan to read a command from memory, 141 * without having software perform a cache flush to force a write of the command 142 * to QMan. 143 * 144 * NOTE: Implemented in QBMan 5.0 or above. 145 */ 146 #define DPAA2_SWP_RT_MODE ((uint32_t)0x100) 147 148 /* Interrupt Enable Register bits. */ 149 #define DPAA2_SWP_INTR_EQRI 0x01 150 #define DPAA2_SWP_INTR_EQDI 0x02 151 #define DPAA2_SWP_INTR_DQRI 0x04 152 #define DPAA2_SWP_INTR_RCRI 0x08 153 #define DPAA2_SWP_INTR_RCDI 0x10 154 #define DPAA2_SWP_INTR_VDCI 0x20 155 156 /* "Write Enable" bitmask for a command to configure SWP WQ Channel.*/ 157 #define DPAA2_WQCHAN_WE_EN (0x1u) /* Enable CDAN generation */ 158 #define DPAA2_WQCHAN_WE_ICD (0x2u) /* Interrupt Coalescing Disable */ 159 #define DPAA2_WQCHAN_WE_CTX (0x4u) 160 161 /* Definitions for parsing DQRR entries. */ 162 #define DPAA2_DQRR_RESULT_MASK (0x7Fu) 163 #define DPAA2_DQRR_RESULT_DQ (0x60u) 164 #define DPAA2_DQRR_RESULT_FQRN (0x21u) 165 #define DPAA2_DQRR_RESULT_FQRNI (0x22u) 166 #define DPAA2_DQRR_RESULT_FQPN (0x24u) 167 #define DPAA2_DQRR_RESULT_FQDAN (0x25u) 168 #define DPAA2_DQRR_RESULT_CDAN (0x26u) 169 #define DPAA2_DQRR_RESULT_CSCN_MEM (0x27u) 170 #define DPAA2_DQRR_RESULT_CGCU (0x28u) 171 #define DPAA2_DQRR_RESULT_BPSCN (0x29u) 172 #define DPAA2_DQRR_RESULT_CSCN_WQ (0x2au) 173 174 /* Frame dequeue statuses */ 175 #define DPAA2_DQ_STAT_FQEMPTY (0x80u) /* FQ is empty */ 176 #define DPAA2_DQ_STAT_HELDACTIVE (0x40u) /* FQ is held active */ 177 #define DPAA2_DQ_STAT_FORCEELIGIBLE (0x20u) /* FQ force eligible */ 178 #define DPAA2_DQ_STAT_VALIDFRAME (0x10u) /* valid frame */ 179 #define DPAA2_DQ_STAT_ODPVALID (0x04u) /* FQ ODP enable */ 180 #define DPAA2_DQ_STAT_VOLATILE (0x02u) /* volatile dequeue (VDC) */ 181 #define DPAA2_DQ_STAT_EXPIRED (0x01u) /* VDC is expired */ 182 183 /* 184 * Portal flags. 185 * 186 * TODO: Use the same flags for both MC and software portals. 187 */ 188 #define DPAA2_SWP_DEF 0x0u 189 #define DPAA2_SWP_NOWAIT_ALLOC 0x2u /* Do not sleep during init */ 190 #define DPAA2_SWP_LOCKED 0x4000u /* Wait till portal's unlocked */ 191 #define DPAA2_SWP_DESTROYED 0x8000u /* Terminate any operations */ 192 193 /* Command return codes. */ 194 #define DPAA2_SWP_STAT_OK 0x0 195 #define DPAA2_SWP_STAT_NO_MEMORY 0x9 /* No memory available */ 196 #define DPAA2_SWP_STAT_PORTAL_DISABLED 0xFD /* QBMan portal disabled */ 197 #define DPAA2_SWP_STAT_EINVAL 0xFE /* Invalid argument */ 198 #define DPAA2_SWP_STAT_ERR 0xFF /* General error */ 199 200 #define DPAA2_EQ_DESC_SIZE 32u /* Enqueue Command Descriptor */ 201 #define DPAA2_FDR_DESC_SIZE 32u /* Descriptor of the FDR */ 202 #define DPAA2_FD_SIZE 32u /* Frame Descriptor */ 203 #define DPAA2_FDR_SIZE 64u /* Frame Dequeue Response */ 204 #define DPAA2_SCN_SIZE 16u /* State Change Notification */ 205 #define DPAA2_FA_SIZE 64u /* SW Frame Annotation */ 206 #define DPAA2_SGE_SIZE 16u /* S/G table entry */ 207 #define DPAA2_DQ_SIZE 64u /* Dequeue Response */ 208 #define DPAA2_SWP_CMD_SIZE 64u /* SWP Command */ 209 #define DPAA2_SWP_RSP_SIZE 64u /* SWP Command Response */ 210 211 /* Opaque token for static dequeues. */ 212 #define DPAA2_SWP_SDQCR_TOKEN 0xBBu 213 /* Opaque token for static dequeues. */ 214 #define DPAA2_SWP_VDQCR_TOKEN 0xCCu 215 216 #define DPAA2_SWP_LOCK(__swp, __flags) do { \ 217 mtx_assert(&(__swp)->lock, MA_NOTOWNED); \ 218 mtx_lock(&(__swp)->lock); \ 219 *(__flags) = (__swp)->flags; \ 220 (__swp)->flags |= DPAA2_SWP_LOCKED; \ 221 } while (0) 222 223 #define DPAA2_SWP_UNLOCK(__swp) do { \ 224 mtx_assert(&(__swp)->lock, MA_OWNED); \ 225 (__swp)->flags &= ~DPAA2_SWP_LOCKED; \ 226 mtx_unlock(&(__swp)->lock); \ 227 } while (0) 228 229 enum dpaa2_fd_format { 230 DPAA2_FD_SINGLE = 0, 231 DPAA2_FD_LIST, 232 DPAA2_FD_SG 233 }; 234 235 /** 236 * @brief Enqueue command descriptor. 237 */ 238 struct dpaa2_eq_desc { 239 uint8_t verb; 240 uint8_t dca; 241 uint16_t seqnum; 242 uint16_t orpid; 243 uint16_t _reserved; 244 uint32_t tgtid; 245 uint32_t tag; 246 uint16_t qdbin; 247 uint8_t qpri; 248 uint8_t _reserved1[3]; 249 uint8_t wae; 250 uint8_t rspid; 251 uint64_t rsp_addr; 252 } __packed; 253 CTASSERT(sizeof(struct dpaa2_eq_desc) == DPAA2_EQ_DESC_SIZE); 254 255 /** 256 * @brief Frame Dequeue Response (FDR) descriptor. 257 */ 258 struct dpaa2_fdr_desc { 259 uint8_t verb; 260 uint8_t stat; 261 uint16_t seqnum; 262 uint16_t oprid; 263 uint8_t _reserved; 264 uint8_t tok; 265 uint32_t fqid; 266 uint32_t _reserved1; 267 uint32_t fq_byte_cnt; 268 uint32_t fq_frm_cnt; 269 uint64_t fqd_ctx; 270 } __packed; 271 CTASSERT(sizeof(struct dpaa2_fdr_desc) == DPAA2_FDR_DESC_SIZE); 272 273 /** 274 * @brief State Change Notification Message (SCNM). 275 */ 276 struct dpaa2_scn { 277 uint8_t verb; 278 uint8_t stat; 279 uint8_t state; 280 uint8_t _reserved; 281 uint32_t rid_tok; 282 uint64_t ctx; 283 } __packed; 284 CTASSERT(sizeof(struct dpaa2_scn) == DPAA2_SCN_SIZE); 285 286 /** 287 * @brief DPAA2 frame descriptor. 288 * 289 * addr: Memory address of the start of the buffer holding the 290 * frame data or the buffer containing the scatter/gather 291 * list. 292 * data_length: Length of the frame data (in bytes). 293 * bpid_ivp_bmt: Buffer pool ID (14 bit + BMT bit + IVP bit) 294 * offset_fmt_sl: Frame data offset, frame format and short-length fields. 295 * frame_ctx: Frame context. This field allows the sender of a frame 296 * to communicate some out-of-band information to the 297 * receiver of the frame. 298 * ctrl: Control bits (ERR, CBMT, ASAL, PTAC, DROPP, SC, DD). 299 * flow_ctx: Frame flow context. Associates the frame with a flow 300 * structure. QMan may use the FLC field for 3 purposes: 301 * stashing control, order definition point identification, 302 * and enqueue replication control. 303 */ 304 struct dpaa2_fd { 305 uint64_t addr; 306 uint32_t data_length; 307 uint16_t bpid_ivp_bmt; 308 uint16_t offset_fmt_sl; 309 uint32_t frame_ctx; 310 uint32_t ctrl; 311 uint64_t flow_ctx; 312 } __packed; 313 CTASSERT(sizeof(struct dpaa2_fd) == DPAA2_FD_SIZE); 314 315 /** 316 * @brief DPAA2 frame annotation. 317 */ 318 struct dpaa2_fa { 319 uint32_t magic; 320 struct dpaa2_buf *buf; 321 union { 322 struct { /* Tx frame annotation */ 323 struct dpaa2_ni_tx_ring *tx; 324 }; 325 #ifdef __notyet__ 326 struct { /* Rx frame annotation */ 327 uint64_t _notused; 328 }; 329 #endif 330 }; 331 } __packed; 332 CTASSERT(sizeof(struct dpaa2_fa) <= DPAA2_FA_SIZE); 333 334 /** 335 * @brief DPAA2 scatter/gather entry. 336 */ 337 struct dpaa2_sg_entry { 338 uint64_t addr; 339 uint32_t len; 340 uint16_t bpid; 341 uint16_t offset_fmt; 342 } __packed; 343 CTASSERT(sizeof(struct dpaa2_sg_entry) == DPAA2_SGE_SIZE); 344 345 /** 346 * @brief Frame Dequeue Response (FDR). 347 */ 348 struct dpaa2_fdr { 349 struct dpaa2_fdr_desc desc; 350 struct dpaa2_fd fd; 351 } __packed; 352 CTASSERT(sizeof(struct dpaa2_fdr) == DPAA2_FDR_SIZE); 353 354 /** 355 * @brief Dequeue Response Message. 356 */ 357 struct dpaa2_dq { 358 union { 359 struct { 360 uint8_t verb; 361 uint8_t _reserved[63]; 362 } common; 363 struct dpaa2_fdr fdr; /* Frame Dequeue Response */ 364 struct dpaa2_scn scn; /* State Change Notification */ 365 }; 366 } __packed; 367 CTASSERT(sizeof(struct dpaa2_dq) == DPAA2_DQ_SIZE); 368 369 /** 370 * @brief Descriptor of the QBMan software portal. 371 * 372 * cena_res: Unmapped cache-enabled part of the portal's I/O memory. 373 * cena_map: Mapped cache-enabled part of the portal's I/O memory. 374 * cinh_res: Unmapped cache-inhibited part of the portal's I/O memory. 375 * cinh_map: Mapped cache-inhibited part of the portal's I/O memory. 376 * 377 * dpio_dev: Device associated with the DPIO object to manage this 378 * portal. 379 * swp_version: Hardware IP version of the software portal. 380 * swp_clk: QBMAN clock frequency value in Hz. 381 * swp_cycles_ratio: How many 256 QBMAN cycles fit into one ns. 382 * swp_id: Software portal ID. 383 * 384 * has_notif: True if the notification mode is used. 385 * has_8prio: True for a channel with 8 priority WQs. Ignored unless 386 * "has_notif" is true. 387 */ 388 struct dpaa2_swp_desc { 389 struct resource *cena_res; 390 struct resource_map *cena_map; 391 struct resource *cinh_res; 392 struct resource_map *cinh_map; 393 394 device_t dpio_dev; 395 uint32_t swp_version; 396 uint32_t swp_clk; 397 uint32_t swp_cycles_ratio; 398 uint16_t swp_id; 399 400 bool has_notif; 401 bool has_8prio; 402 }; 403 404 /** 405 * @brief Command holds data to be written to the software portal. 406 */ 407 struct dpaa2_swp_cmd { 408 uint64_t params[DPAA2_SWP_CMD_PARAMS_N]; 409 }; 410 CTASSERT(sizeof(struct dpaa2_swp_cmd) == DPAA2_SWP_CMD_SIZE); 411 412 /** 413 * @brief Command response holds data received from the software portal. 414 */ 415 struct dpaa2_swp_rsp { 416 uint64_t params[DPAA2_SWP_RSP_PARAMS_N]; 417 }; 418 CTASSERT(sizeof(struct dpaa2_swp_rsp) == DPAA2_SWP_RSP_SIZE); 419 420 /** 421 * @brief QBMan software portal. 422 * 423 * res: Unmapped cache-enabled and cache-inhibited parts of the portal. 424 * map: Mapped cache-enabled and cache-inhibited parts of the portal. 425 * desc: Descriptor of the QBMan software portal. 426 * lock: Lock to guard an access to the portal. 427 * cv: Conditional variable helps to wait for the helper object's state 428 * change. 429 * flags: Current state of the object. 430 * sdq: Push dequeues status. 431 * mc: Management commands data. 432 * mr: Management response data. 433 * dqrr: Dequeue Response Ring is used to issue frame dequeue responses 434 * from the QBMan to the driver. 435 * eqcr: Enqueue Command Ring is used to issue frame enqueue commands 436 * from the driver to the QBMan. 437 */ 438 struct dpaa2_swp { 439 struct resource *cena_res; 440 struct resource_map *cena_map; 441 struct resource *cinh_res; 442 struct resource_map *cinh_map; 443 444 struct mtx lock; 445 struct dpaa2_swp_desc *desc; 446 uint16_t flags; 447 448 /* Static Dequeue Command Register value (to obtain CDANs). */ 449 uint32_t sdq; 450 451 /* Volatile Dequeue Command (to obtain frames). */ 452 struct { 453 uint32_t valid_bit; /* 0x00 or 0x80 */ 454 } vdq; 455 456 struct { 457 bool atomic; 458 bool writes_cinh; 459 bool mem_backed; 460 } cfg; /* Software portal configuration. */ 461 462 struct { 463 uint32_t valid_bit; /* 0x00 or 0x80 */ 464 } mc; 465 466 struct { 467 uint32_t valid_bit; /* 0x00 or 0x80 */ 468 } mr; 469 470 struct { 471 uint32_t next_idx; 472 uint32_t valid_bit; 473 uint8_t ring_size; 474 bool reset_bug; /* dqrr reset workaround */ 475 uint32_t irq_threshold; 476 uint32_t irq_itp; 477 } dqrr; 478 479 struct { 480 uint32_t pi; /* producer index */ 481 uint32_t pi_vb; /* PI valid bits */ 482 uint32_t pi_ring_size; 483 uint32_t pi_ci_mask; 484 uint32_t ci; 485 int available; 486 uint32_t pend; 487 uint32_t no_pfdr; 488 } eqcr; 489 }; 490 491 /* Management routines. */ 492 int dpaa2_swp_init_portal(struct dpaa2_swp **swp, struct dpaa2_swp_desc *desc, 493 uint16_t flags); 494 void dpaa2_swp_free_portal(struct dpaa2_swp *swp); 495 uint32_t dpaa2_swp_set_cfg(uint8_t max_fill, uint8_t wn, uint8_t est, 496 uint8_t rpm, uint8_t dcm, uint8_t epm, int sd, int sp, int se, int dp, 497 int de, int ep); 498 499 /* Read/write registers of a software portal. */ 500 void dpaa2_swp_write_reg(struct dpaa2_swp *swp, uint32_t o, uint32_t v); 501 uint32_t dpaa2_swp_read_reg(struct dpaa2_swp *swp, uint32_t o); 502 503 /* Helper routines. */ 504 void dpaa2_swp_set_ed_norp(struct dpaa2_eq_desc *ed, bool resp_always); 505 void dpaa2_swp_set_ed_fq(struct dpaa2_eq_desc *ed, uint32_t fqid); 506 void dpaa2_swp_set_intr_trigger(struct dpaa2_swp *swp, uint32_t mask); 507 uint32_t dpaa2_swp_get_intr_trigger(struct dpaa2_swp *swp); 508 uint32_t dpaa2_swp_read_intr_status(struct dpaa2_swp *swp); 509 void dpaa2_swp_clear_intr_status(struct dpaa2_swp *swp, uint32_t mask); 510 void dpaa2_swp_set_push_dequeue(struct dpaa2_swp *swp, uint8_t chan_idx, 511 bool en); 512 int dpaa2_swp_set_irq_coalescing(struct dpaa2_swp *swp, uint32_t threshold, 513 uint32_t holdoff); 514 515 /* Software portal commands. */ 516 int dpaa2_swp_conf_wq_channel(struct dpaa2_swp *swp, uint16_t chan_id, 517 uint8_t we_mask, bool cdan_en, uint64_t ctx); 518 int dpaa2_swp_query_bp(struct dpaa2_swp *swp, uint16_t bpid, 519 struct dpaa2_bp_conf *conf); 520 int dpaa2_swp_release_bufs(struct dpaa2_swp *swp, uint16_t bpid, bus_addr_t *buf, 521 uint32_t buf_num); 522 int dpaa2_swp_dqrr_next_locked(struct dpaa2_swp *swp, struct dpaa2_dq *dq, 523 uint32_t *idx); 524 int dpaa2_swp_pull(struct dpaa2_swp *swp, uint16_t chan_id, 525 struct dpaa2_buf *buf, uint32_t frames_n); 526 int dpaa2_swp_enq(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed, 527 struct dpaa2_fd *fd); 528 int dpaa2_swp_enq_mult(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed, 529 struct dpaa2_fd *fd, uint32_t *flags, int frames_n); 530 531 #endif /* _DPAA2_SWP_H */ 532