1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2023 Dmitry Salychev 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _DPAA2_SWP_H 29 #define _DPAA2_SWP_H 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include "dpaa2_types.h" 36 #include "dpaa2_buf.h" 37 #include "dpaa2_bp.h" 38 #include "dpaa2_frame.h" 39 40 /* 41 * DPAA2 QBMan software portal. 42 */ 43 44 /* All QBMan commands and result structures use this "valid bit" encoding. */ 45 #define DPAA2_SWP_VALID_BIT ((uint32_t) 0x80) 46 47 #define DPAA2_SWP_TIMEOUT 100000 /* in us */ 48 #define DPAA2_SWP_CMD_PARAMS_N 8u 49 #define DPAA2_SWP_RSP_PARAMS_N 8u 50 51 /* 52 * Maximum number of buffers that can be acquired/released through a single 53 * QBMan command. 54 */ 55 #define DPAA2_SWP_BUFS_PER_CMD 7u 56 57 /* 58 * Number of times to retry DPIO portal operations while waiting for portal to 59 * finish executing current command and become available. 60 * 61 * We want to avoid being stuck in a while loop in case hardware becomes 62 * unresponsive, but not give up too easily if the portal really is busy for 63 * valid reasons. 64 */ 65 #define DPAA2_SWP_BUSY_RETRIES 1000 66 67 /* Versions of the QBMan software portals. */ 68 #define DPAA2_SWP_REV_4000 0x04000000 69 #define DPAA2_SWP_REV_4100 0x04010000 70 #define DPAA2_SWP_REV_4101 0x04010001 71 #define DPAA2_SWP_REV_5000 0x05000000 72 73 #define DPAA2_SWP_REV_MASK 0xFFFF0000 74 75 /* Registers in the cache-inhibited area of the software portal. */ 76 #define DPAA2_SWP_CINH_CR 0x600 /* Management Command reg.*/ 77 #define DPAA2_SWP_CINH_EQCR_PI 0x800 /* Enqueue Ring, Producer Index */ 78 #define DPAA2_SWP_CINH_EQCR_CI 0x840 /* Enqueue Ring, Consumer Index */ 79 #define DPAA2_SWP_CINH_CR_RT 0x900 /* CR Read Trigger */ 80 #define DPAA2_SWP_CINH_VDQCR_RT 0x940 /* VDQCR Read Trigger */ 81 #define DPAA2_SWP_CINH_EQCR_AM_RT 0x980 82 #define DPAA2_SWP_CINH_RCR_AM_RT 0x9C0 83 #define DPAA2_SWP_CINH_DQPI 0xA00 /* DQRR Producer Index reg. */ 84 #define DPAA2_SWP_CINH_DQRR_ITR 0xA80 /* DQRR interrupt timeout reg. */ 85 #define DPAA2_SWP_CINH_DCAP 0xAC0 /* DQRR Consumption Ack. reg. */ 86 #define DPAA2_SWP_CINH_SDQCR 0xB00 /* Static Dequeue Command reg. */ 87 #define DPAA2_SWP_CINH_EQCR_AM_RT2 0xB40 88 #define DPAA2_SWP_CINH_RCR_PI 0xC00 /* Release Ring, Producer Index */ 89 #define DPAA2_SWP_CINH_RAR 0xCC0 /* Release Array Allocation reg. */ 90 #define DPAA2_SWP_CINH_CFG 0xD00 91 #define DPAA2_SWP_CINH_ISR 0xE00 92 #define DPAA2_SWP_CINH_IER 0xE40 93 #define DPAA2_SWP_CINH_ISDR 0xE80 94 #define DPAA2_SWP_CINH_IIR 0xEC0 95 #define DPAA2_SWP_CINH_ITPR 0xF40 96 97 /* Registers in the cache-enabled area of the software portal. */ 98 #define DPAA2_SWP_CENA_EQCR(n) (0x000 + ((uint32_t)(n) << 6)) 99 #define DPAA2_SWP_CENA_DQRR(n) (0x200 + ((uint32_t)(n) << 6)) 100 #define DPAA2_SWP_CENA_RCR(n) (0x400 + ((uint32_t)(n) << 6)) 101 #define DPAA2_SWP_CENA_CR (0x600) /* Management Command reg. */ 102 #define DPAA2_SWP_CENA_RR(vb) (0x700 + ((uint32_t)(vb) >> 1)) 103 #define DPAA2_SWP_CENA_VDQCR (0x780) 104 #define DPAA2_SWP_CENA_EQCR_CI (0x840) 105 106 /* Registers in the cache-enabled area of the software portal (memory-backed). */ 107 #define DPAA2_SWP_CENA_DQRR_MEM(n) (0x0800 + ((uint32_t)(n) << 6)) 108 #define DPAA2_SWP_CENA_RCR_MEM(n) (0x1400 + ((uint32_t)(n) << 6)) 109 #define DPAA2_SWP_CENA_CR_MEM (0x1600) /* Management Command reg. */ 110 #define DPAA2_SWP_CENA_RR_MEM (0x1680) /* Management Response reg. */ 111 #define DPAA2_SWP_CENA_VDQCR_MEM (0x1780) 112 #define DPAA2_SWP_CENA_EQCR_CI_MEMBACK (0x1840) 113 114 /* Shifts in the portal's configuration register. */ 115 #define DPAA2_SWP_CFG_DQRR_MF_SHIFT 20 116 #define DPAA2_SWP_CFG_EST_SHIFT 16 117 #define DPAA2_SWP_CFG_CPBS_SHIFT 15 118 #define DPAA2_SWP_CFG_WN_SHIFT 14 119 #define DPAA2_SWP_CFG_RPM_SHIFT 12 120 #define DPAA2_SWP_CFG_DCM_SHIFT 10 121 #define DPAA2_SWP_CFG_EPM_SHIFT 8 122 #define DPAA2_SWP_CFG_VPM_SHIFT 7 123 #define DPAA2_SWP_CFG_CPM_SHIFT 6 124 #define DPAA2_SWP_CFG_SD_SHIFT 5 125 #define DPAA2_SWP_CFG_SP_SHIFT 4 126 #define DPAA2_SWP_CFG_SE_SHIFT 3 127 #define DPAA2_SWP_CFG_DP_SHIFT 2 128 #define DPAA2_SWP_CFG_DE_SHIFT 1 129 #define DPAA2_SWP_CFG_EP_SHIFT 0 130 131 /* Static Dequeue Command Register attribute codes */ 132 #define DPAA2_SDQCR_FC_SHIFT 29 /* Dequeue Command Frame Count */ 133 #define DPAA2_SDQCR_FC_MASK 0x1 134 #define DPAA2_SDQCR_DCT_SHIFT 24 /* Dequeue Command Type */ 135 #define DPAA2_SDQCR_DCT_MASK 0x3 136 #define DPAA2_SDQCR_TOK_SHIFT 16 /* Dequeue Command Token */ 137 #define DPAA2_SDQCR_TOK_MASK 0xff 138 #define DPAA2_SDQCR_SRC_SHIFT 0 /* Dequeue Source */ 139 #define DPAA2_SDQCR_SRC_MASK 0xffff 140 141 /* 142 * Read trigger bit is used to trigger QMan to read a command from memory, 143 * without having software perform a cache flush to force a write of the command 144 * to QMan. 145 * 146 * NOTE: Implemented in QBMan 5.0 or above. 147 */ 148 #define DPAA2_SWP_RT_MODE ((uint32_t)0x100) 149 150 /* Interrupt Enable Register bits. */ 151 #define DPAA2_SWP_INTR_EQRI 0x01 152 #define DPAA2_SWP_INTR_EQDI 0x02 153 #define DPAA2_SWP_INTR_DQRI 0x04 154 #define DPAA2_SWP_INTR_RCRI 0x08 155 #define DPAA2_SWP_INTR_RCDI 0x10 156 #define DPAA2_SWP_INTR_VDCI 0x20 157 158 /* "Write Enable" bitmask for a command to configure SWP WQ Channel.*/ 159 #define DPAA2_WQCHAN_WE_EN (0x1u) /* Enable CDAN generation */ 160 #define DPAA2_WQCHAN_WE_ICD (0x2u) /* Interrupt Coalescing Disable */ 161 #define DPAA2_WQCHAN_WE_CTX (0x4u) 162 163 /* Definitions for parsing DQRR entries. */ 164 #define DPAA2_DQRR_RESULT_MASK (0x7Fu) 165 #define DPAA2_DQRR_RESULT_DQ (0x60u) 166 #define DPAA2_DQRR_RESULT_FQRN (0x21u) 167 #define DPAA2_DQRR_RESULT_FQRNI (0x22u) 168 #define DPAA2_DQRR_RESULT_FQPN (0x24u) 169 #define DPAA2_DQRR_RESULT_FQDAN (0x25u) 170 #define DPAA2_DQRR_RESULT_CDAN (0x26u) 171 #define DPAA2_DQRR_RESULT_CSCN_MEM (0x27u) 172 #define DPAA2_DQRR_RESULT_CGCU (0x28u) 173 #define DPAA2_DQRR_RESULT_BPSCN (0x29u) 174 #define DPAA2_DQRR_RESULT_CSCN_WQ (0x2au) 175 176 /* Frame dequeue statuses */ 177 #define DPAA2_DQ_STAT_FQEMPTY (0x80u) /* FQ is empty */ 178 #define DPAA2_DQ_STAT_HELDACTIVE (0x40u) /* FQ is held active */ 179 #define DPAA2_DQ_STAT_FORCEELIGIBLE (0x20u) /* FQ force eligible */ 180 #define DPAA2_DQ_STAT_VALIDFRAME (0x10u) /* valid frame */ 181 #define DPAA2_DQ_STAT_ODPVALID (0x04u) /* FQ ODP enable */ 182 #define DPAA2_DQ_STAT_VOLATILE (0x02u) /* volatile dequeue (VDC) */ 183 #define DPAA2_DQ_STAT_EXPIRED (0x01u) /* VDC is expired */ 184 185 /* 186 * Portal flags. 187 * 188 * TODO: Use the same flags for both MC and software portals. 189 */ 190 #define DPAA2_SWP_DEF 0x0u 191 #define DPAA2_SWP_NOWAIT_ALLOC 0x2u /* Do not sleep during init */ 192 #define DPAA2_SWP_LOCKED 0x4000u /* Wait till portal's unlocked */ 193 #define DPAA2_SWP_DESTROYED 0x8000u /* Terminate any operations */ 194 195 /* Command return codes. */ 196 #define DPAA2_SWP_STAT_OK 0x0 197 #define DPAA2_SWP_STAT_NO_MEMORY 0x9 /* No memory available */ 198 #define DPAA2_SWP_STAT_PORTAL_DISABLED 0xFD /* QBMan portal disabled */ 199 #define DPAA2_SWP_STAT_EINVAL 0xFE /* Invalid argument */ 200 #define DPAA2_SWP_STAT_ERR 0xFF /* General error */ 201 202 #define DPAA2_EQ_DESC_SIZE 32u /* Enqueue Command Descriptor */ 203 #define DPAA2_FDR_DESC_SIZE 32u /* Descriptor of the FDR */ 204 #define DPAA2_FDR_SIZE 64u /* Frame Dequeue Response */ 205 #define DPAA2_SCN_SIZE 16u /* State Change Notification */ 206 #define DPAA2_SGE_SIZE 16u /* S/G table entry */ 207 #define DPAA2_DQ_SIZE 64u /* Dequeue Response */ 208 #define DPAA2_SWP_CMD_SIZE 64u /* SWP Command */ 209 #define DPAA2_SWP_RSP_SIZE 64u /* SWP Command Response */ 210 211 /* Opaque token for static dequeues. */ 212 #define DPAA2_SWP_SDQCR_TOKEN 0xBBu 213 /* Opaque token for static dequeues. */ 214 #define DPAA2_SWP_VDQCR_TOKEN 0xCCu 215 216 #define DPAA2_SWP_LOCK(__swp, __flags) do { \ 217 mtx_assert(&(__swp)->lock, MA_NOTOWNED); \ 218 mtx_lock(&(__swp)->lock); \ 219 *(__flags) = (__swp)->flags; \ 220 (__swp)->flags |= DPAA2_SWP_LOCKED; \ 221 } while (0) 222 223 #define DPAA2_SWP_UNLOCK(__swp) do { \ 224 mtx_assert(&(__swp)->lock, MA_OWNED); \ 225 (__swp)->flags &= ~DPAA2_SWP_LOCKED; \ 226 mtx_unlock(&(__swp)->lock); \ 227 } while (0) 228 229 enum dpaa2_fd_format { 230 DPAA2_FD_SINGLE = 0, 231 DPAA2_FD_LIST, 232 DPAA2_FD_SG 233 }; 234 235 /** 236 * Forward declaration to avoid circular include. 237 */ 238 struct dpaa2_io_softc; 239 240 /** 241 * @brief Enqueue command descriptor. 242 */ 243 struct dpaa2_eq_desc { 244 uint8_t verb; 245 uint8_t dca; 246 uint16_t seqnum; 247 uint16_t orpid; 248 uint16_t _reserved; 249 uint32_t tgtid; 250 uint32_t tag; 251 uint16_t qdbin; 252 uint8_t qpri; 253 uint8_t _reserved1[3]; 254 uint8_t wae; 255 uint8_t rspid; 256 uint64_t rsp_addr; 257 } __packed; 258 CTASSERT(sizeof(struct dpaa2_eq_desc) == DPAA2_EQ_DESC_SIZE); 259 260 /** 261 * @brief Frame Dequeue Response (FDR) descriptor. 262 */ 263 struct dpaa2_fdr_desc { 264 uint8_t verb; 265 uint8_t stat; 266 uint16_t seqnum; 267 uint16_t oprid; 268 uint8_t _reserved; 269 uint8_t tok; 270 uint32_t fqid; 271 uint32_t _reserved1; 272 uint32_t fq_byte_cnt; 273 uint32_t fq_frm_cnt; 274 uint64_t fqd_ctx; 275 } __packed; 276 CTASSERT(sizeof(struct dpaa2_fdr_desc) == DPAA2_FDR_DESC_SIZE); 277 278 /** 279 * @brief State Change Notification Message (SCNM). 280 */ 281 struct dpaa2_scn { 282 uint8_t verb; 283 uint8_t stat; 284 uint8_t state; 285 uint8_t _reserved; 286 uint32_t rid_tok; 287 uint64_t ctx; 288 } __packed; 289 CTASSERT(sizeof(struct dpaa2_scn) == DPAA2_SCN_SIZE); 290 291 /** 292 * @brief DPAA2 scatter/gather entry. 293 */ 294 struct dpaa2_sg_entry { 295 uint64_t addr; 296 uint32_t len; 297 uint16_t bpid; 298 uint16_t offset_fmt; 299 } __packed; 300 CTASSERT(sizeof(struct dpaa2_sg_entry) == DPAA2_SGE_SIZE); 301 302 /** 303 * @brief Frame Dequeue Response (FDR). 304 */ 305 struct dpaa2_fdr { 306 struct dpaa2_fdr_desc desc; 307 struct dpaa2_fd fd; 308 } __packed; 309 CTASSERT(sizeof(struct dpaa2_fdr) == DPAA2_FDR_SIZE); 310 311 /** 312 * @brief Dequeue Response Message. 313 */ 314 struct dpaa2_dq { 315 union { 316 struct { 317 uint8_t verb; 318 uint8_t _reserved[63]; 319 } common; 320 struct dpaa2_fdr fdr; /* Frame Dequeue Response */ 321 struct dpaa2_scn scn; /* State Change Notification */ 322 }; 323 } __packed; 324 CTASSERT(sizeof(struct dpaa2_dq) == DPAA2_DQ_SIZE); 325 326 /** 327 * @brief Descriptor of the QBMan software portal. 328 * 329 * cena_res: Unmapped cache-enabled part of the portal's I/O memory. 330 * cena_map: Mapped cache-enabled part of the portal's I/O memory. 331 * cinh_res: Unmapped cache-inhibited part of the portal's I/O memory. 332 * cinh_map: Mapped cache-inhibited part of the portal's I/O memory. 333 * 334 * dpio_dev: Device associated with the DPIO object to manage this 335 * portal. 336 * swp_version: Hardware IP version of the software portal. 337 * swp_clk: QBMAN clock frequency value in Hz. 338 * swp_cycles_ratio: How many 256 QBMAN cycles fit into one ns. 339 * swp_id: Software portal ID. 340 * 341 * has_notif: True if the notification mode is used. 342 * has_8prio: True for a channel with 8 priority WQs. Ignored unless 343 * "has_notif" is true. 344 */ 345 struct dpaa2_swp_desc { 346 struct resource *cena_res; 347 struct resource_map *cena_map; 348 struct resource *cinh_res; 349 struct resource_map *cinh_map; 350 351 device_t dpio_dev; 352 uint32_t swp_version; 353 uint32_t swp_clk; 354 uint32_t swp_cycles_ratio; 355 uint16_t swp_id; 356 357 bool has_notif; 358 bool has_8prio; 359 }; 360 361 /** 362 * @brief Command holds data to be written to the software portal. 363 */ 364 struct dpaa2_swp_cmd { 365 uint64_t params[DPAA2_SWP_CMD_PARAMS_N]; 366 }; 367 CTASSERT(sizeof(struct dpaa2_swp_cmd) == DPAA2_SWP_CMD_SIZE); 368 369 /** 370 * @brief Command response holds data received from the software portal. 371 */ 372 struct dpaa2_swp_rsp { 373 uint64_t params[DPAA2_SWP_RSP_PARAMS_N]; 374 }; 375 CTASSERT(sizeof(struct dpaa2_swp_rsp) == DPAA2_SWP_RSP_SIZE); 376 377 /** 378 * @brief QBMan software portal. 379 * 380 * res: Unmapped cache-enabled and cache-inhibited parts of the portal. 381 * map: Mapped cache-enabled and cache-inhibited parts of the portal. 382 * desc: Descriptor of the QBMan software portal. 383 * lock: Lock to guard an access to the portal. 384 * cv: Conditional variable helps to wait for the helper object's state 385 * change. 386 * flags: Current state of the object. 387 * sdq: Push dequeues status. 388 * mc: Management commands data. 389 * mr: Management response data. 390 * dqrr: Dequeue Response Ring is used to issue frame dequeue responses 391 * from the QBMan to the driver. 392 * eqcr: Enqueue Command Ring is used to issue frame enqueue commands 393 * from the driver to the QBMan. 394 */ 395 struct dpaa2_swp { 396 struct resource *cena_res; 397 struct resource_map *cena_map; 398 struct resource *cinh_res; 399 struct resource_map *cinh_map; 400 401 struct mtx lock; 402 struct dpaa2_swp_desc *desc; 403 uint16_t flags; 404 405 /* Static Dequeue Command Register value (to obtain CDANs). */ 406 uint32_t sdq; 407 408 /* Volatile Dequeue Command (to obtain frames). */ 409 struct { 410 uint32_t valid_bit; /* 0x00 or 0x80 */ 411 } vdq; 412 413 struct { 414 bool atomic; 415 bool writes_cinh; 416 bool mem_backed; 417 } cfg; /* Software portal configuration. */ 418 419 struct { 420 uint32_t valid_bit; /* 0x00 or 0x80 */ 421 } mc; 422 423 struct { 424 uint32_t valid_bit; /* 0x00 or 0x80 */ 425 } mr; 426 427 struct { 428 uint32_t next_idx; 429 uint32_t valid_bit; 430 uint8_t ring_size; 431 bool reset_bug; /* dqrr reset workaround */ 432 uint32_t irq_threshold; 433 uint32_t irq_itp; 434 } dqrr; 435 436 struct { 437 uint32_t pi; /* producer index */ 438 uint32_t pi_vb; /* PI valid bits */ 439 uint32_t pi_ring_size; 440 uint32_t pi_ci_mask; 441 uint32_t ci; 442 int available; 443 uint32_t pend; 444 uint32_t no_pfdr; 445 } eqcr; 446 }; 447 448 /* Management routines. */ 449 int dpaa2_swp_init_portal(struct dpaa2_io_softc *softc, uint16_t flags); 450 void dpaa2_swp_free_portal(struct dpaa2_swp *swp); 451 uint32_t dpaa2_swp_set_cfg(uint8_t max_fill, uint8_t wn, uint8_t est, 452 uint8_t rpm, uint8_t dcm, uint8_t epm, int sd, int sp, int se, int dp, 453 int de, int ep); 454 455 /* Read/write registers of a software portal. */ 456 void dpaa2_swp_write_reg(struct dpaa2_swp *swp, uint32_t o, uint32_t v); 457 uint32_t dpaa2_swp_read_reg(struct dpaa2_swp *swp, uint32_t o); 458 459 /* Helper routines. */ 460 void dpaa2_swp_set_ed_norp(struct dpaa2_eq_desc *ed, bool resp_always); 461 void dpaa2_swp_set_ed_fq(struct dpaa2_eq_desc *ed, uint32_t fqid); 462 void dpaa2_swp_set_intr_trigger(struct dpaa2_swp *swp, uint32_t mask); 463 uint32_t dpaa2_swp_get_intr_trigger(struct dpaa2_swp *swp); 464 uint32_t dpaa2_swp_read_intr_status(struct dpaa2_swp *swp); 465 void dpaa2_swp_clear_intr_status(struct dpaa2_swp *swp, uint32_t mask); 466 void dpaa2_swp_set_push_dequeue(struct dpaa2_swp *swp, uint8_t chan_idx, 467 bool en); 468 int dpaa2_swp_set_irq_coalescing(struct dpaa2_swp *swp, uint32_t threshold, 469 uint32_t holdoff); 470 471 /* Software portal commands. */ 472 int dpaa2_swp_conf_wq_channel(struct dpaa2_swp *swp, uint16_t chan_id, 473 uint8_t we_mask, bool cdan_en, uint64_t ctx); 474 int dpaa2_swp_query_bp(struct dpaa2_swp *swp, uint16_t bpid, 475 struct dpaa2_bp_conf *conf); 476 int dpaa2_swp_release_bufs(struct dpaa2_swp *swp, uint16_t bpid, bus_addr_t *buf, 477 uint32_t buf_num); 478 int dpaa2_swp_dqrr_next_locked(struct dpaa2_swp *swp, struct dpaa2_dq *dq, 479 uint32_t *idx); 480 int dpaa2_swp_pull(struct dpaa2_swp *swp, uint16_t chan_id, 481 struct dpaa2_buf *buf, uint32_t frames_n); 482 int dpaa2_swp_enq(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed, 483 struct dpaa2_fd *fd); 484 int dpaa2_swp_enq_mult(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed, 485 struct dpaa2_fd *fd, uint32_t *flags, int frames_n); 486 487 #endif /* _DPAA2_SWP_H */ 488